Introduction to

VLSI Design
LECTURE# 01
VLSI DESIGN

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 1

Introduction
Course Title: VLSI Design
Course Code:EEE434
Class: EEE-6
Course Instructor: Saad Arslan
Lab Instructor: Saad Arslan
Contact me at
◦ saad.arslan@comsats.edu.pk (please be careful with spellings)

Text Book
◦ Introduction to VLSI Circuits and Systems
◦ By John P. Uyemura

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 2

Introduction to VLSI
VLSI is an acronym for Very Large Scale Integration
◦ Very dense electronic Integrated Circuits (ICs)
◦ Large number of switching devices (transistor) per unit area
The number of transistors has exceeded 1 billion per chip (IC)1
◦ Nowadays up to tens of billions2
Year Era Level of Integration
1958 Single Transistor -
1960 Monolithic IC 1
1962 Multi-function 2-4
1964 Complex function 5-20
1967 Medium scale integration MSI 20-200
1972 Large scale integration LSI 200-2000
1978 Very large scale integration VLSI 2000-20,000
1989 Ultra large scale integration ULSI Above 20,000
1Peter Clarke, EE Times, “Intel enters billion-transistor processor era”, 14 October 2005
2Antone Gonsalves, EE Times, "Samsung begins production of 16-Gb flash", 30 April 2007

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Introduction to VLSI cont.
In order to achieve higher integration density
◦ Transistor sizes are being decreased (scaling)
◦ Transistor scaling is usually referred by channel length

Transistor scaling has also raised some issues along with the benefits
◦ Power density
◦ Velocity saturation
◦ Other short channel effects
Parameter Trends Transistor scaling
Number of transistors per IC Increasing and operating
frequency reaching
Transistor size Decreasing
its limits.
Operating frequency (speed) Increasing New solutions are
Operating voltage Decreasing (to decrease power consumption) being adopted.

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 4

VLSI Complexity and Design
As the integration density increases Mostly top-down approach
◦ It also increases design complexity Bottom-up is only feasible for small projects
Top
design System Specifications Initial concept
So, it is required to have level

◦ Design team Abstract high-level model System design

◦ Design hierarchy Engineers VHDL, Verilog HDL and verification

Sand Logic design

Logic Synthesis and verification
Marketing
Idea
$$$$$$$ CMOS design
Circuit Design and verification
Bottom
design Physical Design Silicon logic design
level and verification

Mass production,
Manufacturing testing &
packaging

Super chip Finished VLSI Chip Marketing

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 5

VLSI Chip Types
Full Custom
◦ Every circuit is custom designed
◦ Time consuming, high initial cost
◦ Suitable for mass-production
Application Specific Integrated Circuits (ASICs)
◦ ICs for a particular application
◦ Designers use CAD tools to translate higher level design to create layout
◦ No access over low-level electronics design
◦ Suitable for low-production and prototyping
◦ May involve using IP cores
Semi-Custom
◦ Hybrid of the above two
◦ Using standard cells and custom designed circuit

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 6

System-on-Chip
A designed IC will be required to interface with other components
◦ Microprocessor with RAM etc
◦ Multiples ICs are connected on a PC
Current integration levels allows us to implement
◦ Complete systems within a single chip, called System-on-chip
◦ Like a microcontroller
We can implement very large silicon chips as well
◦ However, the defects in the silicon crystal may render entire chip useless
◦ Large the silicon area, higher the probability of defects.
◦ So, yes there is a trade-off between size and yield
So far we are shrinking transistor size to increase number of transistors
◦ Channel length is the measure used to define a fabrication process
◦ 0.13-um process means the channel length is 130 nm (0.13 micron)

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 7

 Moore’s Law
Gordon Moore suggested

http://www.cringely.com/2013/10/15/breaki
that the number of

ng-moores-law/ 2016-02-09 at 1100 hrs

transistors in an IC
◦ Will double every 18 to 24
months

So far, the Moore’s law is

holding, some what

Image courtesy
◦ But it is also struggling
◦ As Gordon Moore himself
said in 2015 1
◦ “I guess I see Moore’s law dying
here in the next decade or so,
but that’s not surprising.”

1Moore, Gordon. “Gordon Moore: The Man Whose Name Means Progress, The visionary engineer
reflects on 50 years of Moore’s Law”, March 30, 2015

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 8

Logic Design Using MOSFETs
Ideal Switches
Assert-high controlled switch 𝑦=𝑥
𝐴=0 if and only if 𝐴 = 1
𝐴=1

𝑥 𝑦 𝑥 𝑦=𝑥
Open Closed

Assert-low controlled switch

𝐴=0 𝑦=𝑥 𝐴=1

if and only if 𝐴 = 0
𝑥 𝑦=x 𝑥 𝑦
Closed Open

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 9

Ideal Switches (Assert High)
Logic gates
AND gate (switches in series)
𝑎 𝑏 𝑔=𝑎⋅𝑏
if and only if 𝑎 = 𝑏 = 1

1 𝑔 =𝑎⋅𝑏
Input a.1 𝑎⋅1 ⋅𝑏 Output

OR Gate (switches in parallel)

𝑎

𝑎⋅1
𝑓 =𝑎+𝑏
𝑏 if and only if 𝑎 = 1 or 𝑏 = 1
+

1 𝑓 =𝑎+𝑏
𝑏⋅1

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 10

Ideal Switches (Assert Low)
Logic gates
NOR gate
𝑎 𝑏

1 ℎ = 𝑎ത ⋅ 𝑏ത = 𝑎 + 𝑏
Input 𝑎ത ⋅ 1 𝑎ത ⋅ 1 ⋅ 𝑏ത Output

NAND gate
𝑎

𝑎ത ⋅ 1

𝑏 +

1 𝑗 = 𝑎ത + 𝑏ത = 𝑎 ⋅ 𝑏
𝑏ത ⋅ 1

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 11

Ideal Switches
Logic gates (NOT)
𝑎
NOT gate
𝑎ത ⋅ 1
1

Inputs 𝑎 + 𝑦 = 𝑎ത ⋅ 1 + 𝑎 ⋅ 0 = 𝑎ത
Output
0
𝑎⋅0

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 12

MOSFETs as Switches
MOSFETs somewhat behave like an ideal switch
◦ nMOS as assert-high switch (closed for Gate = 1)
◦ pMOS as assert-low switch (closed for Gate = 0)
Gate Gate

Logic definitions
V
Source Drain Source Drain
nMOS pMOS VDD
Logic
High
Modern designs require single power supply
◦ 𝑉𝑆𝑆 = 𝐺𝑁𝐷 = 0 V
Undefined
◦ 𝑉𝐷𝐷 = 5 V, 3 V or less
Logic
Low
0V

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 13

 MOSFETs as Switches
MOSFET Threshold Voltages
An n-channel MOSFET conducts when
◦ Gate to Source Voltage are greater than threshold voltage (𝑉𝐺𝑆𝑛 ≥ 𝑉𝑇𝑛 )

An p-channel MOSFET conducts when

◦ Gate to Source Voltage are greater than threshold voltage (𝑉𝑆𝐺𝑝 ≥ 𝑉𝑇𝑝 )
Complementary
VDD
to VDD VA
VA + Source
VGSp VDD A=1
Drain VDD
pMOS Off
̶ (VDD ̶ |VTp|)
VA pMOS
Gate A=1 Gate
VA nMOS nMOS On A=0
+ pMOS On
Drain
VGSn VTn
̶ Source A=0
0V
0V nMOS Off to ground

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 14

 MOSFETs as Switches
nMOS Pass Characteristics
nMOS switch is closed when 𝑉𝐴 = 𝑉𝐷𝐷
When 𝑉𝑥 = 0 V nMOS can pass
◦ 𝑉𝑦 = 0 V, because the switch is always conducting Strong logic 0
Weak logic 1
When 𝑉𝑥 = 𝑉𝐷𝐷
◦ 𝑉𝑦 = 𝑉1 , because the switch is turn-off when 𝑉𝐺𝑆 or 𝑉𝐺𝐷 falls below 𝑉𝑇𝑛
VDD VDD
+
VTn
Input Output Input Output
̶
+ + + +
Vx = 0 V Vy = 0 V Vx = VDD Vy = (VDD ̶ VTn) = V1
̶ ̶ ̶ ̶

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 15

 MOSFETs as Switches
pMOS Pass Characteristics
pMOS switch is closed when 𝑉𝐴 = 0 V
When 𝑉𝑥 = 𝑉𝐷𝐷 pMOS can pass
◦ 𝑉𝑦 = 𝑉𝐷𝐷 , because the switch is always conducting Strong logic 1
Weak logic 0
When 𝑉𝑥 = 0 V
◦ The switch cannot drive output below 𝑉1 , because the switch is turn-off
when 𝑉𝑆𝐺 or 𝑉𝐷𝐺 falls below 𝑉𝑇𝑛
̶
|VTp|
Input Output Input Output
+
+ + + +
Vx = VDD Vy = VDD Vx = 0 V Vy = |VTp| = V0
̶ ̶ ̶ ̶

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 16

MOSFETs as Switches
Pass Characteristics
In order to successfully pass logic low and logic high
◦ We use CMOS circuits
pMOS can pass
Where Strong logic 1
◦ nMOS is used to pass logic low (drive output low) Weak logic 0
◦ pMOS is used to pass logic high (drive output high)

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 17

Design Metrics
The design quality is measured in terms of the following design metrics
◦ Functionality
◦ What operations it can perform of number of I/Os etc.
◦ Cost (non-recurring and recurring)
◦ NRE (Non-Recurrent Engineering) costs
◦ One time cost factor like design time, design effort and mask generation etc.
◦ R&D, Infrastructure building, training, manufacturing equipment, VLSI CAD tools
◦ Recurrent Costs
◦ Proportional to volume, chip area
◦ Silicon processing, packaging, testing
◦ Reliability
◦ noise margin/immunity

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 18

Design Metrics cont.
◦ Power dissipation (speed, power, energy)
◦ Peak and average power dissipation,
◦ Energy Power-delay Product (PDP)
◦ Speed (delay, operating frequency) Energy-Delay Product (EDP)
◦ Delays between process input and output
◦ Maximum operating frequency
◦ Time-to-market
◦ An integrated circuit must be designed, verified, and finally implemented
◦ As quick as possible to become available first in the market to beat the competitors.

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 19

Design Domains
Y-chart
The IC design can be described
in the following three domains: Processor
◦ Behavioural Register Algorithm
◦ Circuit is described by its behavior Gate Register Transfer Language
Transistor Boolean Expression
◦ And not physical implementation or
structure Differential equation
◦ Structural
◦ Circuit is described by components and Transistor
interconnections
Cell
◦ Physical

Physical
◦ Deals with actual geometry Module
◦ Described by shape, size and location of
components Floorplan

Gajski−Kuhn Y-chart

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 20

Computer Aided Design (CAD)
Since the technology has allowed to reach todays integration levels
◦ We need to use CAD tools to cope with the design complexity
◦ A simple three loop circuit calculation requires three equations to be solved
◦ Imagine the analysis/design complexity for millions and billions of transistors

CAD tools fully or party automate the VLSI design steps

Implementation Tools Verification Tools
Logic and Physical Synthesis Simulation
Design for Test (DFT) Timing analysis
Full custom layout Formal Verification
Floorplanning Power Analysis
Place and route DRC and LVS

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 21

Recent Developments in IC
Design
Silicon on Insulator (SOI)
Three-Dimensional Chips (3D Chips)
Nanoelectronic Devices

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 22