Introduction to

VLSI Design
LECTURE# 01
VLSI DESIGN

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 1

Introduction
Course Title: VLSI Design
Course Code:EEE434
Class: EEE-6
Course Instructor: Saad Arslan
Lab Instructor: Saad Arslan
Contact me at
◦ saad.arslan@comsats.edu.pk (please be careful with spellings)

Text Book
◦ Introduction to VLSI Circuits and Systems
◦ By John P. Uyemura

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 2

Introduction to VLSI
VLSI is an acronym for Very Large Scale Integration
◦ Very dense electronic Integrated Circuits (ICs)
◦ Large number of switching devices (transistor) per unit area

The number of transistors has exceeded 1 billion per chip (IC)1

◦ Nowadays up to tens of billions2
Year Era Level of Integration
1958 Single Transistor -
1960 Monolithic IC 1
1962 Multi-function 2-4
1964 Complex function 5-20
1967 Medium scale integration MSI 20-200
1972 Large scale integration LSI 200-2000
1978 Very large scale integration VLSI 2000-20,000
1989 Ultra large scale integration ULSI Above 20,000

1
Peter Clarke, EE Times, “Intel enters billion-transistor processor era”, 14 October 2005
2
Antone Gonsalves, EE Times, "Samsung begins production of 16-Gb flash", 30 April 2007

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 3

Introduction to VLSI cont.
In order to achieve higher integration density
◦ Transistor sizes are being decreased (scaling)
◦ Transistor scaling is usually referred by channel length

Transistor scaling has also raised some issues along with the benefits
◦ Power density
◦ Velocity saturation
◦ Other short channel effects
Parameter Trends Transistor scaling
Number of transistors per IC Increasing and operating
Transistor size Decreasing frequency reaching
Operating frequency (speed) Increasing its limits.
Operating voltage Decreasing (to decrease power consumption) New solutions are
being adopted.

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 4

VLSI Complexity and Design
As the integration density increases Mostly top-down approach
◦ It also increases design complexity Bottom-up is only feasible for small projects
Top
design System Specifications
So, it is required to have level
Initial concept

◦ Design team
Abstract high-level model System design
◦ Design hierarchy Engineers VHDL, Verilog HDL and verification

Logic design
CAD

Sand Logic Synthesis

Marketing and verification

Idea
$$$$$$$ CMOS design
Circuit Design and verification
Bottom
design Physical Design Silicon logic design
level and verification

Mass production,
Manufacturing testing & packaging

Super chip Finished VLSI Chip Marketing

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 5

VLSI Chip Types
Full Custom
◦ Every circuit is custom designed
◦ Time consuming, high initial cost
◦ Suitable for mass-production

Application Specific Integrated Circuits (ASICs)

◦ ICs for a particular application
◦ Designers use CAD tools to translate higher level design to create layout
◦ No access over low-level electronics design
◦ Suitable for low-production and prototyping
◦ May involve using IP cores

Semi-Custom
◦ Hybrid of the above two
◦ Using standard cells and custom designed circuit

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 6

System-on-Chip
A designed IC will be required to interface with other components
◦ Microprocessor with RAM etc
◦ Multiples ICs are connected on a PC

Current integration levels allows us to implement

◦ Complete systems within a single chip, called System-on-chip
◦ Like a microcontroller

We can implement very large silicon chips as well

◦ However, the defects in the silicon crystal may render entire chip useless
◦ Large the silicon area, higher the probability of defects.
◦ So, yes there is a trade-off between size and yield

So far we are shrinking transistor size to increase number of transistors

◦ Channel length is the measure used to define a fabrication process
◦ 0.13-um process means the channel length is 130 nm (0.13 micron)

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 7

 Moore’s Law
Gordon Moore suggested

://www.cringely.com/2013/10/15/breaking-
that the number of
transistors in an IC
◦ Will double every 18 to 24
months

/ 2016-02-09 at 1100 hrs

So far, the Moore’s law is
holding, some what

Image courtesy http

◦ But it is also struggling
◦ As Gordon Moore himself

moores-law
said in 2015 1
◦ “I guess I see Moore’s law dying
here in the next decade or so,
but that’s not surprising.”

1
Moore, Gordon. “Gordon Moore: The Man Whose Name Means Progress, The visionary engineer reflects
on 50 years of Moore’s Law”, March 30, 2015

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 8

Design Metrics
The design quality is measured in terms of the following design metrics
◦ Functionality
◦ What operations it can perform of number of I/Os etc.
◦ Cost (non-recurring and recurring)
◦ NRE (Non-Recurrent Engineering) costs
◦ One time cost factor like design time, design effort and mask generation etc.
◦ R&D, Infrastructure building, training, manufacturing equipment, VLSI CAD tools
◦ Recurrent Costs
◦ Proportional to volume, chip area
◦ Silicon processing, packaging, testing
◦ Reliability
◦ noise margin/immunity

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 9

Design Metrics cont.
◦ Power dissipation (speed, power, energy)
◦ Peak and average power dissipation,
◦ Energy Power-delay Product (PDP)
◦ Speed (delay, operating frequency) Energy-Delay Product (EDP)
◦ Delays between process input and output
◦ Maximum operating frequency
◦ Time-to-market
◦ An integrated circuit must be designed, verified, and finally implemented
◦ As quick as possible to become available first in the market to beat the competitors.

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 10

Design Domains
Y-chart
The IC design can be described
in the following three domains: Processor
◦ Behavioural Register Algorithm
◦ Circuit is described by its behavior Gate Register Transfer Language
Transistor Boolean Expression
◦ And not physical implementation or
structure Differential equation
◦ Structural
◦ Circuit is described by components and Transistor
interconnections
Cell
◦ Physical

Physical
◦ Deals with actual geometry Module
◦ Described by shape, size and location of
components Floorplan

Gajski−Kuhn Y-chart

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 11

Computer Aided Design
(CAD)
Since the technology has allowed to reach todays integration levels
◦ We need to use CAD tools to cope with the design complexity
◦ A simple three loop circuit calculation requires three equations to be solved
◦ Imagine the analysis/design complexity for millions and billions of transistors

CAD tools fully or party automate the VLSI design steps

Implementation Tools Verification Tools
Logic and Physical Synthesis Simulation
Design for Test (DFT) Timing analysis
Full custom layout Formal Verification
Floorplanning Power Analysis
Place and route DRC and LVS

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 12

Recent Developments in IC
Design
Silicon on Insulator (SOI)
Three-Dimensional Chips (3D Chips)
Nanoelectronic Devices

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 13