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MODEL NAME : RANGER 17
1
PCB NO : LA-9331P 1

BOM P/N : 4619KL31L01

Compal Confidential
2 2

RANGER 17
Schematic Document
Rev: X00

3
2012-06-22 3

@ : Nopop Component

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 1 of 61
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LVDS Mux LVDS Mux eDP to LVDS


LVDS Conn.
P.39
PI3LVD1012
P.39
PI3LVD1012
P.38 RTD2136 P.37 www.laptopblue.vn
FFS P.46 Fan Control CPU XDP
eDP deMux 4-lane eDP LNG3DMTR EMC1412 P.51 Conn. P.7
eDP MUX eDP MUX PS8338 P.28
eDP Conn. Intel
P.30 PS8321 P.30 PS8321 P.29 HDMI
1
Haswell 1

Processor
DP/HDMI
4C 47W/57W Memory Bus DDRIII
LVDS to DP SW Dual Channel 204pin DDRIII SO-DIMM x4
eDP Scoket G3 P.13, 14, 15, 16
STDP4028 P.35 BANK 0, 1, 2, 3
PEGx16 1.35V DDRIII 1600 MHz
LVDS Gen 3 rPGA-947
MXM III
LVDS Mux HDMI Conn. P.6, 7, 8, 9, 10, 11, 12
HDMI to LVDS SW
STDP6038 PI3LVD1012
P.34 P.31
DP1.2
DMI x4
DP/HDMI 100MHz
HDMI Redriver HDMI MUX P.26 5GT/s
PS121 P.33 PS8271 P.33 USB3.0 Rediver
USB3.0
PS8713 P.49 USB 3.0/USB 2.0 Conn.
USB 2.0 ( USB Charger Port ) P.49

USB3.0 Rediver
HDMI 1.3 Input HDMI SW USB3.0
PS8713 P.49 USB 3.0/USB 2.0 Conn.
HDMI 1.4a Output USB 2.0 P.49
2 TS3DV421 P.32 2
Conn. P.32
USB3.0 Rediver
USB3.0
USB 2.0
PS8713 USB 3.0/USB 2.0 Conn.

DP Redriver USB3.0 Rediver


miniDP Conn. USB3.0
PS8330 P.27
USB 2.0
PS8713 USB 3.0/USB 2.0 Conn.
P.27
Intel USB3.0 Daughter Board P.50

USB2.0 with eDP Panel


Mini Card #1(Half) USB2.0 Digital Camera P.30

WLAN/WiMax PCI-E 2.0


Lynx Point USB2.0
Digital Camera P.54
with LVDS Panel

BT4.0+LE/WiGig
P.48 PCH USB2.0 AlienFX/ELC
HDMI Redriver HDMI MUX P.45,46

PS121 P.36 PS8271 P.36


DMC HM87 USB2.0 3D IR
P.52
USB2.0
Display MiniCard
PCI-E 2.0 BGA 695 Balls
P.48
SATA 3.0 HDD Conn. 1
P.46

3
RJ45 Conn. LAN(GbE) PCI-E 2.0 SATA 3.0 SATA Rediver HDD Conn. 2 3

E2201 Killer PS8520BT P.46 P.46


P.41
USB3.0 Daughter Board P.50

HDD Conn. 3
In ODD Bay (In place
P.47
of ODD)
Card Reader PCI-E 2.0
9 in 1 Conn. RTS5209 SATA 3.0 SATA Rediver ODD Conn.
P.47
Card Reader Board P.50 PS8520BT P.47

SATA 3.0 SATA Rediver Mini Card #3(Full)


P.17, 18, 19, 20, 21, 22, 23, 24, 25 P.47
PS8520BT P.47 mSATA

SPI ROM SPI Combo Jack


LPC Bus ( iPhone & Nokia compatible) P.42
8MB P.20 HD Audio
RTC conn.
Headphone Jack P.42
ENE KC3810 ENE KB9012 Audio Codec
Power On/Off CKT. P.40 P.40 ALC3661 Headphone Jack
P.52 P.42

Camera with eDP Panel


4 Array Mics P.30 4
DC/DC Interface CKT. P.42
Camera with LVDS Panel
P.53
Array Mics P.39

VPK MCU Int.KBD Touch Pad


Power Circuit DC/DC TI Int. Speaker (2.5W*4)
P.54, 55, 56, 57, 58, 59, 60, 61
VPK Daughter Board P.50
TPA3113D2 P.43 P.43

Security Classification Compal Secret Data


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 2 of 61
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A B C D E

Compal Confidential www.laptopblue.vn


Project Code : VAS00
File Name : LA-9331P
LA-9331P M/B
1 Camera 1
50pin
B To B conn.
LS-9335P
44 pin LCD Panel
POWER BUTTON/B
on/off SW Coaxial/Wire Combo
Led x 2
Hot Bar

22 pin
FFC
6 pin
HDD2 conn.
LS-9336P FFC FFC
20 pin 30 pin
INDICATOR/B LS-9337P
Led-HDD
CardReader /B 22 pin 20 pin ODD HDD3
2
Led-Wireless LF-XXXXP 2

Led-CapsLock Lid HDD1 conn. FPC HDD in ODD Bay Cable

Card Slot

FFC
60 pin Wire
12pin
KSI/KSO
LS-9338P RJ45
30 pin PWM
VPK Daughter/B Hot Key LS-9334P
6 pin
VPK Keyboard USB3.0
VPK MCU MAX7313
10 pin LOGO /B
40 pin Key Pad
Led x 2 USB3.0

Backlight / 8 Pressure-sense Analog Signals FFC LS-9339P


3
16 pin Wire Wire Wire USB30 /B
3

6pin Hot Bar 6pin 6pin


Hot Bar Hot Bar

LS-9333P LS-9331P LS-9332P 50pin


Touch Pad
Alien Slits-R Light/B Alien head badge/B Alien Slits-L Light/B B To B conn.

4 pin Led x 2 Led x 2 Led x 2


To M/B FFC
Tron Light To USB30/B
L R
Wire Wire
6pin 6pin
To M/B
LS-933BP
Wire LS-933CP
Tron L/B
10pin Tron R/B
Led x 1
Led x 1

4 4

LS-933DP LS-933EP
Tron FL/B Tron FR/B
Led x 1 Led x 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 3 of 61
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A

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USB 3.0 PORT Connetion
Board ID Table for AD channel
Vcc 3.3V +/- 5% 1 JUSB1 (Left side)
BOARD ID Table
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 2 JUSB2 (Left side)
USB PORT# DESTINATION
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1 (SSI)
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 (PT) 3 NA 0 JUSB1(USB3.0 P1)
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3 (ST)
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4 (QT) 4 NA
1 JUSB2(USB3.0 P2)
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 1.0 (MP)
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 5 JUSB3 (Right side)
2 JUSB3(USB3.0 P5)
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 6 JUSB4 (Right side) 3 JUSB4(USB3.0 P6)

POWER STATES PM TABLE 4 JMINI1 (WLAN)


Signal SLP SLP SLP S4 SLP ALWAYS SUS RUN CLOCKS +5VS
S3# S4# S5# STATE# M# PLANE PLANE PLANE
5 JMINI2 (DMC)
State +5VALW +3VS

power
+3VALW +1.35V +1.5VS USB2.0 6 AlienFX/ELC
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON plane +3VLP +1.05V +1.05VS
+3V_PCH +0.675VS
7 IR SENSOR
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON ON OFF OFF +3VMXM
+5VMXM
8 None
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF +VCC_CORE
State
+1.35V_CPU_VDDQ
9 None
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF

10 None
S0 ON ON ON
Symbol Note : 11 eDP CAMERA
S3 ON ON OFF
: means Digital Ground 12 LVDS CAMERA
S5 S4/AC ON OFF OFF
13 VPK K/B
: means Analog Ground S5 S4/AC don't exist OFF OFF OFF
1 1

DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION


PCI EXPRESS DESTINATION
CLKOUT_PCIE0 MINI CARD-1 WLAN CLKOUTFLEX0 None
Lane 1/USB3.0 Port 3 None
CLKOUT_PCIE1 MINI CARD-2 DMC CLKOUTFLEX1 None
SATAIII DESTINATION
CLKOUT_PCIE2 10/100/1G LAN CLKOUTFLEX2 None Lane 2/USB3.0 Port 4 None
SATA0 HDD1 Lane 3 10/100/1G LAN
CLK CLKOUT_PCIE3 CARD READER CLKOUTFLEX3 None
SATA1 HDD2
CLKOUT_PCIE4 None Lane 4 CARD READER
CLKOUT DESTINATION SATA2 ODD
Lane 5 None
CLKOUT_PCIE5 None
PCI0 PCH_LOOPBACK SATA3 mSATA Lane 6 None
CLKOUT_PCIE6 None
PCI1 EC SATA4/PCIE LANE1 MINI CARD-1 WLAN
CLKOUT_PCIE7 None Lane 7 None
PCI2 80port debug card SATA5/PCIE LANE2 MINI CARD-2 DMC Lane 8 None
CLKOUT_PEG_A MXM
PCI3 None

PCI4 None

SMBUS Control Table

Thermal
SOURCE WLAN DMC BATT DIMM 6038 4028 Sensor FFS 2136 VPK MCU MXM XDP Charger TP mSATA

EC_SMB_CK1
EC_SMB_DA1
KB9012
V V V
EC_SMB_CK2
EC_SMB_DA2
KB9012
V V V V V
PCH_SML0CLK PCH Link
PCH_SML0DATA

PCH_SML1CLK PCH
PCH_SML1DATA Security Classification Compal Secret Data Compal Electronics, Inc.
2012/06/22 2013/06/21 Title
MEM_SMBCLK
MEM_SMBDATA
PCH
V V V V V V Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Notes List
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 4 of 61
A
5 4 3 2 1

SMBUS Address [TBD]


2.2K 2.2K

2.2K
+3V_PCH
+3VS
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2.2K
+3VS
QH9A
R10 MEM_SMBCLK PCH_SMBCLK
202
U11 MEM_SMBDATA PCH_SMBDATA DIMM1 SMBUS Address [A2]
200
PCH
QH9B
D 202 D
2.2K DIMM2
U8 SML0CLK 200 SMBUS Address [A6]

2.2K +3V_PCH
R7 SML0DATA
202
DIMM3 SMBUS Address [A0]
K6 N11 200
2.2K
SML1CLK
202
SML1DATA
+3V_PCH 200
DIMM4
SMBUS Address [A4]
2.2K
4.7K
+3VS

+DVCC33
4.7K
+3VS 0 Ω
DDR_XDP_SMBCLK_R1 53
XDP SMBUS Address [TBD]
QH9A

QH9B

QV2B DDR_XDP_SMBDAT_R1 51
0 Ω
0 Ω
EC_SMB_CK2 CSCL CIICSCL 111
RTD2136S SMBUS Address [TBD]
EC_SMB_DA2 CSDA CIICSDA 112
0 Ω G sensor
QV2A 4.7K 4
C 6
LNG3DM C
+3VS SMBUS Address [TBD]
4.7K
2.2K
+3VS

LVDS transfer DP 30
2.2K
0 Ω mSATA
EC_HDMI_DAT_R B14 32 SMBUS Address [TBD]
STDP4028 SMBUS Address [TBD]
EC_HDMI_CLK_R C13
0 Ω
0 Ω
79 0 Ω 22 Ω HDMI IN MINI2_SMBCLK
SCL2 EC_SMB_CK2 30
EC_SMB_CK2_R EC_HDMI_CLK 72 DMC
80 SMBUS Address [TBD] 32 SMBUS Address [TBD]
SDA2 STDP6038
EC_SMB_DA2 EC_SMB_DA2_R EC_HDMI_DAT 71
22 Ω 0 Ω MINI2_SMBDATA
0 Ω
KBC 0 Ω
VPK
15
VPK_SMB_CK2 43 Touch pad
MSP430F5508 SMBUS Address [0FFFFh to 0FF80h] 16 SMBUS Address [TBD]
VPK_SMB_DA2 42
0 Ω
Thermal sensor MXM FAN CONTROL
8
ADM1032 SMBUS Address [100_1100]
7
B B

Thermal sensor SYSTEM FAN CONTROL


8
KB9012 ADM1032 SMBUS Address [100_1100]
+3VALW_EC

7
2.2K
4.7K
+3V_MXM
2.2K +3V_MXM
4.7K
QV8
77 VGA_SMB_CK1 70
SCL1 EC_SMB_CK1
SDA1 78 EC_SMB_DA1 VGA_SMB_DA1 68 MXM1 CONN
SMBUS Address []

QV6
0 Ω 0 Ω MXM Current Monitor
MXM_CURI2C_CLK 5
HPA00900
MXM_CURI2C_DATA 6 SMBUS Address []

100 Ω 4
CLK_SMB
A 5 BATT CONN A
DAT_SMB SMBUS Address []
100 Ω
0 Ω
PU700 SMBUS Address [000_1001]
0 Ω Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBus block diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9331P
Date: Friday, June 22, 2012 Sheet 5 of 61
5 4 3 2 1
5 4 3 2 1

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D +VCOMP_OUT D

PEG_COMP 2 1
24.9_0402_1%~D RC2

CAD Note: PEG_GTX_HRX_P[0..15] <29>


PEG_GTX_HRX_N[0..15] <29>
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils. PEG_HTX_C_GRX_P[0..15] <29>
PEG_HTX_C_GRX_N[0..15] <29>

Haswell rPGA EDS


JCPU1A

E23 PEG_COMP
PEG_RCOMP PEG_GTX_C_HRX_N0 CC1 0.22U_0402_16V7K~D PEG_GTX_HRX_N0
PEG_RXN_0 M29 1 2
DMI_CRX_PTX_N0 D21 K28 PEG_GTX_C_HRX_N1 CC2 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N1
<17> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
DMI_CRX_PTX_N1 C21 M31 PEG_GTX_C_HRX_N2 CC3 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N2
<17> DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_RXN_1 PEG_RXN_2 PEG_GTX_C_HRX_N3 PEG_GTX_HRX_N3
B21 L30 CC4 1 2 0.22U_0402_16V7K~D
<17> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_RXN_2 PEG_RXN_3 PEG_GTX_C_HRX_N4 PEG_GTX_HRX_N4
A21 M33 CC5 1 2 0.22U_0402_16V7K~D
<17> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 PEG_GTX_C_HRX_N5 PEG_GTX_HRX_N5
L32 CC13 1 2 0.22U_0402_16V7K~D
DMI_CRX_PTX_P0 PEG_RXN_5 PEG_GTX_C_HRX_N6 CC6 0.22U_0402_16V7K~D PEG_GTX_HRX_N6
D20 M35 1 2

PEG
<17> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_RXP_0 PEG_RXN_6 PEG_GTX_C_HRX_N7 PEG_GTX_HRX_N7
C20 L34 CC7 1 2 0.22U_0402_16V7K~D
<17> DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_RXP_1 PEG_RXN_7 PEG_GTX_C_HRX_N8 PEG_GTX_HRX_N8
B20 E29 CC8 1 2 0.22U_0402_16V7K~D
<17> DMI_CRX_PTX_P2 DMI_RXP_2 PEG_RXN_8
DMI_CRX_PTX_P3 A20 D28 PEG_GTX_C_HRX_N9 CC9 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N9
<17> DMI_CRX_PTX_P3

DMI
DMI_RXP_3 PEG_RXN_9 PEG_GTX_C_HRX_N10 CC10 0.22U_0402_16V7K~D PEG_GTX_HRX_N10
PEG_RXN_10 E31 1 2
<17> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 D18 D30 PEG_GTX_C_HRX_N11 CC11 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N11
DMI_CTX_PRX_N1 DMI_TXN_0 PEG_RXN_11 PEG_GTX_C_HRX_N12 CC12 0.22U_0402_16V7K~D PEG_GTX_HRX_N12
<17> DMI_CTX_PRX_N1 C17 DMI_TXN_1 PEG_RXN_12 E35 1 2
<17> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 B17 D34 PEG_GTX_C_HRX_N13 CC14 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N13
DMI_CTX_PRX_N3 DMI_TXN_2 PEG_RXN_13 PEG_GTX_C_HRX_N14 CC15 0.22U_0402_16V7K~D PEG_GTX_HRX_N14
<17> DMI_CTX_PRX_N3 A17 DMI_TXN_3 PEG_RXN_14 E33 1 2
E32 PEG_GTX_C_HRX_N15 CC16 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N15
C DMI_CTX_PRX_P0 PEG_RXN_15 PEG_GTX_C_HRX_P0 CC17 0.22U_0402_16V7K~D PEG_GTX_HRX_P0 C
<17> DMI_CTX_PRX_P0 D17 DMI_TXP_0 PEG_RXP_0 L29 1 2
<17> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 C18 L28 PEG_GTX_C_HRX_P1 CC18 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P1
DMI_CTX_PRX_P2 DMI_TXP_1 PEG_RXP_1 PEG_GTX_C_HRX_P2 CC19 0.22U_0402_16V7K~D PEG_GTX_HRX_P2
<17> DMI_CTX_PRX_P2 B18 DMI_TXP_2 PEG_RXP_2 L31 1 2
<17> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 A18 K30 PEG_GTX_C_HRX_P3 CC20 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P3
DMI_TXP_3 PEG_RXP_3 PEG_GTX_C_HRX_P4 CC21 0.22U_0402_16V7K~D PEG_GTX_HRX_P4
PEG_RXP_4 L33 1 2
K32 PEG_GTX_C_HRX_P5 CC22 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P5
PEG_RXP_5 PEG_GTX_C_HRX_P6 CC23 0.22U_0402_16V7K~D PEG_GTX_HRX_P6
PEG_RXP_6 L35 1 2
K34 PEG_GTX_C_HRX_P7 CC24 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P7
PEG_RXP_7 PEG_GTX_C_HRX_P8 CC25 0.22U_0402_16V7K~D PEG_GTX_HRX_P8
F29 1 2
RC3 FDI_CSYNC_R PEG_RXP_8 PEG_GTX_C_HRX_P9 PEG_GTX_HRX_P9
<17> FDI_CSYNC 2 1 0_0402_5%~D H29 E28 CC26 1 2 0.22U_0402_16V7K~D

FDI
RC87 FDI_INT_R FDI_CSYNC PEG_RXP_9 PEG_GTX_C_HRX_P10 PEG_GTX_HRX_P10
<17> FDI_INT 2 1 0_0402_5%~D J29 F31 CC27 1 2 0.22U_0402_16V7K~D
FDI_INT PEG_RXP_10 PEG_GTX_C_HRX_P11 CC28 0.22U_0402_16V7K~D PEG_GTX_HRX_P11
E30 1 2
PEG_RXP_11 PEG_GTX_C_HRX_P12 CC29 0.22U_0402_16V7K~D PEG_GTX_HRX_P12
F35 1 2
PEG_RXP_12 PEG_GTX_C_HRX_P13 CC30 0.22U_0402_16V7K~D PEG_GTX_HRX_P13
E34 1 2
PEG_RXP_13 PEG_GTX_C_HRX_P14 CC31 0.22U_0402_16V7K~D PEG_GTX_HRX_P14
F33 1 2
PEG_RXP_14 PEG_GTX_C_HRX_P15 CC32 0.22U_0402_16V7K~D PEG_GTX_HRX_P15
D32 1 2
PEG_RXP_15 PEG_HTX_GRX_N0 CC33 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N0
H35 1 2
PEG_TXN_0 PEG_HTX_GRX_N1 CC34 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N1
H34 1 2
PEG_TXN_1 PEG_HTX_GRX_N2 CC35 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N2
J33 1 2
PEG_TXN_2 PEG_HTX_GRX_N3 CC36 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N3
H32 1 2
PEG_TXN_3 PEG_HTX_GRX_N4 CC37 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N4
J31 1 2
PEG_TXN_4 PEG_HTX_GRX_N5 CC38 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N5
G30 1 2
PEG_TXN_5 PEG_HTX_GRX_N6 CC39 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N6
C33 1 2
PEG_TXN_6 PEG_HTX_GRX_N7 CC40 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N7
B32 1 2
PEG_TXN_7 PEG_HTX_GRX_N8 CC41 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N8
B31 1 2
PEG_TXN_8 PEG_HTX_GRX_N9 CC42 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N9
A30 1 2
PEG_TXN_9 PEG_HTX_GRX_N10 CC43 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N10
B29 1 2
PEG_TXN_10 PEG_HTX_GRX_N11 CC44 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N11
A28 1 2
PEG_TXN_11 PEG_HTX_GRX_N12 CC45 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N12
B27 1 2
PEG_TXN_12 PEG_HTX_GRX_N13 CC46 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N13
A26 1 2
PEG_TXN_13 PEG_HTX_GRX_N14 CC47 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N14
B25 1 2
PEG_TXN_14 PEG_HTX_GRX_N15 CC48 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N15
A24 1 2
B PEG_TXN_15 PEG_HTX_GRX_P0 CC49 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P0 B
J35 1 2
PEG_TXP_0 PEG_HTX_GRX_P1 CC50 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P1
G34 1 2
PEG_TXP_1 PEG_HTX_GRX_P2 CC51 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P2
H33 1 2
PEG_TXP_2 PEG_HTX_GRX_P3 CC52 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P3
G32 1 2
PEG_TXP_3 PEG_HTX_GRX_P4 CC53 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P4
H31 1 2
PEG_TXP_4 PEG_HTX_GRX_P5 CC54 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P5
H30 1 2
PEG_TXP_5 PEG_HTX_GRX_P6 CC55 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P6
B33 1 2
PEG_TXP_6 PEG_HTX_GRX_P7 CC56 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P7
A32 1 2
PEG_TXP_7 PEG_HTX_GRX_P8 CC57 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P8
C31 1 2
PEG_TXP_8 PEG_HTX_GRX_P9 CC58 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P9
B30 1 2
PEG_TXP_9 PEG_HTX_GRX_P10 CC59 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P10
C29 1 2
PEG_TXP_10 PEG_HTX_GRX_P11 CC60 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P11
B28 1 2
PEG_TXP_11 PEG_HTX_GRX_P12 CC61 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P12
C27 1 2
PEG_TXP_12 PEG_HTX_GRX_P13 CC62 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P13
B26 1 2
PEG_TXP_13 PEG_HTX_GRX_P14 CC63 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P14
C25 1 2
PEG_TXP_14 PEG_HTX_GRX_P15 CC64 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P15
B24 1 2
PEG_TXP_15
Near MXM Connector
1 OF 9
INTEL_HASWELL_HASWELL

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (1/7) DMI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 6 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn
+VCCIO_OUT

SM_DRAMPWROK with DDR Power Gating Topology

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D
1 1
+3V_PCH +VCCIO_OUT +VCCIO_OUT

CC65

CC66
+1.35V_CPU_VDDQ
2 2

100K_0402_5%~D
+3V_PCH JXDP1

1
D D

@
1 2
GND0 GND1

1
RC89

1.8K_0402_1%
CC156 XDP_PREQ#_R 3 4 CFG17 CFG17 <9>
XDP_PRDY#_R OBSFN_A0 OBSFN_C0 CFG16
1 2 5 6 CFG16 <9>
OBSFN_A1 OBSFN_C1

RC16
7 8
0.1U_0402_25V6K~D CFG0 GND2 GND3 CFG8
Place near JXDP1 <9> CFG0 9 10 CFG8 <9>

2
+3V_PCH CFG1 OBSDATA_A0 OBSDATA_C0 CFG9
<9> CFG1 11 12 CFG9 <9>

2
OBSDATA_A1 OBSDATA_C1

5
13 14
CFG2 GND4 GND5 CFG10
2 1 1 15 16

P
<17> SYS_PWROK B <9> CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 <9>
RC88 0_0402_5%~D 4 RUNPWROK_AND 2 1 PM_DRAM_PWRGD_CPU 1 2 SYS_PWROK_XDP <9> CFG3 CFG3 17 18 CFG11 CFG11 <9>
O RC28 0_0402_5%~D @ RC125 1K_0402_1%~D OBSDATA_A3 OBSDATA_C3
<17> PM_DRAM_PWRGD 2 19 20
A GND6 GND7

G
UC2 XDP_OBS0 21 22 CFG19 CFG19 <9>
OBSFN_B0 OBSFN_D0

3.3K_0402_1%~D
1 2 74AHC1G09GW_TSSOP5~D XDP_OBS1 23 24 CFG18 CFG18 <9>
+3V_PCH

3
OBSFN_B1 OBSFN_D1

1
39_0402_5%~D
RC18 200_0402_1%~D 25 26
GND8 GND9

2
@ RC64

RC14
<9> CFG4 CFG4 27 28 CFG12 CFG12 <9>
CFG5 OBSDATA_B0 OBSDATA_D0 CFG13
<9> CFG5 29 30 CFG13 <9>
OBSDATA_B1 OBSDATA_D1
31 32
CFG6 GND10 GND11 CFG14
2 1 <9> CFG6 33 34 CFG14 <9>

2
RC94 0_0402_5%~D CFG7 OBSDATA_B2 OBSDATA_D2 CFG15
<9> CFG7 35 36 CFG15 <9>

1
OBSDATA_B3 OBSDATA_D3

SSM3K7002FU_SC70-3~D
@ RC5 need to close to JCPU1 37
GND12 GND13
38
H_CPUPWRGD RC5 1 2 1K_0402_1%~D H_CPUPWRGD_XDP 39 40 CLK_XDP RC144 1 2 0_0402_5%~D
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP <18>

1
D
<17,43> PBTN_OUT#
RC6 1 2 0_0402_5%~D CFD_PWRBTN#_XDP 41 42 CLK_XDP# RC145 1 2 0_0402_5%~D CLK_CPU_ITP# <18>
HOOK1 ITPCLK#/HOOK5

@ QC1
<10,56> RUN_ON_CPU1.5VS3# 2 43 44
RC8 1 CPU_PWR_DEBUG_R VCC_OBS_AB VCC_OBS_CD XDP_RST#_R CPU_PLTRST#_R
G
<10> CPU_PWR_DEBUG 2 0_0402_5%~D 45 46 2 1
RC12 1 SYS_PWROK_XDP HOOK2 RESET#/HOOK6 XDP_DBRESET#
S 2 0_0402_5%~D 47 48 RC9 1K_0402_1%~D

3
<17,43,62> IMVP_PWRGD HOOK3 DBR#/HOOK7
49 50
RC126 DDR_XDP_SMBDAT_R1 GND14 GND15 XDP_TDO
<12,13,14,15,19,49,50,51,53> PCH_SMBDATA 1 2 0_0402_5%~D 51
SDA TD0
52
RC127 1 2 0_0402_5%~D DDR_XDP_SMBCLK_R1 53 54 XDP_TRST#_R
<12,13,14,15,19,49,50,51,53> PCH_SMBCLK SCL TRST#
55 56 XDP_TDI
XDP_TCLK_R TCK1 TDI XDP_TMS_R
57 58
TCK0 TMS
59 60
GND16 GND17
SAMTE_BSH-030-01-L-D-A CONN@

+VCCIO_OUT

1 2 H_THERMTRIP#
@ RC136 56_0402_5%~D
1 2 H_CATERR# Haswell rPGA EDS
C @ RC128 49.9_0402_1%~D JCPU1B C
1 2 H_PROCHOT#
RC44 62_0402_5%~D AP32 MISC AP3 SM_RCOMP0
SKTOCC SM_RCOMP_0 SM_RCOMP1
AR3
SM_RCOMP_1

DDR3
THERMAL
H_CATERR# AN32 AP2 SM_RCOMP2
H_PECI CATERR SM_RCOMP_2 DDR3_DRAMRST#_CPU
<21,43> H_PECI AR27 AN3 DDR3_DRAMRST#_CPU <12>
PAD~D T66 @ PECI SM_DRAMRST
AK31
RSVD
<43,63> H_PROCHOT#
RC57 1 2 56_0402_5%~D H_PROCHOT#_R AM30 PROCHOT PRDY AR29 XDP_PRDY# RC50 1 2 0_0402_5%~D XDP_PRDY#_R
<21> H_THERMTRIP#
RC134 1 2 0_0402_5%~D H_THERMTRIP#_R AM35 AT29 XDP_PREQ# RC36 1 2 0_0402_5%~D XDP_PREQ#_R
THERMTRIP PREQ XDP_TCLK RC46 0_0402_5%~D XDP_TCLK_R
place RC134 near CPU AM34 1 2
TCK XDP_TMS RC47 0_0402_5%~D XDP_TMS_R
AN33 1 2
TMS XDP_TRST# RC48 0_0402_5%~D XDP_TRST#_R

JTAG
TRST AM33 1 2
H_PM_SYNC AT28 AM31 XDP_TDI_R RC23 1 2 0_0402_5%~D XDP_TDI
<17> H_PM_SYNC

PWR
VCCPWRGOOD_0_R PM_SYNC TDI XDP_TDO_R RC24 0_0402_5%~D XDP_TDO
<21> H_CPUPWRGD 1 2 AL34 AL33 1 2
RC25 0_0402_5%~D PM_DRAM_PWRGD_CPU PWRGOOD TDO XDP_DBRESET#_R RC26 0_0402_5%~D XDP_DBRESET#
AC10 AP33 2 1 XDP_DBRESET# <17>
CPU_PLTRST#_R SM_DRAMPWROK DBR
AT26
PLTRSTIN XDP_OBS0_R RC30 0_0402_5%~D XDP_OBS0
AR30 1 2
BPM_N_0 XDP_OBS1_R RC31 0_0402_5%~D XDP_OBS1
AN31 1 2
RC51 0_0402_5%~D CPU_DPLL# BPM_N_1 XDP_OBS2_R RC33 0_0402_5%~D
<18> CLK_CPU_DPLL# 2 1 G28 AN29 1 2
DPLL_REF_CLKN BPM_N_2

CLOCK
RC52 2 1 0_0402_5%~D CPU_DPLL H28 AP31 XDP_OBS3_R RC34 1 2 0_0402_5%~D
<18> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3
RC43 2 1 0_0402_5%~D CPU_SSC_DPLL# F27 AP30 XDP_OBS4_R RC37 1 2 0_0402_5%~D
<18> CLK_CPU_SSC_DPLL# SSC_DPLL_REF_CLKN BPM_N_4
RC22 2 1 0_0402_5%~D CPU_SSC_DPLL E27 AN28 XDP_OBS5_R RC40 1 2 0_0402_5%~D
<18> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5
RC15 2 1 0_0402_5%~D CPU_DMI# D26 AP29 XDP_OBS6_R RC38 1 2 0_0402_5%~D
<18> CLK_CPU_DMI# BCLKN BPM_N_6
RC13 2 1 0_0402_5%~D CPU_DMI E26 AP28 XDP_OBS7_R RC39 1 2 0_0402_5%~D
<18> CLK_CPU_DMI BCLKP BPM_N_7
For ESD concern, please put near CPU
INTEL_HASWELL_HASWELL 2 OF 9

+VCCIO_OUT CONN@

CPU_SSC_DPLL 1 2
10K_0402_5%~D RC20 @
CPU_SSC_DPLL# 1 2
10K_0402_5%~D RC21 @
PU/PD for JTAG signals
+3VS

B SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21 XDP_DBRESET#_RRC19 2


B
1 1K_0402_1%~D

+1.05VS
VCCPWRGOOD_0_R
XDP_TMS @ RC27 2 1 51_0402_1%~D
10K_0402_5%~D

Buffered reset to CPU


1

+3VS XDP_TDI_R RC29 2 1 51_0402_1%~D


+1.05VS CRB Rev 0.7 no pull up
RC135

XDP_PREQ# @ RC32 2 1 51_0402_1%~D


0.1U_0402_25V6K~D

XDP_TDO_R RC35 2 1 51_0402_1%~D


1
DDR3 COMPENSATION SIGNALS
2
1 1K_0402_1%~D
CC140

CRB Rev 0.7 is depop


RC17

2 SM_RCOMP0 RC45 1 2 100_0402_1%~D XDP_TCLK RC42 2 1 51_0402_1%~D


UC1 CAD Note:
2

1 5 SM_RCOMP1 RC55 1 2 75_0402_1%~D XDP_TRST# RC41 2 1 51_0402_1%~D


NC VCC Avoid stub in the PWRGD path
<17,43,44,51,53> PLT_RST# 2
A PCH_PLTRST#_BUF
3 4 1 2 @ RC54 2 1 0_0402_5%~D CPU_PLTRST#_R while placing resistors RC25 & RC130 SM_RCOMP2 RC49 1 2 100_0402_1%~D
GND Y RC10 43_0402_5%~D
SN74LVC1G07DCKR_SC70-5~D CAD Note:
RC53 2 1 0_0402_5%~D
<21> CPU_PLTRST# Trace width=12~15 mil, Spcing=20 mils
1 20K_0402_5%~D

Max trace length= 500 mil


RC11
2

CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 7 of 61
5 4 3 2 1
5 4 3 2 1

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Haswell rPGA EDS


JCPU1C Haswell rPGA EDS
D JCPU1D D
<12,14> DDR_A_D[0..63] DDR_A_D0 <13,15> DDR_B_D[0..63]
AR15 AC7 @ T67 PAD~D
DDR_A_D1 SA_DQ_0 RSVD_AC7 M_CLK_DDR#0 DDR_B_D0 @ T76 PAD~D
AT14 U4 M_CLK_DDR#0 <14> AR18 AG8
DDR_A_D2 SA_DQ_1 SA_CK_N_0 M_CLK_DDR0 DDR_B_D1 SB_DQ_0 RSVD M_CLK_DDR#2
AM14 V4 M_CLK_DDR0 <14> AT18 Y4 M_CLK_DDR#2 <15>
DDR_A_D3 SA_DQ_2 SA_CK_P_0 DDR_CKE0_DIMMA DDR_B_D2 SB_DQ_1 SB_CKN0
AN14 AD9 DDR_CKE0_DIMMA <14> AM17 AA4 M_CLK_DDR2 M_CLK_DDR2 <15>
DDR_A_D4 SA_DQ_3 SA_CKE_0 M_CLK_DDR#1 DDR_B_D3 SB_DQ_2 SB_CK0 DDR_CKE2_DIMMB
AT15 U3 M_CLK_DDR#1 <14> AM18 AF10 DDR_CKE2_DIMMB <15>
DDR_A_D5 SA_DQ_4 SA_CK_N_1 M_CLK_DDR1 DDR_B_D4 SB_DQ_3 SB_CKE_0 M_CLK_DDR#3
AR14 V3 M_CLK_DDR1 <14> AR17 Y3 M_CLK_DDR#3 <15>
DDR_A_D6 SA_DQ_5 SA_CK_P_1 DDR_CKE1_DIMMA DDR_B_D5 SB_DQ_4 SB_CKN1
AN15 AC9 DDR_CKE1_DIMMA <14> AT17 AA3 M_CLK_DDR3 M_CLK_DDR3 <15>
DDR_A_D7 SA_DQ_6 SA_CKE_1 M_CLK_DDR#4 DDR_B_D6 SB_DQ_5 SB_CK1
AM15 U2 M_CLK_DDR#4 <12> AN17 AG10 DDR_CKE3_DIMMB DDR_CKE3_DIMMB <15>
DDR_A_D8 SA_DQ_7 SA_CK_N_2 M_CLK_DDR4 DDR_B_D7 SB_DQ_6 SB_CKE_1 M_CLK_DDR#6
AM9 V2 M_CLK_DDR4 <12> AN18 Y2 M_CLK_DDR#6 <13>
DDR_A_D9 SA_DQ_8 SA_CK_P_2 DDR_CKE4_DIMMC DDR_B_D8 SB_DQ_7 SB_CKN2
AN9 AD8 DDR_CKE4_DIMMC <12> AT12 AA2 M_CLK_DDR6 M_CLK_DDR6 <13>
DDR_A_D10 SA_DQ_9 SA_CKE_2 M_CLK_DDR#5 DDR_B_D9 SB_DQ_8 SB_CK2
AM8 SA_DQ_10 SA_CK_N_3 U1 M_CLK_DDR#5 <12> AR12 SB_DQ_9 SB_CKE_2 AG9 DDR_CKE6_DIMMD DDR_CKE6_DIMMD <13>
DDR_A_D11 AN8 V1 M_CLK_DDR5 DDR_B_D10 AN12 Y1 M_CLK_DDR#7
DDR_A_D12 SA_DQ_11 SA_CK_P_3 DDR_CKE5_DIMMC M_CLK_DDR5 <12> DDR_B_D11 SB_DQ_10 SB_CKN3 M_CLK_DDR#7 <13>
AR9 SA_DQ_12 SA_CKE_3 AC8 DDR_CKE5_DIMMC <12> AM11 SB_DQ_11 SB_CK3 AA1 M_CLK_DDR7 M_CLK_DDR7 <13>
DDR_A_D13 AT9 DDR_B_D12 AT11 AF9 DDR_CKE7_DIMMD
DDR_A_D14 SA_DQ_13 DDR_CS0_DIMMA# DDR_B_D13 SB_DQ_12 SB_CKE_3 DDR_CKE7_DIMMD <13>
AR8 SA_DQ_14 SA_CS_N_0 M7 DDR_CS0_DIMMA# <14> AR11 SB_DQ_13
DDR_A_D15 AT8 L9 DDR_CS1_DIMMA# DDR_B_D14 AM12 P4 DDR_CS2_DIMMB#
DDR_A_D16 SA_DQ_15 SA_CS_N_1 DDR_CS4_DIMMC# DDR_CS1_DIMMA# <14> DDR_B_D15 SB_DQ_14 SB_CS_N_0 DDR_CS3_DIMMB# DDR_CS2_DIMMB# <15>
AJ9 SA_DQ_16 SA_CS_N_2 M9 DDR_CS4_DIMMC# <12> AN11 SB_DQ_15 SB_CS_N_1 R2 DDR_CS3_DIMMB# <15>
DDR_A_D17 AK9 M10 DDR_CS5_DIMMC# DDR_B_D16 AR5 P3 DDR_CS6_DIMMD#
DDR_A_D18 SA_DQ_17 SA_CS_N_3 M_ODT0 DDR_CS5_DIMMC# <12> DDR_B_D17 SB_DQ_16 SB_CS_N_2 DDR_CS7_DIMMD# DDR_CS6_DIMMD# <13>
AJ6 SA_DQ_18 SA_ODT_0 M8 M_ODT0 <14> AR6 SB_DQ_17 SB_CS_N_3 P1 DDR_CS7_DIMMD# <13>
DDR_A_D19 AK6 L7 M_ODT1 DDR_B_D18 AM5
DDR_A_D20 SA_DQ_19 SA_ODT_1 M_ODT4 M_ODT1 <14> DDR_B_D19 SB_DQ_18 M_ODT2
AJ10 SA_DQ_20 SA_ODT_2 L8 M_ODT4 <12> AM6 SB_DQ_19 SB_ODT_0 R4 M_ODT2 <15>
DDR_A_D21 AK10 L10 M_ODT5 DDR_B_D20 AT5 R3 M_ODT3
DDR_A_D22 SA_DQ_21 SA_ODT_3 DDR_A_BS0 M_ODT5 <12> DDR_B_D21 SB_DQ_20 SB_ODT_1 M_ODT6 M_ODT3 <15>
AJ7 SA_DQ_22 SA_BS_0 V5 DDR_A_BS0 <12,14> AT6 SB_DQ_21 SB_ODT_2 R1 M_ODT6 <13>
DDR_A_D23 AK7 U5 DDR_A_BS1 DDR_B_D22 AN5 P2 M_ODT7
SA_DQ_23 SA_BS_1 DDR_A_BS1 <12,14> SB_DQ_22 SB_ODT_3 M_ODT7 <13>
DDR_A_D24 AF4 AD1 DDR_A_BS2 DDR_B_D23 AN6 R7 DDR_B_BS0
DDR_A_D25 SA_DQ_24 SA_BS_2 DDR_A_BS2 <12,14> DDR_B_D24 SB_DQ_23 SB_BS_0 DDR_B_BS1 DDR_B_BS0 <13,15>
AF5 SA_DQ_25 AJ4 SB_DQ_24 SB_BS_1 P8 DDR_B_BS1 <13,15>
DDR_A_D26 AF1 V10 DDR_B_D25 AK4 AA9 DDR_B_BS2
DDR_A_D27 SA_DQ_26 RSVD_V10 DDR_A_RAS# DDR_B_D26 SB_DQ_25 SB_BS_2 DDR_B_BS2 <13,15>
AF2 SA_DQ_27 SA_RAS U6 DDR_A_RAS# <12,14> AJ1 SB_DQ_26
DDR_A_D28 AG4 U7 DDR_A_WE# DDR_B_D27 AJ2 R10
SA_DQ_28 SA_WE DDR_A_WE# <12,14> SB_DQ_27 RSVD
DDR_A_D29 AG5 U8 DDR_A_CAS# DDR_B_D28 AM1 R6 DDR_B_RAS#
DDR_A_D30 SA_DQ_29 SA_CAS DDR_A_CAS# <12,14> DDR_B_D29 SB_DQ_28 SB_RAS DDR_B_WE# DDR_B_RAS# <13,15>
AG1 SA_DQ_30 DDR_A_MA[0..15] <12,14> AN1 SB_DQ_29 SB_WE
P6 DDR_B_WE# <13,15>
C DDR_A_D31 DDR_A_MA0 DDR_B_D30 DDR_B_CAS# C
AG2 SA_DQ_31 SA_MA_0 V8 AK2 SB_DQ_30 SB_CAS P7 DDR_B_CAS# <13,15>
DDR_A_D32 J1 AC6 DDR_A_MA1 DDR_B_D31 AK1
SA_DQ_32 SA_MA_1 SB_DQ_31 DDR_B_MA[0..15] <13,15>
DDR_A_D33 J2 V9 DDR_A_MA2 DDR_B_D32 L2 R8 DDR_B_MA0
DDR_A_D34 SA_DQ_33 SA_MA_2 DDR_A_MA3 DDR_B_D33 SB_DQ_32 SB_MA_0 DDR_B_MA1
J5 SA_DQ_34 SA_MA_3 U9 M2 SB_DQ_33 SB_MA_1 Y5
DDR_A_D35 H5 AC5 DDR_A_MA4 DDR_B_D34 L4 Y10 DDR_B_MA2
DDR_A_D36 SA_DQ_35 SA_MA_4 DDR_A_MA5 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
H2 SA_DQ_36 SA_MA_5 AC4 M4 SB_DQ_35 SB_MA_3 AA5
DDR_A_D37 H1 AD6 DDR_A_MA6 DDR_B_D36 L1 Y7 DDR_B_MA4
DDR_A_D38 SA_DQ_37 SA_MA_6 DDR_A_MA7 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
J4 AC3 M1 AA6
DDR_A_D39 SA_DQ_38 SA_MA_7 DDR_A_MA8 DDR_B_D38 SB_DQ_37 SB_MA_5 DDR_B_MA6
H4 AD5 L5 Y6
DDR_A_D40 SA_DQ_39 SA_MA_8 DDR_A_MA9 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
F2 AC2 M5 AA7
DDR_A_D41 SA_DQ_40 SA_MA_9 DDR_A_MA10 DDR_B_D40 SB_DQ_39 SB_MA_7 DDR_B_MA8
F1 V6 G7 Y8
DDR_A_D42 SA_DQ_41 SA_MA_10 DDR_A_MA11 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
D2 AC1 J8 AA10
DDR_A_D43 SA_DQ_42 SA_MA_11 DDR_A_MA12 DDR_B_D42 SB_DQ_41 SB_MA_9 DDR_B_MA10
D3 AD4 G8 R9
DDR_A_D44 SA_DQ_43 SA_MA_12 DDR_A_MA13 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
D1 V7 G9 Y9
DDR_A_D45 SA_DQ_44 SA_MA_13 DDR_A_MA14 DDR_B_D44 SB_DQ_43 SB_MA_11 DDR_B_MA12
F3 AD3 J7 AF7
DDR_A_D46 SA_DQ_45 SA_MA_14 DDR_A_MA15 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
C3 AD2 J9 P9
DDR_A_D47 SA_DQ_46 SA_MA_15 DDR_B_D46 SB_DQ_45 SB_MA_13 DDR_B_MA14
B3 G10 AA8
DDR_A_D48 SA_DQ_47 DDR_B_D47 SB_DQ_46 SB_MA_14 DDR_B_MA15
B5 DDR_A_DQS#[0..7] <12,14> J10 AG7
DDR_A_D49 SA_DQ_48 DDR_A_DQS#0 DDR_B_D48 SB_DQ_47 SB_MA_15
E6 AP15 A8
DDR_A_D50 SA_DQ_49 SA_DQS_N_0 DDR_A_DQS#1 DDR_B_D49 SB_DQ_48
A5 AP8 B8 DDR_B_DQS#[0..7] <13,15>
DDR_A_D51 SA_DQ_50 SA_DQS_N_1 DDR_A_DQS#2 DDR_B_D50 SB_DQ_49 DDR_B_DQS#0
D6 AJ8 A9 AP18
DDR_A_D52 SA_DQ_51 SA_DQS_N_2 DDR_A_DQS#3 DDR_B_D51 SB_DQ_50 SB_DQS_N_0 DDR_B_DQS#1
D5 AF3 B9 AP11
DDR_A_D53 SA_DQ_52 SA_DQS_N_3 DDR_A_DQS#4 DDR_B_D52 SB_DQ_51 SB_DQS_N_1 DDR_B_DQS#2
E5 J3 D8 AP5
DDR_A_D54 SA_DQ_53 SA_DQS_N_4 DDR_A_DQS#5 DDR_B_D53 SB_DQ_52 SB_DQS_N_2 DDR_B_DQS#3
B6 E2 E8 AJ3
DDR_A_D55 SA_DQ_54 SA_DQS_N_5 DDR_A_DQS#6 DDR_B_D54 SB_DQ_53 SB_DQS_N_3 DDR_B_DQS#4
A6 C5 D9 L3
DDR_A_D56 SA_DQ_55 SA_DQS_N_6 DDR_A_DQS#7 DDR_B_D55 SB_DQ_54 SB_DQS_N_4 DDR_B_DQS#5
E12 C11 DDR_A_DQS[0..7] <12,14> E9 H9
DDR_A_D57 SA_DQ_56 SA_DQS_N_7 DDR_A_DQS0 DDR_B_D56 SB_DQ_55 SB_DQS_N_5 DDR_B_DQS#6
D12 AP14 E15 C8
DDR_A_D58 SA_DQ_57 SA_DQS_P_0 DDR_A_DQS1 DDR_B_D57 SB_DQ_56 SB_DQS_N_6 DDR_B_DQS#7
B11 AP9 D15 C14 DDR_B_DQS[0..7] <13,15>
DDR_A_D59 SA_DQ_58 SA_DQS_P_1 DDR_A_DQS2 DDR_B_D58 SB_DQ_57 SB_DQS_N_7 DDR_B_DQS0
A11 AK8 A15 AP17
DDR_A_D60 SA_DQ_59 SA_DQS_P_2 DDR_A_DQS3 DDR_B_D59 SB_DQ_58 SB_DQS_P_0 DDR_B_DQS1
E11 AG3 B15 AP12
DDR_A_D61 SA_DQ_60 SA_DQS_P_3 DDR_A_DQS4 DDR_B_D60 SB_DQ_59 SB_DQS_P_1 DDR_B_DQS2
D11 H3 E14 AP6
DDR_A_D62 SA_DQ_61 SA_DQS_P_4 DDR_A_DQS5 DDR_B_D61 SB_DQ_60 SB_DQS_P_2 DDR_B_DQS3
B12 E3 D14 AK3
B DDR_A_D63 SA_DQ_62 SA_DQS_P_5 DDR_A_DQS6 DDR_B_D62 SB_DQ_61 SB_DQS_P_3 DDR_B_DQS4 B
A12 C6 A14 M3
SA_DQ_63 SA_DQS_P_6 DDR_A_DQS7 DDR_B_D63 SB_DQ_62 SB_DQS_P_4 DDR_B_DQS5
+V_SM_VREF AM3 C12 B14 H8
SM_VREF SA_DQS_P_7 SB_DQ_63 SB_DQS_P_5 DDR_B_DQS6
+DIMM0_1_VREF F16 C9
SA_DIMM_VREFDQ SB_DQS_P_6 DDR_B_DQS7
+DIMM0_1_CA F13 C15
SB_DIMM_VREFDQ SB_DQS_P_7

4 OF 9 INTEL_HASWELL_HASWELL
3 OF 9 INTEL_HASWELL_HASWELL
CONN@
CONN@
+1.35V

11K_0402_1%~D
RC86
+1.35V +1.35V +V_SM_VREF
+V_SM_VREF_CNT

2
1

1
1K_0402_1%~D

1K_0402_1%~D

RC146
1 2
RC96

RC95

+DIMM0_1_CA +DIMM0_1_VREF 0_0402_5%


1
+DIMM0_1_CA_CPU +DIMM0_1_VREF_CPU

1K_0402_1%~D
2

1
CC139

RC78
RC147 RC148 0.022U_0402_25V7K~D
2
1 2 1 2

1 0_0402_5% 1 0_0402_5%
2
1
1K_0402_1%~D

1K_0402_1%~D
1

CC137 CC138 RC149


RC82

RC81

0.022U_0402_25V7K~D 0.022U_0402_25V7K~D 24.9_0402_1%


A 2 2 A
2
2

2
1

RC150 RC151
24.9_0402_1% 24.9_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.


2

Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 8 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn COMPENSATION PU FOR eDP


+VCOMP_OUT

EDP_COMP 2 1
24.9_0402_1%~D RC1
D D
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

Haswell rPGA EDS


JCPU1H

CPU_HDMI_N0 T28 M27 CPU_EDP_AUX#


<36> CPU_HDMI_N0 CPU_HDMI_P0 DDIB_TXBN_0 EDP_AUXN CPU_EDP_AUX CPU_EDP_AUX# <31>
<36> CPU_HDMI_P0 U28 DDIB_TXBP_0 EDP_AUXP N27 CPU_EDP_AUX <31>
CPU_HDMI_N1 T30 P27 EDP_HPD
<36> CPU_HDMI_N1 CPU_HDMI_P1 DDIB_TXBN_1 eDP
EDP_HPD EDP_COMP
U30 E24
HDMI <36>
<36>
<36>
CPU_HDMI_P1
CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N3
U29
V29
U31
DDIB_TXBP_1
DDIB_TXBN_2
DDIB_TXBP_2
EDP_RCOMP
RSVD R27
PAD~D T77 @
<36> CPU_HDMI_N3 CPU_HDMI_P3 DDIB_TXBN_3
V31 DDIB_TXBP_3
<36> CPU_HDMI_P3 CPU_EDP_N0
EDP_TXN_0 P35
CPU_EDP_P0 CPU_EDP_N0 <31>
T34 DDIC_TXCN_0 EDP_TXP_0 R35
CPU_EDP_N1 CPU_EDP_P0 <31>
U34 DDIC_TXCP_0 EDP_TXN_1 N34
CPU_EDP_P1 CPU_EDP_N1 <31>
U35 DDIC_TXCN_1 EDP_TXP_1 P34 CPU_EDP_P1 <31>
V35 P33 CPU_EDP_N2
DDIC_TXCP_1 FDI_TXN_0 CPU_EDP_P2 CPU_EDP_N2 <31>
U32 DDIC_TXCN_2 FDI_TXP_0 R33
CPU_EDP_N3 CPU_EDP_P2 <31>
T32 DDIC_TXCP_2 FDI_TXN_1 N32
CPU_EDP_P3 CPU_EDP_N3 <31>
U33 DDIC_TXCN_3 FDI_TXP_1 P32
CPU_EDP_P3 <31>
V33 DDIC_TXCP_3
C CPU_DPD_DMC_N0 C
<39> CPU_DPD_DMC_N0 P29 DDID_TXDN_0
<39> CPU_DPD_DMC_P0 CPU_DPD_DMC_P0 R29
CPU_DPD_DMC_N1 DDID_TXDP_0
<39> CPU_DPD_DMC_N1 N28 DDID_TXDN_1 DDI
CPU_DPD_DMC_P1 P28
DMC <39>
<39>
<39>
CPU_DPD_DMC_P1
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_N3
P31
R31
N30
DDID_TXDP_1
DDID_TXDN_2
DDID_TXDP_2
<39> CPU_DPD_DMC_N3 DDID_TXDN_3
<39> CPU_DPD_DMC_P3 CPU_DPD_DMC_P3 P30
DDID_TXDP_3

INTEL_HASWELL_HASWELL 8 OF 9

CONN@

+VCCIO_OUT

1
B
HPD INVERSION FOR EDP 10K_0402_5%~D
RC65 B

2
EDP_HPD

BSS138_SOT23~D
1
D

QC10
<31> CPU_EDP_HPD# 2
G
S

3
1 100K_0402_5%~D
RC75
2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (4/7) FDI,eDP,DDI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 9 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn
CFG STRAPS for CPU
CFG2

1 1K_0402_1%~D
D D

@ RC76
2
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
0:Lane Reversed
Haswell rPGA EDS

JCPU1I

CFG4
@ T103PAD~D AT1 RSVD_TP

1K_0402_1%~D
@ T80 PAD~D AT2 C23 PAD~D T99 @
RSVD_TP RSVD_TP

1
@ T78 PAD~D AD10 B23 PAD~D T90 @
RSVD RSVD_TP

RC77
D24 PAD~D T87 @
@ T110PAD~D RSVD_TP PAD~D T88 @
A34 RSVD_TP RSVD_TP D23
@ T81 PAD~D A35 RSVD_TP

2
@ T79 PAD~D W29
@ T101PAD~D RSVD CFG_RCOMP
W28 RSVD CFG_RCOMP AT31
C H_CPU_RSVD G26 CFG16 C
RSVD CFG_16 AR21 CFG16 <6>
W33 AR23 CFG18
RSVD CFG_18 CFG18 <6>
@ T83 PAD~D AL30 AP21 CFG17
RSVD CFG_17 CFG19 CFG17 <6>
@ T108PAD~D AL29 AP23
+VCC_CORE F25
RSVD CFG_19 CFG19 <6> Display Port Presence Strap
VCC
@ T82 PAD~D C35 AR33 PAD~D T91 @
@ T94 PAD~D B35
RSVD_TP RSVD
G6 PAD~D T104@ 1 : Disabled; No Physical Display Port
RSVD_TP RSVD PAD~D T92 @
@ T85 PAD~D AL25
RSVD
AM27
AM26 PAD~D T89 @ CFG4 attached to Embedded Display Port
RSVD_TP RSVD PAD~D T93 @
F5
@ T84 PAD~D W30
RSVD
AM2 PAD~D T95 @ 0 : Enabled; An external Display Port device is
@ T86 PAD~D RSVD RSVD PAD~D T111@
H_CPU_TESTLO
W31
W34
RSVD RSVD
K6 connected to the Embedded Display Port
TESTLO PAD~D T96 @
E18
CFG0 RSVD
<6> CFG0 AT20
CFG1 CFG_0 PAD~D T98 @ CFG6
<6> CFG1 AR20 U10
CFG2 CFG_1 RSVD PAD~D T97 @
<6> CFG2 AP20 P10
CFG3 CFG_2 RSVD CFG5
<6> CFG3 AP22
CFG_3

1K_0402_1%~D
CFG4 AT22 B1
<6> CFG4 CFG_4 NC

1
1K_0402_1%~D
CFG5 AN22 A2 PAD~D T100 @
<6> CFG5 CFG_5 RSVD

@ RC90

@ RC92
CFG6 AT25 AR1 PAD~D T109 @
<6> CFG6 CFG_6 RSVD_TP
CFG7 AN23
<6> CFG7 CFG8 CFG_7
AR24 E21 PAD~D T102 @
<6> CFG8 CFG9 CFG_8 RSVD_TP
AT23 E20 PAD~D T107 @
<6> CFG9

2
CFG10 CFG_9 RSVD_TP
<6> CFG10 AN20
CFG11 CFG_10
<6> CFG11 AP24 AP27
CFG12 CFG_11 RSVD
<6> CFG12 AP26 AR26
CFG13 CFG_12 RSVD
<6> CFG13 AN25
CFG14 CFG_13 PAD~D T105 @
<6> CFG14 AN26 AL31
CFG15 CFG_14 RSVD PAD~D T106 @
<6> CFG15 AP25 AL32
CFG_15 RSVD
B PCIE Port Bifurcation Straps B

2 1 H_CPU_TESTLO INTEL_HASWELL_HASWELL 9 OF 9 11: (Default) x16 - Device 1 functions 1 and 2 disabled


RC60 49.9_0402_1%~D
2 1 CFG_RCOMP CONN@
10: x8, x8 - Device 1 function 1 enabled ; function 2
RC58 49.9_0402_1%~D
2 1 H_CPU_RSVD
CFG[6:5] disabled
RC59 49.9_0402_1%~D 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1
1K_0402_1%~D
@ RC91
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately
A CFG7 following xxRESETB de assertion A

0: PEG Wait for BIOS for training

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (5/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 10 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

D +1.35V_CPU_VDDQ Source Haswell rPGA EDS


JCPU1E
+VCC_CORE
D

+1.35V QC3 +1.35V_CPU_VDDQ


+3VALW B+_BIAS AO4304L_SO8 AA26
VCC
8 1 AA28
VCC

330K_0402_5%~D

10U_0603_6.3V6M~D
7 2 @ T113 PAD~D K27 AA34
RSVD VCC

1
20K_0402_5%~D
6 3 1 @ T114 PAD~D L27 AA30
RSVD VCC

100K_0402_5%~D

RC72

CC135
5 @ T112 PAD~D T27 AA32
RSVD VCC

@ RC73
@ T116 PAD~D V27 AB26
RSVD VCC

RC74
AB29

4
2 +1.35V_CPU_VDDQ VCC
AB25

2
RUN_ON_CPU1.5VS3 +1.35V VCC
AB27
VCC
AB28

2
VCC

0.022U_0402_25V7K~D
CC151 2 1 0.1U_0402_10V7K~D AB11 AB30
VDDQ VCC
AB2 AB31
VDDQ VCC

1
DMN66D0LDW-7_SOT363-6~D
QC4B

1M_0402_5%~D
1 CC152 2 1 0.1U_0402_10V7K~D AB5 AB33
VDDQ VCC

RC143
RUN_ON_CPU1.5VS3# 5 AB8 AB34
VDDQ VCC

CC136
AE11 AB32
VDDQ VCC
AE2 AC26

4
2 VDDQ VCC
AE5 AB35

2
VDDQ VCC

6
AE8 AC28
VDDQ VCC

DMN66D0LDW-7_SOT363-6~D
QC4A
<43,56,59,61> SUSP# 1 2 AH11 AD25
@ RC93 0_0402_5%~D VDDQ VCC
K11 AC30
VDDQ VCC
<43> CPU1.5V_S3_GATE 1 2 2 N11 AD28
RC79 0_0402_5%~D VDDQ VCC
N8 AC32
VDDQ VCC
T11 AD31

1
VDDQ VCC
T2 AC34
VDDQ VCC
T5 AD34
VDDQ VCC
T8 AD26
VDDQ VCC
W11 AD27
VDDQ VCC
RUN_ON_CPU1.5VS3# <6,56> W2 AD29
VDDQ VCC
W5 AD30
VDDQ VCC
W8 AD32
VDDQ VCC
AD33
@ T115 PAD~D VCC
N26 AD35
RSVD VCC
+VCC_CORE K26 AE26
VCC VCC
AL27 AE32
@ T151 PAD~D RSVD VCC
AK27 AE28
@ T152 PAD~D RSVD VCC
AE30
VCC
AG28
VCC
C AG34 C
VCC
AE34
+1.05VS +VCCIO_OUT VCC
AF25
+VCCIO_OUT VCC
AF26
SVID ALERT 2 1 @ T153 PAD~D
VCCSENSE_R AL35
E17
VCC_SENSE
RSVD
VCC
VCC
VCC
AF27
AF28
75_0402_1%~D

@ RC4 0_0603_5%~D +VCCIO_OUT AN35 AF29


VCCIO_OUT VCC
1

@ T156 PAD~D A23 AF30


VCCIO2PCH VCC
RC61

CAD Note: Place the PU resistors close to CPU +VCOMP_OUT F22


VCCIOA_OUT VCC
AF31
RESISTOR STUFFING OPTIONS ARE W32
RSVD VCC
AF32
RC60 close to CPU 300 - 1500mils PROVIDED FOR TESTING PURPOSES @ T160 PAD~D AL16 AF33
@ T159 PAD~D RSVD VCC
J27 AF34
2

@ T168 PAD~D VSS VCC


AL13 AF35
H_CPU_SVIDALRT# +1.05VS @ T154 PAD~D RSVD VCC
<62> VIDALERT_N 2 1 AG26
43_0402_5%~D RC69 VCC
AH26
H_CPU_SVIDALRT# AM28 VCC
AH29
VIDSCLK VIDALERT VCC
<62> VIDSCLK AM29 AG30
VIDSCLK VCC

10K_0402_5%~D
VIDSOUT AL28 AG32
VIDSOUT VCC

1
+VCCIO_OUT AH32
SVID DATA VCC

@
AP35 AH35
VSS VCC
110_0402_1%~D

RC80
<6> CPU_PWR_DEBUG H27 AH25
PWR_DEBUG VCC
1

CAD Note: Place the PU resistors close to CPU AP34


RSVD VCC
AH27
RC63

AT35 AH28

2
RC63 close to CPU 300 - 1500mils @ T157 PAD~D RSVD VCC
AR35 AH30
CPU_PWR_DEBUG @ T158 PAD~D RSVD VCC
AR32 AH31
@ T162 PAD~D RSVD VCC
AL26 AH33
2

RSVD VCC

10K_0402_5%~D
@ T163 PAD~D AT34 AH34
RSVD VCC

1
VIDSOUT AL22 AJ25
<62> VIDSOUT RSVD VCC

@
AT33 AJ26
RSVD VCC

RC71
AM21 AJ27
RSVD VCC
AM25 AJ28
RSVD VCC
AM22 AJ29

2
RSVD VCC
AM20 AJ30
RSVD VCC
AM24 AJ31
RSVD VCC
AL19 AJ32
+VCC_CORE RSVD VCC
AM23 AJ33
RSVD VCC
AT32 AJ34
VCC_SENSE RSVD VCC
VCC
AJ35
100_0402_1%~D

G25
VCC
1

H25
B VCC B
RC66

J25
VCC
K25
+VCC_CORE VCC
L25
VCC
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU M25
2

+1.35V_CPU_VDDQ VCC
Y25 N25
VDDQ DECOUPLING Y26
VCC VCC
P25
VCCSENSE VCCSENSE_R VCC VCC
<62> VCCSENSE 2 1 Y27 R25
0_0402_5%~D RC67 VCC VCC
Y28 T25
VCC VCC
Y29
VCC
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_D2_2VM_R6M~D
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU 1 Y30 U25
VCC VCC
1 1 1 1 1 1 1 1 1 1 Y31 U26
VCC VCC

CC167
+ Y32 V25
VCC VCC
CC180

CC170

CC169

CC168

CC161

CC162

CC163

CC164

CC165

CC166
VSSSENSE 2 1 VSSSENSE_R Y33 V26
<62> VSSSENSE VSSSENSE_R <11> VCC VCC
0_0402_5%~D RC68 Y34
2 2 2 2 2 2 2 2 2 2 2 VCC
Y35 W26
VCC VCC
1 100_0402_1%~D

W27
VCC
RC70

INTEL_HASWELL_HASWELL 5 OF 9

CONN@
2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
1 1 1 1 1 1 1 1 1 1 1
CC181

CC182

CC183

CC184

CC185

CC186

CC187

CC188

CC189

CC190

CC191
C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW
2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 11 of 61
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D Haswell rPGA EDS Haswell rPGA EDS D


JCPU1F JCPU1G

A10 AK34 B34 K10


VSS VSS VSS VSS
A13 AK5 B4 K2
VSS VSS VSS VSS
A16 AL1 B7 K29
VSS VSS VSS VSS
A19 AL10 C1 K3
VSS VSS VSS VSS
A22 AL11 C10 K31
VSS VSS VSS VSS
A25 AL12 C13 K33
VSS VSS VSS VSS
A27 AL14 C16 K35
VSS VSS VSS VSS
A29 AL15 C19 K4
VSS VSS VSS VSS
A3 AL17 C2 K5
VSS VSS VSS VSS
A31 VSS VSS AL18 C22 VSS VSS K7
A33 VSS VSS AL2 C24 VSS VSS K8
A4 VSS VSS AL20 C26 VSS VSS K9
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AA31 VSS VSS AL4 C4 VSS VSS M26
AA29 VSS VSS AL5 C7 VSS VSS M28
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AC27 VSS VSS AM16 D27 VSS VSS N2
AB4 VSS VSS AM19 D29 VSS VSS N29
AB6 VSS VSS E25 D31 VSS VSS N3
AB7 VSS VSS AM32 D33 VSS VSS N31
AB9 VSS VSS AM4 D35 VSS VSS N33
AC11 VSS VSS AM7 D4 VSS VSS N35
C C
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
AC31 VSS VSS AN16 E10 VSS VSS N6
AC33 VSS VSS AN19 E13 VSS VSS N7
AC35 VSS VSS AN2 E16 VSS VSS N9
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 AN27 F10 P5
VSS VSS VSS VSS
AE25 AN30 F11 R11
VSS VSS VSS VSS
AE29 AN34 F12 R26
VSS VSS VSS VSS
AE3 AN4 F14 R28
VSS VSS VSS VSS
AE27 AN7 F15 R30
VSS VSS VSS VSS
AE35 AP1 F17 R32
VSS VSS VSS VSS
AE4 AP10 F18 R34
VSS VSS VSS VSS
AE6 AP13 F20 R5
VSS VSS VSS VSS
AE7 AP16 F21 T1
VSS VSS VSS VSS
AE9 AP19 F23 T10
VSS VSS VSS VSS
AF11 AP4 F24 T29
VSS VSS VSS VSS
AF6 AP7 F26 T3
VSS VSS VSS VSS
AF8 W25 F28 T31
VSS VSS VSS VSS
AG11 AR10 F30 T33
VSS RSVD VSS VSS
AG25 AR13 F32 T35
VSS VSS VSS VSS
AE31 AR16 F34 T4
VSS VSS VSS VSS
AG31 AR19 F4 T6
VSS VSS VSS VSS
AE33 AR2 F6 T7
VSS VSS VSS VSS
AG6 AR22 F7 T9
VSS VSS VSS VSS
AH1 AR25 F8 U11
VSS VSS VSS VSS
AH10 AR28 F9 U27
VSS VSS VSS VSS
AH2 AR31 G1 V11
VSS VSS VSS VSS
AG27 AR34 G11 V28
VSS VSS VSS VSS
AG29 AR4 G2 V30
VSS VSS VSS VSS
AH3 AR7 G27 V32
B VSS VSS VSS VSS B
AG33 AT10 G29 V34
VSS VSS VSS VSS
AG35 AT13 G3 W1
VSS VSS VSS VSS
AH4 AT16 G31 W10
VSS VSS VSS VSS
AH5 AT19 G33 W3
VSS VSS VSS VSS
AH6 AT21 G35 W35
VSS VSS VSS VSS
AH7 AT24 G4 W4
VSS VSS VSS VSS
AH8 AT27 G5 W6
VSS VSS VSS VSS
AH9 AT3 H10 W7
VSS VSS VSS VSS
AJ11 AT30 H26 W9
VSS VSS VSS VSS
AJ5 AT4 H6 Y11
VSS VSS VSS VSS
AK11 AT7 H7 H11
VSS VSS VSS RSVD
AK25 B10 J11 AL24
VSS VSS VSS RSVD
AK26 B13 J26 F19
VSS VSS VSS RSVD
AK28 B16 J28 T26
VSS VSS RSVD RSVD
AK29 B19 J30 AK35
VSS VSS VSS VSS_SENSE VSSSENSE_R <10>
AK30 B2 J32 AK33
VSS VSS VSS RSVD PAD~D T120
@
AK32 B22 J34
VSS VSS VSS
E19 J6
VSS VSS
K1
VSS

INTEL_HASWELL_HASWELL 6 OF 9 INTEL_HASWELL_HASWELL 7 OF 9

CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 12 of 61
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+1.35V

1 1K_0402_5%~D
RD27
@
CRB Rev 0.7 is depop
JDIMMA H=4mm

2
D D

DDR3_DRAMRST#_R 1 2
+DIMM0_1_VREF_CPU <13,14,15> DDR3_DRAMRST#_R DDR3_DRAMRST#_CPU <6>
RD29 1K_0402_5%~D
+1.35V +1.35V
JDIMM1
1 2
VREF_DQ VSS DDR_A_D4
All VREF traces should 3 4
VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D0 5 6 DDR_A_D5
have 20 mil trace width DDR_A_D1 DQ0 DQ5
1 1 7 8
DQ1 VSS DDR_A_DQS#0
9 10
VSS DQS0#

CD1

CD2
11 12 DDR_A_DQS0
DM0 DQS0
13 14
2 2 DDR_A_D2 VSS VSS DDR_A_D6
15 16
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18
DQ3 DQ7
19 20
DDR_A_D8 VSS VSS DDR_A_D12
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
<7,14> DDR_A_DQS#[0..7] 23 24
DQ9 DQ13
25 26
DDR_A_DQS#1 VSS VSS
<7,14> DDR_A_D[0..63] 27 28
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30
DQS1 RESET#
<7,14> DDR_A_DQS[0..7] 31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
<7,14> DDR_A_MA[0..15] 35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS VSS
45 46
DDR_A_DQS2 DQS2# DM2
47 48
DQS2 VSS DDR_A_D22
49 50
DDR_A_D18 VSS DQ22 DDR_A_D23
Layout Note: DDR_A_D19
51
DQ18 DQ23
52
53 54
Place near JDIMMA DQ19 VSS DDR_A_D28
55 56
DDR_A_D24 VSS DQ28 DDR_A_D29
57 58
DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS DDR_A_DQS#3
61 62
VSS DQS3# DDR_A_DQS3
63 64
DM3 DQS3
65 66
+1.35V DDR_A_D26 VSS VSS DDR_A_D30
67 68
DDR_A_D27 DQ26 DQ30 DDR_A_D31
C 69 70 C
DQ27 DQ31
71 72
VSS VSS
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1 DDR_CKE4_DIMMC 73 74 DDR_CKE5_DIMMC
<7> DDR_CKE4_DIMMC CKE0 CKE1 DDR_CKE5_DIMMC <7>
75 76
VDD VDD
CD3

CD4

CD5

CD6

77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
<7,14> DDR_A_BS2 79 80
2 2 2 2 BA2 A14
81 82
DDR_A_MA12 VDD VDD DDR_A_MA11
83 84
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 86
A9 A7
87 88
DDR_A_MA8 VDD VDD DDR_A_MA6
89 90
DDR_A_MA5 A8 A6 DDR_A_MA4
91 92
A5 A4
93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
+1.35V A1 A0
99 100 M_CLK_DDR5 <7>
M_CLK_DDR4 VDD VDD M_CLK_DDR5
<7> M_CLK_DDR4 101 102 M_CLK_DDR#5 <7>
M_CLK_DDR#4 CK0 CK1 M_CLK_DDR#5
<7> M_CLK_DDR#4 103 104
CK0# CK1#
105 106 DDR_A_BS1 <7,14>
VDD VDD
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

DDR_A_MA10 107 108 DDR_A_BS1


A10/AP BA1 DDR_A_RAS# <7,14>
330U_SX_2VY~D

DDR_A_BS0 109 110 DDR_A_RAS#


<7,14> DDR_A_BS0 BA0 RAS#
1 111 112 DDR_CS4_DIMMC# <7>
VDD VDD
@ CD13

CD14

1 1 1 1 1 1 1 DDR_A_WE# 113 114 DDR_CS4_DIMMC#


<7,14> DDR_A_WE# WE# S0# M_ODT4 <7>
CD7

CD8

CD9

CD10

CD11

CD74

+ DDR_A_CAS# 115 116 M_ODT4


<7,14> DDR_A_CAS# CAS# ODT0
117 118 M_ODT5 <7> +V_SM_VREF_CNT
DDR_A_MA13 VDD VDD M_ODT5
119 120
2 2 2 2 2 2 2 2 DDR_CS5_DIMMC# A13 ODT1
<7> DDR_CS5_DIMMC# 121 122
S1# NC
123 124
VDD VDD
125
TEST VREF_CA
126 All VREF traces should
127 128
VSS VSS have 20 mil trace width

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
DQ33 DQ37
133 134 1 1
VSS VSS

CD15

CD16
DDR_A_DQS#4 135 136
DDR_A_DQS4 DQS4# DM4
137 138
DQS4 VSS DDR_A_D38
139 140
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
B DQ35 VSS DDR_A_D44
B
145 146
DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
Layout Note: 149 150
DQ41 VSS DDR_A_DQS#5
151 152
Place near JDIMMA.203,204 VSS DQS5# DDR_A_DQS5
153 154
DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS VSS DDR_A_D52
163 164
DDR_A_D49 165
DQ48
DQ49
DQ52
DQ53
166 DDR_A_D53 2(H8)
167 168
DDR_A_DQS#6 169
VSS
DQS6#
VSS
DM6
170 JDIMMA(H4)
+0.675VS DDR_A_DQS6 171 172
DQS6 VSS DDR_A_D54
173 174
+3VS DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

179 180 DDR_A_D60


1 1 1 1 DDR_A_D56
DDR_A_D57
181
VSS
DQ56
DQ60
DQ61
182 DDR_A_D61 CPU 3(H5.2)
183 184
DQ57 VSS
2

2
CD17

CD18

CD19

CD20

185 186 DDR_A_DQS#7


2 2 2 2
RD38 @ RD39 187
VSS
DM7
DQS7#
DQS7
188 DDR_A_DQS7 4(H9.2)
10K_0402_5%~D 10K_0402_5%~D 189 190
DDR_A_D58 VSS VSS DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
1

DQ59 DQ63
195 196
VSS VSS M_THERMAL#
197 198 M_THERMAL# <13,14,15,43>
SA0 EVENT#
+3VS 199 200 PCH_SMBDATA <6,13,14,15,19,49,50,51,53>
VDDSPD SDA
201 202 PCH_SMBCLK <6,13,14,15,19,49,50,51,53>
SA1 SCL
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

+0.675VS 203 204 +0.675VS


VTT VTT
1 1
2

CD21

CD22

205 206
RD21 @ RD22 GND1 GND2
207 208
10K_0402_5%~D 10K_0402_5%~D BOSS1 BOSS2
2 2
TYCO_2-2013022-1
1

SA0 SA1 CONN@

1 0 DIMM1A
A A
1 1 DIMMB
0 0 DIMMC
0 1 DIMMD

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 13 of 61
5 4 3 2 1
5 4 3 2 1

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D
JDIMMB H=4mm D

+DIMM0_1_CA_CPU
+1.35V +1.35V
JDIMM2
1 2
VREF_DQ VSS DDR_B_D4
3 4
VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
7 8
DQ1 VSS DDR_B_DQS#0
1 1 9 10
VSS DQS0#

CD23

CD24
11 12 DDR_B_DQS0
DM0 DQS0
13 14
DDR_B_D2 VSS VSS DDR_B_D6
All VREF traces should 15 16
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 18
have 20 mil trace width DQ3 DQ7
19 20
DDR_B_D8 VSS VSS DDR_B_D12
21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
DQ9 DQ13
<7,15> DDR_B_DQS#[0..7] 25 26
DDR_B_DQS#1 VSS VSS
27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
<7,15> DDR_B_D[0..63] 29 30 DDR3_DRAMRST#_R <12,14,15>
DQS1 RESET#
31 32
DDR_B_D10 VSS VSS DDR_B_D14
<7,15> DDR_B_DQS[0..7] 33 34
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
<7,15> DDR_B_MA[0..15] 37 38
DDR_B_D16 VSS VSS DDR_B_D20
39 40
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS VSS
45 46
DDR_B_DQS2 DQS2# DM2
47 48
DQS2 VSS DDR_B_D22
49 50
DDR_B_D18 VSS DQ22 DDR_B_D23
Layout Note: 51 52
DDR_B_D19 DQ18 DQ23
53 54
Place near JDIMMB DQ19 VSS DDR_B_D28
55 56
DDR_B_D24 VSS DQ28 DDR_B_D29
57 58
DDR_B_D25 DQ24 DQ29
59 60
DQ25 VSS DDR_B_DQS#3
61 62
VSS DQS3# DDR_B_DQS3
63 64
DM3 DQS3
65 66
DDR_B_D26 VSS VSS DDR_B_D30
C 67 68 C
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 70
+1.35V DQ27 DQ31
71 72
VSS VSS

DDR_CKE6_DIMMD 73 74 DDR_CKE7_DIMMD
<7> DDR_CKE6_DIMMD CKE0 CKE1 DDR_CKE7_DIMMD <7>
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

75 76
VDD VDD DDR_B_MA15
1 1 1 1 77 78
DDR_B_BS2 NC A15 DDR_B_MA14
<7,15> DDR_B_BS2 79 80
BA2 A14
CD25

CD26

CD27

CD28

81 82
DDR_B_MA12 VDD VDD DDR_B_MA11
83 84
2 2 2 2 DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 88
DDR_B_MA8 VDD VDD DDR_B_MA6
89 90
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 94
DDR_B_MA3 VDD VDD DDR_B_MA2
95 96
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
+1.35V M_CLK_DDR6 VDD VDD M_CLK_DDR7
<7> M_CLK_DDR6 101 102 M_CLK_DDR7 <7>
M_CLK_DDR#6 CK0 CK1 M_CLK_DDR#7
<7> M_CLK_DDR#6 103 104 M_CLK_DDR#7 <7>
CK0# CK1#
105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 108 DDR_B_BS1 <7,15>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<7,15> DDR_B_BS0 109 110
BA0 RAS# DDR_B_RAS# <7,15>
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

111 112
VDD VDD
330U_SX_2VY~D

1 DDR_B_WE# 113 114 DDR_CS6_DIMMD#


<7,15> DDR_B_WE# WE# S0# DDR_CS6_DIMMD# <7>
@ CD35

1 1 1 1 1 1 1 DDR_B_CAS# 115 116 M_ODT6


<7,15> DDR_B_CAS# CAS# ODT0 M_ODT6 <7>
CD29

CD30

CD31

CD32

CD33

CD34

CD36

+ 117 118
DDR_B_MA13 VDD VDD M_ODT7 +V_SM_VREF_CNT
119 120 M_ODT7 <7>
DDR_CS7_DIMMD# A13 ODT1
<7> DDR_CS7_DIMMD# 121 122
2 2 2 2 2 2 2 2 S1# NC
123 124
VDD VDD
125
TEST VREF_CA
126 All VREF traces should
127 128
VSS VSS have 20 mil trace width

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37

CD37
133 134 1 1
VSS VSS

CD38
DDR_B_DQS#4 135 136
DDR_B_DQS4 DQS4# DM4
137 138
DQS4 VSS DDR_B_D38
139 140
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 142
B
DDR_B_D35 DQ34 DQ39 B
143 144
DQ35 VSS DDR_B_D44
Layout Note: DDR_B_D40
145
VSS DQ44
146
DDR_B_D45
147 148
Place near JDIMMB.203,204 DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS DDR_B_DQS#5
151 152
VSS DQS5# DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 163
VSS
DQ48
VSS
DQ52
164 DDR_B_D52 JDIMMB(H8)
+0.675VS DDR_B_D49 165 166 DDR_B_D53
167
DQ49
VSS
DQ53
VSS
168 1(H4)
DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_B_D54
173 174
VSS DQ54
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+3VS DDR_B_D50 175 176 DDR_B_D55


DDR_B_D51 DQ50 DQ55
177 178
1 1 1 1
179
DQ51
VSS
VSS
DQ60
180 DDR_B_D60 CPU 3(H5.2)
CD39

CD40

CD41

CD42

DDR_B_D56 181 182 DDR_B_D61


DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS 4(H9.2)
2

2 2 2 2 DDR_B_DQS#7
185 186
RD40 RD24 VSS DQS7# DDR_B_DQS7
187 188
10K_0402_5%~D 10K_0402_5%~D DM7 DQS7
189 190
DDR_B_D58 VSS VSS DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
1

DQ59 DQ63
195 196
VSS VSS M_THERMAL#
197 198 M_THERMAL# <12,14,15,43>
SA0 EVENT#
+3VS 199 200 PCH_SMBDATA <6,12,14,15,19,49,50,51,53>
VDDSPD SDA
201 202 PCH_SMBCLK <6,12,14,15,19,49,50,51,53>
SA1 SCL
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

+0.675VS 203 204 +0.675VS


VTT VTT
1 1
2

CD44

CD43

205 206
RD23 @ @ RD41 GND1 GND2
207 208
BOSS1 BOSS2
SA0 SA1 10K_0402_5%~D 10K_0402_5%~D
2 2
1 0 DIMMA SUYIN_600025HB204G251ZL
1

CONN@
1 1 DIMMB
A A
0 0 DIMMC
0 1 DIMMD

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 14 of 61
5 4 3 2 1
5 4 3 2 1

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D
JDIMMC H=5.2mm D

+DIMM0_1_VREF_CPU
+1.35V +1.35V
JDIMM3
1 2
VREF_DQ VSS DDR_A_D4
3 4
VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
1 1 7 8
DQ1 VSS DDR_A_DQS#0
9 10
VSS DQS0#

CD50

CD53
All VREF traces should 11 12 DDR_A_DQS0
DM0 DQS0
13 14
have 20 mil trace width 2 2 DDR_A_D2 VSS VSS DDR_A_D6
15 16
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18
DQ3 DQ7
19 20
DDR_A_D8 VSS VSS DDR_A_D12
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
<7,12> DDR_A_DQS#[0..7] 23 24
DQ9 DQ13
25 26
DDR_A_DQS#1 VSS VSS
<7,12> DDR_A_D[0..63] 27 28
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30 DDR3_DRAMRST#_R <12,13,15>
DQS1 RESET#
<7,12> DDR_A_DQS[0..7] 31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
<7,12> DDR_A_MA[0..15] 35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS VSS
45 46
DDR_A_DQS2 DQS2# DM2
47 48
DQS2 VSS DDR_A_D22
49 50
DDR_A_D18 VSS DQ22 DDR_A_D23
Layout Note: DDR_A_D19
51
DQ18 DQ23
52
53 54
Place near JDIMMC DQ19 VSS DDR_A_D28
55 56
DDR_A_D24 VSS DQ28 DDR_A_D29
57 58
DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS DDR_A_DQS#3
61 62
VSS DQS3# DDR_A_DQS3
63 64
DM3 DQS3
65 66
+1.35V DDR_A_D26 VSS VSS DDR_A_D30
67 68
DDR_A_D27 DQ26 DQ30 DDR_A_D31
C 69 70 C
DQ27 DQ31
71 72
VSS VSS
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1 DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
VDD VDD
CD12

CD54

CD63

CD47

77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
<7,12> DDR_A_BS2 79 80
2 2 2 2 BA2 A14
81 82
DDR_A_MA12 VDD VDD DDR_A_MA11
83 84
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 86
A9 A7
87 88
DDR_A_MA8 VDD VDD DDR_A_MA6
89 90
DDR_A_MA5 A8 A6 DDR_A_MA4
91 92
A5 A4
93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
+1.35V A1 A0
99 100
M_CLK_DDR0 VDD VDD M_CLK_DDR1
<7> M_CLK_DDR0 101 102 M_CLK_DDR1 <7>
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
<7> M_CLK_DDR#0 103 104 M_CLK_DDR#1 <7>
CK0# CK1#
105 106 DDR_A_BS1 <7,12>
VDD VDD
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

DDR_A_MA10 107 108 DDR_A_BS1


A10/AP BA1 DDR_A_RAS# <7,12>
330U_SX_2VY~D

DDR_A_BS0 109 110 DDR_A_RAS#


<7,12> DDR_A_BS0 BA0 RAS#
1 111 112 DDR_CS0_DIMMA# <7>
VDD VDD
@ CD61

CD45

1 1 1 1 1 1 1 DDR_A_WE# 113 114 DDR_CS0_DIMMA#


<7,12> DDR_A_WE# WE# S0# M_ODT0 <7>
CD56

CD59

CD62

CD46

CD49

CD75

+ DDR_A_CAS# 115 116 M_ODT0


<7,12> DDR_A_CAS# CAS# ODT0
117 118 M_ODT1 <7> +V_SM_VREF_CNT
DDR_A_MA13 VDD VDD M_ODT1
119 120
2 2 2 2 2 2 2 2 DDR_CS1_DIMMA# A13 ODT1
<7> DDR_CS1_DIMMA# 121 122
S1# NC
123 124
VDD VDD
125 126
TEST VREF_CA
127
VSS VSS
128 All VREF traces should

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37 have 20 mil trace width
131 132
DQ33 DQ37
133 134 1 1
VSS VSS

CD52

CD58
DDR_A_DQS#4 135 136
DDR_A_DQS4 DQS4# DM4
137 138
DQS4 VSS DDR_A_D38
139 140
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
B DQ35 VSS DDR_A_D44
B
145 146
DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
Layout Note: 149 150
DQ41 VSS DDR_A_DQS#5
151 152
Place near JDIMMC.203,204 VSS DQS5# DDR_A_DQS5
153 154
DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48
DDR_A_D49
163
VSS
DQ48
VSS
DQ52
164 DDR_A_D52
DDR_A_D53
2(H8)
165 166
DDR_A_DQS#6
167
DQ49
VSS
DQ53
VSS
168 1(H4)
169 170
+0.675VS DDR_A_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_A_D54
173 174
+3VS DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS CPU
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

179 180 DDR_A_D60


1 1 1 1 DDR_A_D56
DDR_A_D57
181
VSS
DQ56
DQ60
DQ61
182 DDR_A_D61 JDIMMC(H5.2)
183 184
DQ57 VSS 4(H9.2)
2

2
CD64

CD51

CD57

CD55

185 186 DDR_A_DQS#7


RD25 @ @ RD43 VSS DQS7# DDR_A_DQS7
187 188
2 2 2 2 10K_0402_5%~D 10K_0402_5%~D DM7 DQS7
189 190
DDR_A_D58 VSS VSS DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
1

DQ59 DQ63
195 196
VSS VSS M_THERMAL#
197 198 M_THERMAL# <12,13,15,43>
SA0 EVENT#
+3VS 199 200 PCH_SMBDATA <6,12,13,15,19,49,50,51,53>
VDDSPD SDA
201 202 PCH_SMBCLK <6,12,13,15,19,49,50,51,53>
SA1 SCL
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

+0.675VS 203 204 +0.675VS


VTT VTT
1 1
2

CD48

CD60

205 206
RD42 RD26 GND1 GND2
207 208
10K_0402_5%~D 10K_0402_5%~D BOSS1 BOSS2
2 2
SA0 SA1 LCN_DAN06-K4526-0103
1

CONN@
1 0 DIMMA
A 1 1 DIMMB A

0 0 DIMMC
0 1 DIMMD

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 15 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

JDIMMD H=9.2mm
D D
+DIMM0_1_CA_CPU
+1.35V +1.35V
JDIMM4
1 2
VREF_DQ VSS1 DDR_B_D4
3 4
VSS2 DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
7 8
DQ1 VSS3 DDR_B_DQS#0
1 1 9 10
VSS4 DQS#0

CD84

CD76
11 12 DDR_B_DQS0
DM0 DQS0
13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6
All VREF traces should 15 16
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 18
have 20 mil trace width DQ3 DQ7
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
DQ9 DQ13
<7,13> DDR_B_DQS#[0..7] 25 26
DDR_B_DQS#1 VSS9 VSS10
27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#_R
<7,13> DDR_B_D[0..63] 29 30 DDR3_DRAMRST#_R <12,13,14>
DQS1 RESET#
31 32
DDR_B_D10 VSS11 VSS12 DDR_B_D14
<7,13> DDR_B_DQS[0..7] 33 34
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
<7,13> DDR_B_MA[0..15] 37 38
DDR_B_D16 VSS13 VSS14 DDR_B_D20
39 40
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS15 VSS16
45 46
DDR_B_DQS2 DQS#2 DM2
47 48
DQS2 VSS17 DDR_B_D22
49 50
DDR_B_D18 VSS18 DQ22 DDR_B_D23
Layout Note: DDR_B_D19
51
DQ18 DQ23
52
53 54
Place near JDIMMD DQ19 VSS19 DDR_B_D28
55 56
DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 58
DDR_B_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_B_DQS#3
61 62
VSS22 DQS#3 DDR_B_DQS3
63 64
DM3 DQS3
65 66
DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 68
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 70
+1.35V DQ27 DQ31
C 71 72 C
VSS25 VSS26
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
1 1 1 1 75 76
VDD1 VDD2 DDR_B_MA15
77 78
NC1 A15
CD82

CD80

CD78

CD71

DDR_B_BS2 79 80 DDR_B_MA14
<7,13> DDR_B_BS2 BA2 A14
81 82
2 2 2 2 DDR_B_MA12 VDD3 VDD4 DDR_B_MA11
83 84
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 88
DDR_B_MA8 VDD5 VDD6 DDR_B_MA6
89 90
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 94
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
95 96
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
+1.35V A1 A0
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
<7> M_CLK_DDR2 101 102 M_CLK_DDR3 <7>
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
<7> M_CLK_DDR#2 103 104 M_CLK_DDR#3 <7>
CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 <7,13>
A10/AP BA1
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

DDR_B_BS0 109 110 DDR_B_RAS#


<7,13> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7,13>
330U_SX_2VY~D

1 111 112
VDD13 VDD14
@ CD70

1 1 1 1 1 1 1 DDR_B_WE# 113 114 DDR_CS2_DIMMB#


<7,13> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
CD67

CD87

CD81

CD79

CD65

CD88

CD68

+ DDR_B_CAS# 115 116 M_ODT2


<7,13> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3 +V_SM_VREF_CNT
119 120 M_ODT3 <7>
2 2 2 2 2 2 2 2 DDR_CS3_DIMMB# A13 ODT1
<7> DDR_CS3_DIMMB# 121 122
S1# NC2
123 124
VDD17 VDD18
125
NCTEST VREF_CA
126 All VREF traces should
127 128
VSS27 VSS28 have 20 mil trace width

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134 1 1
VSS29 VSS30

CD72

CD83
DDR_B_DQS#4 135 136
DDR_B_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_B_D38
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
Layout Note: 143 144
B DQ35 VSS33 DDR_B_D44
B
145 146
Place near JDIMMD.203,204 DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 148
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 152
VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
+0.675VS DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 165
DQ48
DQ49
DQ52
DQ53
166 DDR_B_D53 2(H8)
167 168
DDR_B_DQS#6 169
VSS41
DQS#6
VSS42
DM6
170 1(H4)
DDR_B_DQS6 171 172
DQS6 VSS43
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

173 174 DDR_B_D54


+3VS DDR_B_D50 VSS44 DQ54 DDR_B_D55
1 1 1 1 175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45
CD89

CD77

CD86

CD85

179 180 DDR_B_D60


2 2 2 2
DDR_B_D56
DDR_B_D57
181
VSS46
DQ56
DQ60
DQ61
182 DDR_B_D61 CPU 3(H5.2)
183 184
DQ57 VSS47
2

185 186 DDR_B_DQS#7


RD31 @ RD32 187
VSS48
DM7
DQS#7
DQS7
188 DDR_B_DQS7 JDIMMD(H9.2)
10K_0402_5%~D 10K_0402_5%~D 189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
1

DQ59 DQ63
195 196
VSS51 VSS52 M_THERMAL#
197 198 M_THERMAL# <12,13,14,43>
SA0 EVENT#
+3VS 199 200 PCH_SMBDATA <6,12,13,14,19,49,50,51,53>
VDDSPD SDA
201 202 PCH_SMBCLK <6,12,13,14,19,49,50,51,53>
SA1 SCL
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

+0.675VS 203 204 +0.675VS


VTT1 VTT2
1 1
2

CD69

CD66

SA0 SA1 205


G1 G2
206
RD44 @ RD45
1 0 DIMMA 10K_0402_5%~D 10K_0402_5%~D
2 2
FOX_AS0A626-UARN-7F
CONN@
1 1 DIMMB
1

0 0 DIMMC
A 0 1 DIMMD A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 16 of 61
5 4 3 2 1
5 4 3 2 1

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+RTC_CELL

1 330K_0402_1%~D
RH38
2
D D

PCH_INTVRMEN
330K_0402_1%~D
1
@ RH39
2

INTVRMEN - INTEGRATED SUS 1.05V VRM


ENABLE
High - Enable Internal VRs
Low - Enable External VRs

+3VS +3V_PCH

1 2 HDA_SPKR 1 2 PCH_AZ_SDOUT
@ RH35 10K_0402_5%~D @ RH287 1K_0402_1%~D

+3VS
NO REBOOT STRAP FLASH DESCRIPTOR SECURITY OVERRIDE
DISABLED WHEN LOW (DEFAULT) LOW = DESABLED (DEFAULT) PCH_GPIO21 1 2
10K_0402_5%~D RH30
ENABLED WHEN HIGH HIGH = ENABLED BBS_BIT0_R 2 1
CH2 4.7K_0402_5%~D RH52
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1 PCH_SATALED# 1 2
RH286 0_0402_5%~D 10K_0402_5%~D RH55
18P_0402_50V8J~D

1
+3VS
LPT_PCH_M_EDS
C YH1 RH2 UH1A C
32.768KHZ_12.5PF_Q13FC1350000~D 10M_0402_5%~D
1 2 PCH_GPIO33 BC8 SATA_PRX_DTX_N0

2
5 SATA_RXN_0 SATA_PRX_DTX_N0 <49>
RH355 100K_0402_5%~D B5 BE8 SATA_PRX_DTX_P0

2
RTCX1 SATA_RXP_0 SATA_PRX_DTX_P0 <49>
CH3 HDD1(Master)
1 2 PCH_RTCX2 B4 AW8 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 <49>
RTCX2 SATA_TXN_0 SATA_PTX_DRX_P0
AY8

RTC
SATA_TXP_0 SATA_PTX_DRX_P0 <49>
RH22 1 2 20K_0402_5%~D 18P_0402_50V8J~D SRTCRST# B9
+RTC_CELL SRTCRST#
BC10 SATA_PRX_DTX_N1
INTRUDER# SATA_RXN_1 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 <49>
RH11 1 2 1M_0402_5%~D A8 BE10
INTRUDER# SATA_RXP_1 SATA_PRX_DTX_P1 <49>
PCH_INTVRMEN G10 AV10 SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 <49>
HDD2(Slave)
INTVRMEN SATA_TXN_1 SATA_PTX_DRX_P1
AW10 SATA_PTX_DRX_P1 <49>
RH23 1 PCH_RTCRST# SATA_TXP_1
2 20K_0402_5%~D D9
RTCRST#

SATA
BB9 SATA_ODD_PRX_DTX_N2
SATA_RXN_2 SATA_ODD_PRX_DTX_N2 <50>
BD9 SATA_ODD_PRX_DTX_P2
SATA_RXP_2 SATA_ODD_PRX_DTX_P2 <50>
CMOS_CLR1 CMOS setting PCH_AZ_BITCLK B25 ODD/HDD3 Bay
HDA_BCLK SATA_ODD_PTX_DRX_N2
AY13 SATA_ODD_PTX_DRX_N2 <50>
PCH_AZ_SYNC SATA_TXN_2 SATA_ODD_PTX_DRX_P2
Shunt Clear CMOS 1
1 2
2 1
1 2
2 A22
HDA_SYNC SATA_TXP_2
AW13 SATA_ODD_PTX_DRX_P2 <50>

Open Keep CMOS HDA_SPKR AL10 BC12 MSATA_PRX_DTX_N3


<45> HDA_SPKR SPKR SATA_RXN_3 MSATA_PRX_DTX_N3 <50>
BE12 MSATA_PRX_DTX_P3
SATA_RXP_3 MSATA_PRX_DTX_P3 <50>
@ @ PCH_AZ_RST# C24 mSATA
ME1 SHORT PADS~D CMOS1 SHORT PADS~D HDA_RST# MSATA_PTX_DRX_N3
ME_CLR1 TPM setting SATA_TXN_3
AR13 MSATA_PTX_DRX_N3 <50>

AZALIA
1 2 1 2 PCH_AZ_CODEC_SDIN0 L22 AT13 MSATA_PTX_DRX_P3 MSATA_PTX_DRX_P3 <50>
1U_0402_6.3V6K~D <45> PCH_AZ_CODEC_SDIN0 HDA_SDI0 SATA_TXP_3
Shunt Clear ME RTC Registers CH5 1U_0402_6.3V6K~D CH4
CMOS place near DIMM K22
HDA_SDI1 PCIE_PRX_WLANTX_N1
Open Keep ME RTC Registers BD13 PCIE_PRX_WLANTX_N1 <51>
SATA_RXN4/PERN1 PCIE_PRX_WLANTX_P1
G22 BB13 PCIE_PRX_WLANTX_P1 <51>
HDA_SDI2 SATA_RXP4/PERP1
MiniWLAN (Mini Card 1)
F22 AV15 PCIE_PTX_WLANRX_N1 PCIE_PTX_WLANRX_N1 <51>
HDA_SDI3 SATA_TXN4/PETN1 PCIE_PTX_WLANRX_P1
AW15 PCIE_PTX_WLANRX_P1 <51>
PCH_AZ_SDOUT SATA_TXP4/PETP1
<43> HDA_SDO 1 2 A24
RH50 1K_0402_1%~D HDA_SDO PCIE_PRX_WANTX_N2
BC14 PCIE_PRX_WANTX_N2 <51>
PCH_GPIO33 SATA_RXN5/PERN2 PCIE_PRX_WANTX_P2
B17 BE14 PCIE_PRX_WANTX_P2 <51>
DOCKEN#/GPIO33 SATA_RXP5/PERP2
MiniDMC (Mini Card 2)
HDA_SYNC Isolation Circuit +5VS +3V_PCH
<30> DP_PCH_HPD
DP_PCH_HPD C22
HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2
AP15
AR15
PCIE_PTX_WANRX_N2
PCIE_PTX_WANRX_P2
PCIE_PTX_WANRX_N2 <51>
SATA_TXP5/PETP2 PCIE_PTX_WANRX_P2 <51>
1 0_0603_5%~D
2

B B
G

RH288

AY5 SATA_COMP
SATA_RCOMP
PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC AP3 PCH_SATALED#
SATALED# PCH_SATALED# <48>
S

RH59 2 1 51_0402_1%~D PCH_JTAG_TCK AB3 AT1 PCH_GPIO21


QH8 JTAG_TCK SATA0GP/GPIO21
1M_0402_5%~D

SSM3K7002FU_SC70-3~D +3.3V_ALW_PCH_JTAG RH44 1 2 210_0402_1%~D PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R


JTAG_TMS SATA1GP/GPIO19
2

@
RH31

RH45 1 2 210_0402_1%~D PCH_JTAG_TDI SATA_IREF

JTAG
AE2 BD4 2 1 +1.5VS
JTAG_TDI SATA_IREF
@

0_0402_5% RH41
RH46 1 2 210_0402_1%~D PCH_JTAG_TDO AD3 BA2
JTAG_TDO TP9
@

PAD~D T161 @
1

1 2 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

RH289 0_0402_5%~D PAD~D T155 @


1

C26
TP22
RH48

RH49

RH47

@ T122 PAD~D
AB6
TP20
SATA Impedance Compensation
2

LYNXPOINT_BGA695 1 OF 11 +1.5VS

RTC Battery SATA_COMP


7.5K_0402_1%~D
1 2
RH40

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
+RTCBATT routing next to clock pins.
HDA for Codec
2

+3VLP RH34 1 2 PCH_AZ_SDOUT


<45> PCH_AZ_CODEC_SDOUT
1K_0402_5% RH29 33_0402_5%~D
1 2 PCH_AZ_SYNC_Q
<45> PCH_AZ_CODEC_SYNC
RH56 33_0402_5%~D
1

W=20mils <45> PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST#


W=20mils RH27 33_0402_5%~D
3

A
<45> PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK A
DH1 RH26 33_0402_5%~D
27P_0402_50V8J~D

BAT54CW_SOT323-3
@ CH101

1
1

+RTC_CELL 2
W=20mils 1
CH12
1U_0603_10V6K
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) RTC,HDA,SATA,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 17 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn
RH357 1 2 0_0402_5%~D
+3VS
@ CH143
1 2

5
0.1U_0402_25V6K~D
1

P
D <6> XDP_DBRESET# B D
4 SYS_RESET#
O
2 1 ME_RESET# 2
A

G
@ RH199 8.2K_0402_5%~D @ UH13
+3V_PCH 74AHC1G09GW_TSSOP5~D

3
1 2 SUS_STAT#
LPT_PCH_M_EV
@ RH318 10K_0402_5%~D UH1E 5
1 2 SUSPWRDNACK
RH153 10K_0402_5%~D T45 R40 PCH_DPB_HDMI_CLK PCH_DPB_HDMI_CLK <36>
PCIE_WAKE# VGA_BLUE DDPB_CTRLCLK
RH148
1 2
10K_0402_5%~D U44
VGA_GREEN DDPB_CTRLDATA
R39 PCH_DPB_HDMI_DAT PCH_DPB_HDMI_DAT <36>
HDMI
V45 R35
PCH_RI# VGA_RED DDPC_CTRLCLK
1 2
RH172 10K_0402_5%~D M43 R36
VGA_DDC_CLK DDPC_CTRLDATA
M45 N40 PCH_DPD_CLK

CRT
VGA_DDC_DATA DDPD_CTRLCLK PCH_DPD_CLK <39>
+3VS
N42
VGA_HSYNC DDPD_CTRLDATA
N38 PCH_DPD_DAT PCH_DPD_DAT <39>
DMC
1 2 PM_CLKRUN# ME_SUS_PWR_ACK_R 1 2 SUSACK#_R
RH138 8.2K_0402_5%~D RH323 0_0402_5%~D N44
ME_RESET# VGA_VSYNC
1 2 H45
@ RH152 8.2K_0402_5%~D DDPB_AUXN
1 2 U40
RH139 649_0402_1%~D DAC_IREF
K43
DDPC_AUXN
U39
VGA_IRTN

DISPLAY
J42
DDPD_AUXN
PCH_EDP_PWM N36 H43
UH1B LPT_PCH_M_EDS
5 <40> PCH_EDP_PWM EDP_BKLTCTL DDPB_AUXP

LVDS
K36 K45
DMI_CTX_PRX_N0 EDP_BKLTEN DDPC_AUXP
<5> DMI_CTX_PRX_N0 AW22
DMI_CTX_PRX_N1 DMI_RXN_0
<5> DMI_CTX_PRX_N1 AR20 G36 J44
DMI_RXN_1 EDP_VDDEN DDPD_AUXP
AJ35
DMI_CTX_PRX_N2 FDI_RXN_0
<5> DMI_CTX_PRX_N2 AP17 K40 PCH_HDMI_HPD PCH_HDMI_HPD <36>
DMI_CTX_PRX_N3 DMI_RXN_2 PCI_PIRQA# DDPB_HPD
<5> DMI_CTX_PRX_N3 AV20 AL35 H20
DMI_RXN_3 FDI_RXN_1 PIRQA#
K38
DMI_CTX_PRX_P0 PCI_PIRQB# DDPC_HPD
<5> DMI_CTX_PRX_P0 AY22 AJ36 L20
DMI_CTX_PRX_P1 DMI_RXP_0 FDI_RXP_0 PIRQB#
<5> DMI_CTX_PRX_P1 AP20 H39 PCH_DMC_HPD
DMI_RXP_1 FDI
PCI_PIRQC# DDPD_HPD PCH_DMC_HPD <39>
AL36 K17
DMI_CTX_PRX_P2 FDI_RXP_1 PIRQC#
C
<5> DMI_CTX_PRX_P2 AR17 C
DMI_CTX_PRX_P3 DMI_RXP_2 PAD~D T144 @ PCI_PIRQD#
<5> DMI_CTX_PRX_P3 AW20 DMI AV43 M20
DMI_RXP_3 TP16 PIRQD# PCI
G17 BT_ON# BT_ON# <51>
DMI_CRX_PTX_N0 PAD~D T141 @ PIRQE#/GPIO2
<5> DMI_CRX_PTX_N0 BD21 AY45 A12
DMI_CRX_PTX_N1 DMI_TXN_0 TP5 GPIO50 DP_CBL_DET
<5> DMI_CRX_PTX_N1 BE20 F17 DP_CBL_DET <30>
DMI_TXN_1 PAD~D T147 @ DGPU_SELECT# B13 PIRQF#/GPIO3
AV45 <32,36,42> DGPU_SELECT#
DMI_CRX_PTX_N2 TP15 GPIO52 ODD_DA#
<5> DMI_CRX_PTX_N2 BD17 L15 ODD_DA# <50>
DMI_CRX_PTX_N3 DMI_TXN_2 PAD~D T148 @ PIRQG#/GPIO4
<5> DMI_CRX_PTX_N3 BE18 AW44 C12
DMI_TXN_3 TP10 GPIO54
M15 FFS_INT1 FFS_INT1 <49>
DMI_CRX_PTX_P0 FDI_CSYNC BBS_BIT1 PIRQH#/GPIO5
<5> DMI_CRX_PTX_P0 BB21 AL39 C10
DMI_CRX_PTX_P1 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <5> GPIO51 @ T124 PAD~D
<5> DMI_CRX_PTX_P1 BC20 AD10
DMI_TXP_1 FDI_INT HDMI_IN_PWMSEL# PME#
AL40 A10
DMI_CRX_PTX_P2 FDI_INT FDI_INT <5> <42> HDMI_IN_PWMSEL# GPIO53
<5> DMI_CRX_PTX_P2 BB17 Y11 PCH_PLTRST#
DMI_CRX_PTX_P3 DMI_TXP_2 FDI_IREF WL_OFF# PLTRST#
<5> DMI_CRX_PTX_P3 BC18 AT45 2 1 +1.5VS AL6
DMI_TXP_3 FDI_IREF 0_0402_5% RH42 <51> WL_OFF# GPIO55
2 1 DMI_IREF BE16 AU42 PAD~D T145 @
+1.5VS DMI_IREF TP17
RH43 0_0402_5% LYNXPOINT_BGA695 5 OF 11
AW17 AU44 PAD~D T146 @
@ T139 PAD~D TP12 TP13
AV17 AR44 FDI_RCOMP 2 1 +3VS +3VS
TP7 FDI_RCOMP +1.5VS
@ T123 PAD~D 7.5K_0402_1%~D RH206 CH144
+1.5VS 1 2 DMI_RCOMP AY17 1 2
DMI_RCOMP

1
RH204 7.5K_0402_1%~D
0.1U_0402_25V6K~D RH367
10K_0402_5%~D
1 2 SUSACK#_R R6 C8 DSWODVREN @
<42,43> SG_AMD_BKL SUSACK# DSWVRMEN

5
@ RH114 0_0402_5%~D RH167 1 0_0402_5%~D
2 PCH_RSMRST#_R

2
System Power
SYS_RESET# AM1 L13 PCH_DRWROK_R 1 2 PCH_PLTRST# 1

P
SYS_RESET# Management DPWROK PCH_DPWROK <43> B
RH186 @ 0_0402_5%~D 4 PLT_RST
SYS_PWROK_R PCIE_WAKE# O PLT_RST# <6,43,44,51,53>
<6> SYS_PWROK 1 2 AD7
SYS_PWROK WAKE#
K3 PCIE_WAKE# <43,44,51> 2
A

G
RH193 0_0402_5%~D UH3

1
1 2 PCH_PWROK_R F10 AN7 PM_CLKRUN# TC7SH08FU_SSOP5~D

3
<43> PCH_PWROK PWROK CLKRUN#
RH144 0_0402_5%~D
1 2 PM_APWROK_R AB7 U7 SUS_STAT# T129 PAD~D@ RH201
RH149 0_0402_5%~D APWROK SUS_STAT#/GPIO61 100K_0402_5%~D
1 2 PM_DRAM_PWRGD_R H3 Y6

2
<6> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62
RH320 0_0402_5%~D T126 PAD~D@
1 2 PCH_RSMRST#_R J2 Y7 PM_SLP_S5# +3V_MXM
<43> PCH_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# <43,47>
RH185 0_0402_5%~D
ME_SUS_PWR_ACK_R J4 PM_SLP_S4# T125 PAD~D @
<43> SUSPWRDNACK 1 2 C6
B
RH200 0_0402_5%~D SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# <43> +3VS B

2
1 2 SIO_PWRBTN#_R K1 H1 PM_SLP_S3# CH147
<6,43> PBTN_OUT# PWRBTN# SLP_S3# PM_SLP_S3# <43,47>
RH163 0_0402_5%~D 1 2 RH215
ACIN_PCH E6 F3 100K_0402_5%~D
ACPRESENT/GPIO31 SLP_A#

5
0.1U_0402_25V6K~D @ +3VS
PCH_BATLOW# PM_SLP_SUS# T128 PAD~D @ DGPU_HOLD_RST#
1 2 K7 F1 1

P
+PCH_VCCDSW3_3

1
BATLOW#/GPIO72 SLP_SUS# PM_SLP_SUS# <43> <43> DGPU_HOLD_RST# B
RH156 8.2K_0402_5%~D T127 PAD~D @ 4 PLTRST_VGA# PLTRST_VGA# <29> BT_ON# 2 1
PCH_RI# H_PM_SYNC PCH_PLTRST# O 8.2K_0402_5%~D RH366
N4 AY3 2
RI# PMSYNCH H_PM_SYNC <6> A

G
UH6 ODD_DA# 2 1

1
@ T140 PAD~D AB10 G5 TC7SH08FU_SSOP5~D 8.2K_0402_5%~D RH365

3
TP21 SLP_LAN# WL_OFF# 2 1
D2 RH196 8.2K_0402_5%~D RH362
SLP_WLAN#/GPIO29 100K_0402_5%~D HDMI_IN_PWMSEL# 2 1
+3VS 8.2K_0402_5%~D RH352

2
LYNXPOINT_BGA695 4 OF 11 +RTC_CELL PCI_PIRQA# 2 1
8.2K_0402_5%~D RH324

330K_0402_1%~D
1 PCI_PIRQB# 2 1

2
8.2K_0402_5%~D RH325

RH191
CH41 PCI_PIRQC# 2 1
0.1U_0402_16V7K 8.2K_0402_5%~D RH326
2 PCI_PIRQD# 2 1
8.2K_0402_5%~D RH329
1
5

UH8 DGPU_HOLD_RST# 2 1
A16 SWAP OVERRIDE STRAP 10K_0402_5%~D @ RH327
Boot BIOS Strap
VCC

PCH_PWROK 1
IN1 SYS_PWROK DSWODVREN
4
OUT
2 GNT1#/GPIO51 SATA1GP/GPIO19 STP_A16OVR LOW = A16 SWAP OVERRIDE
GND

<6,43,62> IMVP_PWRGD IN2


330K_0402_1%~D

BBS_BIT1 Boot BIOS Location


(BBS_BIT1) (BBS_BIT0) HIGH = DEFAULT
@ RH178
2
1K_0402_1%~D

MC74VHC1G08DFT2G_SC70-5
3

0 0 LPC
@ RH342

+3V_PCH
0 1 Reserved (NAND)
1
2

1 2 PM_CLKRUN#
1

+3V_PCH RH351 @ 10K_0402_5%~D


1 0 PCI
R1900
10K_0402_5%
A
* 1 1 SPI DSWODVREN - ON DIE DSW VR ENABLE A
1

R1899 ACIN_PCH HIGH = ENABLED (DEFAULT)


10K_0402_5%
LOW = DISABLED
3

GPIO51 has internal pull up.


2

DMN66D0LDW-7_SOT363-6~D
5
QH13B
6

<29,43,47,57,63> ACIN 2
DMN66D0LDW-7_SOT363-6~D
QH13A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title
PCH (2/9) DMI,FDI,PM,DP,CRT
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 18 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

D D

LPT_PCH_M_EDS
UH1C 5

RH307 2 1 0_0402_5%~D PCIE_MINI1# Y43 AB35 CLK_PEG_PCH#


<51> CLK_PCIE_MINI1# CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PEG_PCH# <29>
MiniWLAN (Mini Card 1) RH308 2 1 0_0402_5%~D PCIE_MINI1 Y45 AB36 CLK_PEG_PCH
<51> CLK_PCIE_MINI1 RH142 CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PEG_PCH <29>
+3V_PCH 2 1 10K_0402_5%~D
MINI1CLK_REQ# AB1 AF6 PEG_CLKREQ#
<51> MINI1CLK_REQ# PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 PEG_CLKREQ# <29>
RH99 2 1 0_0402_5%~D PCIE_MINI2# AA44 Y39 1 2 +3V_PCH
<51> CLK_PCIE_MINI2# PCIE_MINI2 CLKOUT_PCIE_N_1 CLKOUT_PEG_B
DMC (Mini Card 2) RH98 2 1 0_0402_5%~D AA42 RH76 10K_0402_5%~D
<51> CLK_PCIE_MINI2 CLKOUT_PCIE_P_1
+3VS RH145 2 110K_0402_5%~D Y38
MINI2CLK_REQ# CLKOUT_PEG_B_P CLK_BUF_DMI# RH74 1
<51> MINI2CLK_REQ# AF1 2 10K_0402_5%~D
PCIECLKRQ1#/GPIO18 CLK_BUF_DMI RH75 1
U4 2 1 +3V_PCH 2 10K_0402_5%~D
RH158 PCIE_LAN# PEGB_CLKRQ#/GPIO56
2 1 0_0402_5%~D AB43 10K_0402_5%~D RH125
<44> CLK_PCIE_LAN# CLKOUT_PCIE_N_2
CLKOUT_DMI AF39 CLK_CPU_DMI#
RH147 PCIE_LAN CLK_CPU_DMI# <6> CLK_BUF_BCLK#
10/100/1G LAN 2 1 0_0402_5%~D AB45
CLKOUT_PCIE_P_2
RH105 1 2 10K_0402_5%~D
<44> CLK_PCIE_LAN CLK_CPU_DMI CLK_BUF_BCLK RH157 1
+3VS 1 2 AF40 2 10K_0402_5%~D
RH28 10K_0402_5%~D LANCLK_REQ# CLKOUT_DMI_P CLK_CPU_DMI <6>
<44> LANCLK_REQ# AF3
PCIECLKRQ2#/GPIO20/SMI# CLK_CPU_SSC_DPLL#
CLKOUT_DP AJ40
RH129 PCIE_EXP# CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# <6> CLK_BUF_DOT96#
<53> CLK_PCIE_CD# 2 1 0_0402_5%~D AD43 AJ39 RH143 1 2 10K_0402_5%~D
RH124 PCIE_EXP CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <6> CLK_BUF_DOT96
C
<53> CLK_PCIE_CD 2 1 0_0402_5%~D AD45 RH130 1 2 10K_0402_5%~D C
CDCLK_REQ# CLKOUT_PCIE_P_3 CLK_CPU_DPLL#
Card Reader <53> CDCLK_REQ# T3
PCIECLKRQ3#/GPIO25 CLKOUT_DPNS
AF35
CLK_CPU_DPLL# <6>
RH126 2 1 10K_0402_5%~D AF36 CLK_CPU_DPLL
+3V_PCH CLKOUT_DPNS_P CLK_CPU_DPLL <6>
AF43 CLK_BUF_CKSSCD# RH146 1 2 10K_0402_5%~D
CLKOUT_PCIE_N_4 CLK_BUF_DMI# CLK_BUF_CKSSCD RH155 1
AF45
CLKOUT_PCIE_P_4 CLKIN_DMI AY24 2 10K_0402_5%~D
RH128 2 1 10K_0402_5%~D V3 AW24 CLK_BUF_DMI
+3V_PCH PCIECLKRQ4#/GPIO26 CLKIN_DMI_P
AE44 AR24 CLK_BUF_BCLK# CLK_PCH_14M RH205 1 2 10K_0402_5%~D
CLKOUT_PCIE_N5 CLKIN_GND CLK_BUF_BCLK
AE42 AT24
RH132 CLKOUT_PCIE_P_5 CLKIN_GND_P
+3V_PCH 2 1 10K_0402_5%~D AA2
PCIECLKRQ5#/GPIO44 CLK_BUF_DOT96#
H33
CLKIN_DOT96N CLK_BUF_DOT96
AB40 G33
CLKOUT_PCIE_N_6 CLKIN_DOT96P
AB39
RH133 CLKOUT_PCIE_P_6 CLK_BUF_CKSSCD#
+3V_PCH 2 1 10K_0402_5%~D AE4 BE6
PCIECLKRQ6#/GPIO45 CLKIN_SATA CLK_BUF_CKSSCD
BC6
AJ44
CLKIN_SATA_P CLOCK TERMINATION for FCIM and need close to PCH
CLKOUT_PCIE_N_7 CLK_PCH_14M
F45
REFCLK14IN CLK_PCI_LPBACK
AJ42 D17
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
RH127 2 1 10K_0402_5%~D Y3 AL44 XTAL25_IN 2 1
+3V_PCH PCIECLKRQ7#/GPIO46 XTAL25_IN
AM43 XTAL25_OUT RH309 1 2 0_0402_5%~D
RH280 CLK_BCLK_ITP# XTAL25_OUT
1 0_0402_5%~D RH131 1M_0402_5%~D

XTAL25_IN_R
<6> CLK_CPU_ITP# 2 AH43
CLKOUT_ITPXDP
C40
RH281 CLK_BCLK_ITP CLKOUTFLEX0/GPIO64
<6> CLK_CPU_ITP 2 1 0_0402_5%~D AH45 PAD~D T176 @
CLKOUT_ITPXDP_P DMC_PCH_DET#
F38 DMC_PCH_DET# <51>
CLK_PCI_LPBACK RH169 CLK_PCI0 CLKOUTFLEX1/GPIO65
2 1 22_0402_5%~D D44
CLKOUT_33MHZ0 PCH_GPIO66 YH4
F36
CLK_PCI_LPC RH111 CLK_PCI1 CLKOUTFLEX2/GPIO66
<43> CLK_PCI_LPC 2 1 22_0402_5%~D E44 25MHZ_10PF_Q22FA2380049900~D
CLKOUT_33MHZ1 CAM_DET#
F39 3 OUT
CLK_DEBUG RH151 CLK_PCI2 CLKOUTFLEX3/GPIO67 CAM_DET# <33,42> IN 1
<51> CLK_DEBUG 2 1 22_0402_5%~D B42
CLKOUT_33MHZ2

8.2P_0402_50V8D~D

8.2P_0402_50V8D~D
AM45 ICLK_IREF 1 2 4 2
ICLK_IREF +1.5VS GND GND
@ T142 PAD~D CLK_PCI3 F41 RH54 0_0402_5% 2 2
CLKOUT_33MHZ3

CH19
AD39

CH18
@ T138 PAD~D CLK_PCI4 TP19 PAD~D T149 @
A40 AD38
CLKOUT_33MHZ4 TP18 PAD~D T150 @
AN44 PCH_CLK_BIASREF 1 2 1 1
DIFFCLK_BIASREF +1.05V_+1.5V_RUN
CLOCK SIGNAL 7.5K_0402_1%~D RH208

LYNXPOINT_BGA695 2 OF 11
B B

+3VS

CAM_DET# 10K_0402_5%~D1 2 RH216


DMC_PCH_DET# 10K_0402_5%~D1 2 RH217

PCH_GPIO66 10K_0402_5%~D1 2 RH218

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 19 of 61
5 4 3 2 1
5 4 3 2 1

+3VS

www.laptopblue.vn

2
SML1CLK 6 1 EC_SMB_CK2 <40,43,53,54>
QH10A

5
DMN66D0LDW-7_SOT363-6~D

SML1DATA 3 4
D EC_SMB_DA2 <40,43,53,54> D
+3VS
+3VS QH10B
DMN66D0LDW-7_SOT363-6~D

1
RH304 RH310

2
2.2K_0402_5%~D 2.2K_0402_5%~D

2
MEM_SMBCLK 6 1 PCH_SMBCLK <6,12,13,14,15,49,50,51,53>
QH9A

5
DMN66D0LDW-7_SOT363-6~D

MEM_SMBDATA 3 4 PCH_SMBDATA <6,12,13,14,15,49,50,51,53> +3V_PCH


QH9B
+3VS DMN66D0LDW-7_SOT363-6~D MEM_SMBCLK 2 1
2.2K_0402_5%~D RH302
1 2 SERIRQ MEM_SMBDATA 2 1
RH337 10K_0402_5%~D 2.2K_0402_5%~D RH303
DDR_HVREF_RST_PCH 2 1
1K_0402_1%~D RH300
LPT_PCH_M_EDS
UH1D PCH_GPIO74 2 1
10K_0402_5%~D RH301
RH3681 20_0402_5%~D SML1CLK 1 2
EC_LID_OUT# <43>
2.2K_0402_5%~D RH298
N7 PCH_LID_SW_IN# RH3691 20_0402_5%~D SML1DATA 1 2
LPC_AD0 SMBALERT#/GPIO11 LID_SW_IN# <43,47,48,53>
A20 @ 2.2K_0402_5%~D RH299
<43,51> LPC_AD0 LAD_0
SMBus R10 MEM_SMBCLK
LPC_AD1 SMBCLK
<43,51> LPC_AD1 C20 LAD_1
C MEM_SMBDATA C
SMBDATA U11
LPC_AD2 A18

LPC
<43,51> LPC_AD2 LAD_2 +3V_PCH
N8 DDR_HVREF_RST_PCH
LPC_AD3 SML0ALERT#/GPIO60
<43,51> LPC_AD3 C18 LAD_3
U8 SML0CLK SML0CLK 2 1
LPC_FRAME# SML0CLK 2.2K_0402_5%~D RH305
B21 LFRAME#
<43,51> LPC_FRAME# SML0DATA SML0DATA
SML0DATA R7 2 1
D21 2.2K_0402_5%~D RH306
LDRQ0# PCH_GPIO74
H6
PANEL_SW SML1ALERT#/PCHHOT#/GPIO74
G20
<31,34> PANEL_SW LDRQ1#/GPIO23 SML1CLK
K6
SERIRQ SML1CLK/GPIO58
<43> SERIRQ AL11
SERIRQ SML1DATA
N11
SML1DATA/GPIO75

AF11
PCH_SPI_CLK CL_CLK
AJ11
SPI

SPI_CLK
AF10
PCH_SPI_CS0# C-Link CL_DATA
AJ7
SPI_CS0#
AF7
CL_RST#
AL7
SPI_CS1#
AJ10
SPI_CS2# PAD~D T130 @
BA45
PCH_SPI_SI TP1
AH1
SPI_MOSI PAD~D T133 @
BC45
PCH_SPI_SO Thermal TP2
AH3
SPI_MISO PAD~D T131 @
BE43
PCH_SPI_DO2 TP4
AJ4
SPI_IO2 PAD~D T132 @
BE44
PCH_SPI_DO3 TP3
AJ2
SPI_IO3 PCH_TD_IREF 1
AY43 2
B TD_IREF RH322 8.2K_0402_1% B

LYNXPOINT_BGA695 3 OF 11 5

+3V_PCH
+3V_PCH

PCH_SPI_CLK
3.3K_0402_5%

1 2 PCH_SPI_DO3_R +3V_PCH
2

RH370 3.3K_0402_5%~D

2
RH58

2 PCH_SPI_DO2_R CH56
RH371
1
3.3K_0402_5%~D 200 MIL SO8 1 2 RH60 @
33_0402_5%~D
64Mb Flash ROM 0.1U_0402_25V6K~D
1

UH14

1
PCH_SPI_CS0# RH3731 2 0_0402_5%~D PCH_SPI_CS0#_R 1 8
/CS VCC

22P_0402_50V8J~D
PCH_SPI_SO RH3721 2 33_0402_5%~D PCH_SPI_SO_R 2 7 PCH_SPI_DO3_R RH3741 2 33_0402_5%~D PCH_SPI_DO3 1
DO /HOLD

@
PCH_SPI_DO2 RH3751 2 33_0402_5%~D PCH_SPI_DO2_R 3 6 PCH_SPI_CLK_R RH3761 2 33_0402_5%~D PCH_SPI_CLK
/WP CLK

CH8
4 5 PCH_SPI_SI_R RH3771 2 33_0402_5%~D PCH_SPI_SI 2
GND DIO

64M EN25Q64-104HIP_SO8

EON Reserve for EMI please


A
close to UH14 A

Security Classification Compal Secret Data


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) SPI, SMBUS,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 20 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

D D

LPT_PCH_M_EDS
UH1I

AW31 B37 USB20_N0


PERN1/USB3RN3 USB2N0 USB20_N0 <52>
AY31 D37 USB20_P0 JUSB1
PERP1/USB3RP3 USB2P0 USB20_N1 USB20_P0 <52>
A38 USB20_N1 <52>
USB2N1 USB20_P1
BE32
PETN1/USB3TN3 USB2P1
C38 USB20_P1 <52> JUSB2
BC32 A36 USB20_N2
PETP1/USB3TP3 USB2N2 USB20_N2 <53>
C36 USB20_P2 JUSB3
USB2P2 USB20_P2 <53>
AT31 A34 USB20_N3
PERN2/USB3RN4 USB2N3 USB20_P3 USB20_N3 <53>
AR31
PERP2/USB3RP4 USB2P3
C34
USB20_N4
USB20_P3 <53> JUSB4
B33 USB20_N4 <51>
USB2N4 USB20_P4
BD33
PETN2/USB3TN4 USB2P4
D33
USB20_N5
USB20_P4 <51> Mini Card(WLAN)
BB33 F31 USB20_N5 <51>
PETP2/USB3TP4 USB2N5 USB20_P5
USB2P5
G31
USB20_N6 USB20_P5 <51> Mini Card(DMC)
K31 USB20_N6 <47>
PCIE_PRX_GLANTX_N1 USB2N6 USB20_P6
<44> PCIE_PRX_GLANTX_N1 AW33
PERN_3 USB2P6
L31 USB20_P6 <47> ELC LED
PCIE_PRX_GLANTX_P1 AY33 G29 USB20_N7
<44> PCIE_PRX_GLANTX_P1 PERP_3 USB2N7 USB20_N7 <55>
10/100/1G LAN H29 USB20_P7 IR sensor
USB2P7 USB20_P7 <55>
CH149 1 2 0.1U_0402_25V6K~D PCIE_PTX_GLANRX_N1_C BE34 A32
<44> PCIE_PTX_GLANRX_N1 CH150 PCIE_PTX_GLANRX_P1_C PETN_3 USB2N8
1 2 0.1U_0402_25V6K~D BC34
PETP_3 USB2P8
C32
<44> PCIE_PTX_GLANRX_P1
A30
PCIE_PRX_CARDTX_N4 USB2N9
<53> PCIE_PRX_CARDTX_N4 AT33 C30
PCIE_PRX_CARDTX_P4 PERN_4 USB2P9
<53> PCIE_PRX_CARDTX_P4 AR33 B29
PERP_4 USB2N10
CARD READER USB2P10
D29
CH153 1 2 0.1U_0402_25V6K~D PCIE_PTX_CARDRX_N4_C BE36 A28 USB20_N11
<53> PCIE_PTX_CARDRX_N4 PETN_4 USB2N11 USB20_N11 <33>
C CH154 1 2 0.1U_0402_25V6K~D PCIE_PTX_CARDRX_P4_C BC36 C28 USB20_P11 eDP Camera C
<53> PCIE_PTX_CARDRX_P4 PETP_4 USB2P11 USB20_P11 <33>
G26 USB20_N12

PCIe
USB2N12 USB20_N12 <42>
AW36 F26 USB20_P12 LVDS Camera

USB
PERN_5 USB2P12 USB20_P12 <42>
AV36 F24 USB20_N13
PERP_5 USB2N13 USB20_P13 USB20_N13 <53>
USB2P13
G24 USB20_P13 <53> VPK K/B
BD37
PETN_5
BB37
PETP_5 USB3RN1 USBRBIAS
AR26 USB3RN1 <52>
USB3RN1 USB3RP1
AY38 AP26 USB3RP1 <52>
PERN_6 USB3RP1

22.6_0402_1%~D
AW38 BE24 USB3TN1 P1: JUSB1
PERP_6 USB3TN1 USB3TN1 <52>

1
BD23 USB3TP1
USB3TP1 USB3TP1 <52>

RH160
BC38 AW26 USB3RN2
PETN_6 USB3RN2 USB3RN2 <52>
BE38 AV26 USB3RP2
PETP_6 USB3RP2 USB3RP2 <52>
BD25 USB3TN2 P2: JUSB2
USB3TN2 USB3TP2 USB3TN2 <52>
AT40 BC24

2
PERN_7 USB3TP2 USB3TP2 <52>
AT39 AW29 USB3RN5
PERP_7 USB3RN5 USB3RN5 <53>
AV29 USB3RP5
USB3RP5 USB3RP5 <53>
BE40 BE26 USB3TN5 P5: JUSB3
PETN_7 USB3TN5 USB3TN5 <53>
BC40 BC26 USB3TP5
PETP_7 USB3TP5 USB3RN6 USB3TP5 <53>
USB3RN6
AR29 USB3RN6 <53> CAD NOTE:
AN38 AP29 USB3RP6
PERN_8 USB3RP6 USB3TN6
USB3RP6 <53> Route single-end 50-ohms and max 500-mils length.
AN39
PERP_8 USB3TN6
BD27
USB3TP6
USB3TN6 <53> P6: JUSB4 Avoid routing next to clock pins or under stitching capacitors.
BE28 USB3TP6 <53>
USB3TP6
BD42
PETN_8
Recommended minimum spacing to other signal traces is 15 mils.
BD41 K24 USBRBIAS
PETP_8 USBRBIAS#
K26
USBRBIAS
1 2 PCH_PCIE_IREF BE30 M33 PAD~D T135 @
+1.5VS PCIE_IREF TP24
RH51 0_0402_5% L33 PAD~D T137 @
TP23 +3V_PCH
@ T134 PAD~D BC30 P3 USB_OC0# USB_OC0# <52>
TP11 OC0#/GPIO59
V1 USB_OC1# USB_OC1# <52>
RPH1
OC1#/GPIO40
U2 USB_OC2# USB_OC2# <53>
USB_OC0# 4 5
OC2#/GPIO41
@ T136 PAD~D BB29 P1 USB_OC3# USB_OC3# <53>
USB_OC1# 3 6
TP6 OC3#/GPIO42
M3 USB_OC4# USB_OC3# 2 7
OC4#/GPIO43
T1 USB_OC5# USB_OC4# 1 8
PCH_PCIE_RCOMP BD29 OC5#/GPIO9
+1.5VS 1 2 N2 USB_OC6#
PCIE_RCOMP OC6#/GPIO10
RH210 7.5K_0402_1%~D M1 USB_OC7# 10K_1206_8P4R_5%~D
OC7#/GPIO14
RPH2
B B
LYNXPOINT_BGA695 9 OF 11 5 USB_OC5# 4 5
USB_OC6# 3 6
USB_OC7# 2 7
USB_OC2# 1 8

10K_1206_8P4R_5%~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCIE,USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 21 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

D D

+3VS
+3VS
GATEA20 2 1
LPT_PCH_M_EDS
1 2 DMC_RADIO_OFF# UH1F 10K_0402_5%~D RH161
RH270 10K_0402_5%~D KB_RST# 2 1
1 2 DGPU_EDIDSEL# DMC_RADIO_OFF# AT8 10K_0402_5%~D RH203
RH271 10K_0402_5%~D <51> DMC_RADIO_OFF# BMBUSY#/GPIO0
1 2 DGPU_HPD_INT# DGPU_EDIDSEL# F13
RH164 10K_0402_5%~D <32,36,42> DGPU_EDIDSEL# TACH1/GPIO1
2 1 STP_PCI# DGPU_HPD_INT# A14
<36,39> DGPU_HPD_INT# TACH2/GPIO6
RH179 10K_0402_5%~D
CPU/Misc
1 2 VGA_PRSNT_R# EC_SCI# G15
<43> EC_SCI# TACH3/GPIO7
RH267 10K_0402_5%~D
1 2 VGA_PRSNT_L# EC_SMI# Y1
<43> EC_SMI# GPIO8
RH57 20K_0402_5%~D
1 2 PCH_GPIO22 EDP_DETECT# K13
<41> EDP_DETECT# LAN_PHY_PWR_CTRL/GPIO12
RH256 10K_0402_5%~D AN10 GATEA20
LVDS_CAB_DET# PCH_GPIO15 TP14 GATEA20 <43>
1 2 AB11
RH257 10K_0402_5%~D GPIO15
AY1 2 RH184 1 H_PECI <6,43>
PECI

@
1 2 EDP_CAB_DET# PCH_GPIO16 AN2 0_0402_5%~D
RH258 10K_0402_5%~D SATA4GP/GPIO16 KB_RST#
AT6 KB_RST# <43>
GPIO RCIN#
C14
TACH0/GPIO17 H_CPUPWRGD
AV3 H_CPUPWRGD <6>
+3V_PCH PCH_GPIO22 PROCPWRGD
BB4
SCLOCK/GPIO22 PCH_THRMTRIP#_R
AV1 1 2 H_THERMTRIP# <6>
HDD_DET# ODD_EN# THRMTRIP# 390_0402_5% RH262
2 1 <50> ODD_EN# Y10
RH187 10K_0402_5%~D GPIO24 CPU_PLTRST#
AU4 CPU_PLTRST# <6>
PCH_GPIO27 PLTRST_PROC#
R11
GPIO27
N10
PCH_GPIO15 PCH_GPIO28 VSS
1 2 AD11
RH354 1K_0402_1%~D GPIO28
2 1 ODD_EN# STP_PCI# AN6
RH182 10K_0402_5%~D GPIO34
2 1 PCH_GPIO35 PCH_GPIO35 AP1
<36> PCH_GPIO35 GPIO35/NMI#
RH264 10K_0402_5%~D
ODD_DETECT# AT3
<50> ODD_DETECT# SATA2GP/GPIO36
PCH_GPIO37 AK1
PCH_GPIO27 SATA3GP/GPIO37
C 2 1 C
@ RH269 10K_0402_5%~D <29> VGA_PRSNT_R# VGA_PRSNT_R# AT7
SLOAD/GPIO38
<29> VGA_PRSNT_L# VGA_PRSNT_L# AM3 A2
SDATAOUT0/GPIO39 VSS +5VS +5VALW
A41
FFS_INT2 VSS
<49,50> FFS_INT2 AN4 A43
SDATAOUT1/GPIO48 VSS PCH_VSS_A44
A44
PCH_GPIO49 VSS
AK3 B1
SATA5GP/GPIO49 VSS

0_0402_5%~D

0_0402_5%~D
B2
VSS

2
@ RH166

@ RH175
HDD_DET# U12 B44
+3V_PCH <49> HDD_DET# GPIO57 VSS
B45 PCH_VSS_B45
DGPU_BKL_PWM_SEL# C16 VSS
<42> DGPU_BKL_PWM_SEL# BA1
TACH4/GPIO68 VSS
BC1
VSS
2
4.7K_0402_5%~D

EDP_CAB_DET# D13 BD1 PCH_VSS_BD1

1
<33> EDP_CAB_DET# TACH5/GPIO69 VSS
BD2
VSS
RH53

LVDS_CAB_DET# G13 BD44


<42> LVDS_CAB_DET# TACH6/GPIO70 VSS
BD45 PCH_VSS_A44 PCH_VSS_B45 PCH_VSS_BD1
WiGi_RADIO_DIS# VSS
<51> WiGi_RADIO_DIS# H15 BE2
1

TACH7/GPIO71 VSS

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D
BE3
VSS

2
PCH_GPIO28 D1
VSS

RH165

RH168

RH170
BE41 E1
TP_VSS_NCTF VSS NCTF VSS
1 2 BE5 E45
VSS VSS
1 1K_0402_1%~D

RH162 0_0402_5%~D C45 A4


VSS VSS
@ RH353

A5

1
VSS

LYNXPOINT_BGA695 6 OF 11 5
2

PLL ON DIE VR ENABLE


+3VS
ENABLED - HIGH(DEFAULT) PCH_GPIO16
1 2
DISABLED - LOW RH272 @ 10K_0402_5%~D
2 1 PCH_GPIO49
RH266 10K_0402_5%~D

2 1 PCH_GPIO16
B B
RH265 10K_0402_5%~D
2 1 PCH_GPIO49
RH268 @ 10K_0402_5%~D

+3VS
Config GPIO16,49 ODD_DETECT#
1 2
RH176 200K_0402_5%
USB X4,PCIEX8,SATAX6 11 1 2 PCH_GPIO37
@ RH171 200K_0402_5%
2 1 ODD_DETECT#
@ RH174 10K_0402_5%~D
* USB X6,PCIEX8,SATAX4 01
2 1 PCH_GPIO37
RH181 10K_0402_5%~D

SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.


WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO,MISC,NTFC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 22 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

D D

LH1
+VCCADAC 2 1 1 2 +1.5VS
PCH Power Rail Table
BLM18PG181SN1_0603~D
0_0603_5%~D RH211

0.01U_0402_16V7K~D

0.1U_0402_10V7K~D

10U_0603_6.3V6M~D
1 1 1 Voltage Rail Voltage S0 Iccmax Current (A)

CH57

CH80

CH156
2 2 2
VCC 1.05V 1.29 A

VCCIO 1.05V 3.629 A


LPT_PCH_M_EDS
UH1G
C +1.05V_+1.5V_RUN VCCADAC1_5 1.5V 0.070 A C
+1.05VS P45
VCCADAC1_5

10U_0603_6.3V6M~D
AA24
VCC CRT DAC VSS
P43 VCCADAC3_3 3.3V 0.0133 A
10U_0603_6.3V6M~D

AA26 +1.05VS
VCC
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1 AD20 M31 +3VS 1


VCC VCCADACBG3_3

1U_0402_6.3V6K~D

@ CH81
AD22
VCC VCCCLK 1.05V 0.306 A
CH30

CH32

CH33

CH31

AD24 1
VCC
AD26 BB44
2 2 2 2 VCC VCCVRM +3VS 2

CH48
AD28
VCC FDI
VCCCLK3_3 3.3V 0.055 A
AE18 AN34
VCC VCCIO 2
AE20
VCC
AE22
VCC VCCIO
AN35 VCCVRM 1.5V 0.179 A
+3V_PCH

0.1U_0402_10V7K~D
AE24
VCC
AE26 R30 1
VCC HVCMOS VCC3_3_R30
AG18
VCC VCC3_3_R32
R32 VCC3_3 3.3V 0.133 A

0.1U_0402_10V7K~D

CH38
AG20
VCC +PCH_USB_DCPSUS1
AG22 Y12 1
VCC DCPSUS1 2
AG24
VCC VCCASW 1.05V 0.67 A

CH60
Y26 AJ30
VCC VCCSUS3_3
Core

AJ32
VCCSUS3_3 2
VCCSUSHDA 3.3V 0.01 A
+1.05V AJ26 +PCH_USB_DCPSUS3 +1.05V_+1.5V_RUN
+PCH_VCCDSW U14 USB3 DCPSUS3
AJ28
DCPSUSBYP DCPSUS3
AA18
VCCASW VCCIO
AK20 +1.05VS VCCSPI 3.3V 0.022 A
U18 AK26
VCCASW VCCVRM
22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05V_+1.5V_RUN

10U_0603_6.3V6M~D
U20 AK28 1
VCCASW VCCVRM

@ CH82
1 1 1 U22
VCCASW VCCSUS3_3 3.3V 0.261 A
U24 BE22
VCCASW VCCVRM
CH64

CH35

CH36
C_0805NEW

V18 PCIe/DMI
VCCASW +1.05V_+1.5V_RUN 2

10U_0603_6.3V6M~D
2 2 2
V20
VCCASW VCCIO
AK18 +1.05VS 1 VCCDSW3_3 3.3V 0.015 A

@ CH83
V22
VCCASW
V24 AN11
VCCASW VCCVRM

10U_0603_6.3V6M~D
Y18
VCCASW SATA 2
V_PROC_IO 1.05V 0.004 A
Y20 AK22 1
VCCASW VCCIO

@ CH85
Y22 +1.05VS
VCCASW
AM18
VCCIO
AM20
VCCIO 2
AM22
VCCMPHY VCCIO
AP22
B VCCIO B

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
AR22 1 1 1 1 1
VCCIO
AT22
VCCIO

CH86

CH47

CH46

CH45

CH44
LYNXPOINT_BGA695 7 OF 11 5 2 2 2 2 2 +1.05V

+PCH_USB_DCPSUS1 2 1
0_0402_5%~D RH360 @

1U_0402_6.3V6K~D
1

@ CH61
1 2 +PCH_VCCDSW +1.5VS +1.05V_+1.5V_RUN
@ RH37 5.11_0402_1%~D
+PCH_VCCDSW_R

2 1 2
RH197 0_0603_5%~D
+1.05VS
+1.05V
2 1
1U_0402_6.3V6K~D

@ RH198 0_0603_5%~D +PCH_USB_DCPSUS3 1 2


0_0603_5%~D RH209 @

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D
1
@ CH34

1 1

@ CH40

@ CH39
2
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 23 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

D D

+PCH_VCCDSW3_3

LPT_PCH_M_EDS
2 1 +3V_PCH
UH1H 0_0402_5%~D RH213 @

0.1U_0402_10V7K~D
2 1 +3VALW
+3V_PCH +3V_PCH 0_0402_5%~D RH253
1

CH155
R24 R20
VCCSUS3_3 VCCSUS3_3
R26 R22
0.1U_0402_10V7K~D VCCSUS3_3 VCCSUS3_3
R28
+1.05VS VCCSUS3_3 GPIO/LPC 2
1 U26
VCCSUS3_3 +PCH_VCCDSW3_3
A16
VCCDSW3_3
CH66

M24 +3VS
VSS +PCH_VCCSST 1
AA14 2
2 DCPSST
0.1U_0402_10V7K~D
+3VS U35 CH84 0.1U_0402_10V7K~D
VCCUSBPLL
1 AE14

USB
VCC3_3
L24 AF12
VCC3_3 VCC3_3
CH62

0.1U_0402_10V7K~D
AG14
VCC3_3 +3V_PCH

0.1U_0402_10V7K~D
U30 1
2 +1.05VS VCCIO
1 V28
VCCIO

CH63

CH65
V30 U36 +1.05VS
VCCIO VCCIO
Y30
VCCIO +3V_PCH 2
2

0.1U_0402_10V7K~D
+1.05V_+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2

1U_0402_6.3V6K~D
1 A26 1
VCCSUSHDA
AF34
VCCVRM

CH37

CH90
10U_0603_6.3V6M~D
+RTC_CELL

1U_0402_6.3V6K~D
1 +PCH_VCC AP45 K8 1
2 VCC VCCSUS3_3 2

CH42

CH59
+PCH_VCCCLK Y32 A6
+1.05V VCCCLK VCCRTC
2 RTC 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D
M29 P14 +PCH_DCPRTC CH70
+PCH_VCCCLK3_3 VCCCLK3_3 DCPRTC
1 2 +PCH_USB_DCPSUS2 P16 1 2 1 1 1
@ RH361 0_0402_5%~D DCPRTC
L29
VCCCLK3_3
1U_0402_6.3V6K~D

CH69

CH68

CH67
0.1U_0402_10V7K~D
1 L26 AJ12 +PCH_VPROC
VCCCLK3_3 V_PROC_IO 2 2 2
@ CH87

C M26 CPU AJ14 +3V_PCH C


VCCCLK3_3 V_PROC_IO
U32
2 VCCCLK3_3

1U_0402_6.3V6K~D
ICC
V32 AD12
VCCCLK3_3 SPI VCCSPI

+PCH_VCCCLK AD34 1
VCCCLK
P18 +PCH_VCCCFUSE
VCC

CH74
AA30 P20
VCCCLK VCC
AA32
VCCCLK 2
L17 +1.05V
Fuse VCCASW
AD35
VCCCLK
R18
VCCASW +1.05VS
AG30
VCCCLK
AG32
VCCCLK +PCH_VPROC
AW40 +1.5VS 2 1
VCCVRM 0_0805_5%~D RH219
AD36
VCCCLK +3VS

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D
AK30
VCC3_3
AE30 Thermal 1 1 1
VCCCLK
AE32 AK32
+1.05VS +1.05VS_VCC VCCCLK VCC3_3

0.1U_0402_10V7K~D

CH73

CH72

CH71
1 2 2 2
LH100

CH76
1 2 1 2 +PCH_VCC LYNXPOINT_BGA695 8 OF 11 5
4.7UH_LQM18FN4R7M00D_20%~D RH207 0_0603_5%~D
2
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1 1
CH55

CH51

2 2

Place near pin AP45 +PCH_VCCCFUSE 2 1 +3VS


0_0805_5%~D RH220

1U_0402_6.3V6K~D
2 1 +1.05VS
1 0_0805_5%~D RH221 @

CH75
B 2 B

+1.05VS +PCH_VCCCLK

1 2
RH214 0_0805_5%~D
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
@ CH43

1 1 1 1 1 1
CH49

CH50

CH77

CH78

CH79
2 2 2 2 2 2

Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32

+3VS +PCH_VCCCLK3_3

1 2
RH212 0_0805_5%~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1
CH52

CH54

CH53

CH58

2 2 2 2

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/9) Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 24 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

D D

UH1J LPT_PCH_M_EDS UH1K LPT_PCH_M_EDS

AL34 VSS VSS K39 AA16 VSS VSS B19


AL38 VSS VSS L2 AA20 VSS VSS B23
AL8 VSS VSS L44 AA22 VSS VSS B27
AM14 VSS VSS M17 AA28 VSS VSS B31
AM24 VSS VSS M22 AA4 VSS VSS B35
AM26 VSS VSS N12 AB12 VSS VSS B39
AM28 VSS VSS N35 AB34 VSS VSS B7
AM30 VSS VSS N39 AB38 VSS VSS BA40
AM32 VSS VSS N6 AB8 VSS VSS BD11
AM16 VSS VSS P22 AC2 VSS VSS BD15
AN36 VSS VSS P24 AC44 VSS VSS BD19
AN40 VSS VSS P26 AD14 VSS VSS AY36
AN42 VSS VSS P28 AD16 VSS VSS AT43
AN8 VSS VSS P30 AD18 VSS VSS BD31
AP13 VSS VSS P32 AD30 VSS VSS BD35
C C
AP24 VSS VSS R12 AD32 VSS VSS BD39
AP31 VSS VSS R14 AD40 VSS VSS BD7
AP43 VSS VSS R16 AD6 VSS VSS D25
AR2 VSS VSS R2 AD8 VSS VSS AV7
AK16 VSS VSS R34 AE16 VSS VSS F15
AT10 VSS VSS R38 AE28 VSS VSS F20
AT15 VSS VSS R44 AF38 VSS VSS F29
AT17 R8 AF8 F33
VSS VSS VSS VSS
AT20 T43 AG16 BC16
VSS VSS VSS VSS
AT26 U10 AG2 D4
VSS VSS VSS VSS
AT29 U16 AG26 G2
VSS VSS VSS VSS
AT36 U28 AG28 G38
VSS VSS VSS VSS
AT38 U34 AG44 G44
VSS VSS VSS VSS
D42 U38 AJ16 G8
VSS VSS VSS VSS
AV13 U42 AJ18 H10
VSS VSS VSS VSS
AV22 U6 AJ20 H13
VSS VSS VSS VSS
AV24 V14 AJ22 H17
VSS VSS VSS VSS
AV31 V16 AJ24 H22
VSS VSS VSS VSS
AV33 V26 AJ34 H24
VSS VSS VSS VSS
BB25 V43 AJ38 H26
VSS VSS VSS VSS
AV40 W2 AJ6 H31
VSS VSS VSS VSS
AV6 W44 AJ8 H36
VSS VSS VSS VSS
AW2 Y14 AK14 H40
VSS VSS VSS VSS
F43 Y16 AK24 H7
VSS VSS VSS VSS
AY10 Y24 AK43 K10
VSS VSS VSS VSS
AY15 Y28 AK45 K15
VSS VSS VSS VSS
AY20 Y34 AL12 K20
VSS VSS VSS VSS
AY26 Y36 AL2 K29
VSS VSS VSS VSS
AY29 Y40 BC22 K33
VSS VSS VSS VSS
AY7 Y8 BB42 BC28
VSS VSS VSS VSS
B11
VSS
B15
B VSS B
LYNXPOINT_BGA695 11 OF 11 5

LYNXPOINT_BGA695 10 OF 11 5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 25 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

+3V_MXM +3V_MXM +3V_MXM +3V_MXM


PEG_HTX_C_GRX_N[0..15] +3V_MXM +3VALW
<5> PEG_HTX_C_GRX_N[0..15]
VGA_LCD_CLK RV63 1 2 4.3K_0402_5% MXM_CURI2C_CLK @ RV64 1 2 3.3K_0402_5%
D D
PEG_HTX_C_GRX_P[0..15] VGA_LCD_DAT RV65 1 2 4.3K_0402_5% MXM_CURI2C_DATA @ RV66 1 2 3.3K_0402_5%

10K_0402_5%~D
<5> PEG_HTX_C_GRX_P[0..15]

10K_0402_5%~D

4.7K_0402_5%~D

4.7K_0402_5%~D
DGPU_PWROK RV67 2 1 10K_0402_5%~D

1
<5> PEG_GTX_HRX_N[0..15] PEG_GTX_HRX_N[0..15] VGA_HDMI_CEC RV68 1 2 10K_0402_5%~D

RV71
VGA_DISABLE# RV69 @ 10K_0402_5%~D AC_BATT# RV70 1 10K_0402_5%~D

RV72
1 2 2

RV73

RV74
PEG_GTX_HRX_P[0..15] VGA_WAKE# RV75 1 @ 2 10K_0402_5%~D 2
<5> PEG_GTX_HRX_P[0..15]

G
2
B+_MXM B+_MXM

G
2

2
JMXM1A
400mil(10A) +3VALW VGA_SMB_DA1

S
1 2 <43> EC_SMB_DA1 1 3
PWR_SRC PWR_SRC

D
3 4 VGA_TH_OVERT# 3 1 TH_OVERT# <43> 2
PWR_SRC PWR_SRC

10U_1206_25V6M~D

680P_0603_50V7K~D

68P_0402_50V8J~D

0.1U_0603_25V7K~D

G
5 6 1 QV6
PWR_SRC PWR_SRC
7 8 1 1 1 2 QV7 SSM3K7002F_SC59-3~D
PWR_SRC PWR_SRC

CV2
CV5
PWR_SRCE1 E2
9 10 SSM3K7002F_SC59-3~D
PWR_SRC

CV1

CV3
VGA_SMB_CK1

S
11 12 0.1U_0402_25V6K~D <43> EC_SMB_CK1 1 3
PWR_SRC PWR_SRC

CV4
13 14 2
+5VMXM +5V_MXM PWR_SRC PWR_SRC 2 2 2 1
15 16 QV8
J12 @ PWR_SRC PWR_SRC JMXM1B SSM3K7002F_SC59-3~D
17 18
PWR_SRC PWR_SRC

5
2 1 UV4 163 162
GND GND
0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D
1 PEG_GTX_HRX_N2 165 164 PEG_HTX_C_GRX_N2

G VCC
<17,43,47,57,63> ACIN B PEX_RX2# PEX_TX2#
PAD-OPEN 4x4m 1 1 19 20 4 AC_BATT# PEG_GTX_HRX_P2 167 166 PEG_HTX_C_GRX_P2
GND GND Y PEX_RX2 PEX_TX2
CV7

21 22 <43> EC_AC_BAT# 2 169 168


GND GND A GND GND
CV6

23 24 PEG_GTX_HRX_N1 171 170 PEG_HTX_C_GRX_N1


GND GND MC74VHC1G09DFT2G_SC70-5 PEG_GTX_HRX_P1 PEX_RX1# PEX_TX1# PEG_HTX_C_GRX_P1
25 26 173 172

3
2 2 GND GND PEX_RX1 PEX_TX1
27 28 175 174
GND GND PEG_GTX_HRX_N0 GND GND PEG_HTX_C_GRX_N0
29
GND E3 E4 GND
30 177
PEX_RX0# PEX_TX0#
176
31 32 1 @ 2 PEG_GTX_HRX_P0 179 178 PEG_HTX_C_GRX_P0
+5V_MXM GND GND RV94 0_0402_5%~D PEX_RX0 PEX_TX0
33 34 181 180
GND GND RV76 1 CLK_PEG_PCH#_R GND GND PEG_CLKREQ#
35 36 <18> CLK_PEG_PCH# 2 0_0402_5%~D 183 182 PEG_CLKREQ# <18>
GND GND VGA_PRSNT_R# RV77 1 CLK_PEG_PCH_R PEX_REFCLK# PEX_CLK_REQ# PLTRST_VGA#
37 38 VGA_PRSNT_R# <21> <18> CLK_PEG_PCH 2 0_0402_5%~D 185 184 PLTRST_VGA# <17>
5V PRSNT_R# VGA_WAKE# PEX_REFCLK PEX_RST#
39 40 187 186
5V WAKE# DGPU_PWROK GND VGA_DDC_DAT
41 42 DGPU_PWROK <30,43> 189 188
5V PWR_GOOD DGPU_PWR_EN RSVD VGA_DDC_CLK
43 44 DGPU_PWR_EN <43,56> 191 190
5V PWR_EN RSVD VGA_VSYNC
45 46 193 192
5V RSVD RSVD VGA_HSYNC
100mil(2.5A, 5VIA) 47
49
GND RSVD
48
50
195
197
RSVD GND
194
196
CRT
GND RSVD +3V_MXM RSVD VGA_RED
Add R7 increase NV MXM PEG Swing 51 52 +3VMXM LVDS_MXM_TZCLK- 199 198
GND RSVD AC_BATT# <41> LVDS_MXM_TZCLK- LVDS_MXM_TZCLK+ LVDS_UCLK# VGA_GREEN
53 54 201 200
GND PWR_LEVEL <41> LVDS_MXM_TZCLK+ LVDS_UCLK VGA_BLUE

4.7U_0805_10V4Z~D
RV781 2 0_0402_5%~D 55 56 VGA_TH_OVERT# J13 @ 203 202
VGA_DISABLE# PEX_STD_SW# TH_OVERT# GND GND LVDS_MXM_TXCLK-
57 58 1 2 2 1 205 204
VGA_DISABLE# TH_ALERT# LVDS_UTX3# LVDS_LCLK# LVDS_MXM_TXCLK- <41>
C <42> DGPU_ENVDD 59
61
PNL_PWR_EN TH_PWM
60
62
RV79 10K_0402_5%~D 1 LVDS TZ 207
209
LVDS_UTX3 LVDS_LCLK
206
208
LVDS_MXM_TXCLK+
LVDS_MXM_TXCLK+ <41>
C
<42> DGPU_BKL_EN PNL_BL_EN GPIO0 PAD-OPEN 4x4m GND GND

CV8
<42> VGA_PNL_PWM 63 64 LVDS_MXM_TZOUT2- 211 210 LVDS TX
VGA_HDMI_CEC PNL_BL_PWM GPIO1 <41> LVDS_MXM_TZOUT2- LVDS_MXM_TZOUT2+ LVDS_UTX2# LVDS_LTX3#
65 66 213 212
HDMI_CEC GPIO2 VGA_SMB_DA1 2 <41> LVDS_MXM_TZOUT2+ LVDS_UTX2 LVDS_LTX3
67 68 215 214
VGA_LCD_DAT DVI_HPD SMB_DAT VGA_SMB_CK1 LVDS_MXM_TZOUT1- GND GND LVDS_MXM_TXOUT2-
69 70 217 216
<42> VGA_LCD_DAT VGA_LCD_CLK LVDS_DDC_DAT SMB_CLK SYSTEM <41> LVDS_MXM_TZOUT1- LVDS_MXM_TZOUT1+ LVDS_UTX1# LVDS_LTX2# LVDS_MXM_TXOUT2+ LVDS_MXM_TXOUT2- <41>
71 72 219 218 LVDS_MXM_TXOUT2+ <41>
<42> VGA_LCD_CLK LVDS_DDC_CLK GND <41> LVDS_MXM_TZOUT1+ LVDS_UTX1 LVDS_LTX2
LVDS DDC Module have 4.7K Pull-UP 73 74 221 220
GND OEM VGA_PS_0 0_0402_5%~D LVDS_MXM_TZOUT0- GND GND LVDS_MXM_TXOUT1-
75 76 223 222
@ RV80 1 OEM OEM VGA_PS_1 <41> LVDS_MXM_TZOUT0- LVDS_MXM_TZOUT0+ LVDS_UTX0# LVDS_LTX1# LVDS_MXM_TXOUT1+ LVDS_MXM_TXOUT1- <41>
+3V_MXM 210K_0402_5%~D 77 78 RV92 1 2 FB_CLAMP_TGL_REQ# <43> 225 224
@ RV81 1 OEM OEM VGA_PS_2 <41> LVDS_MXM_TZOUT0+ LVDS_UTX0 LVDS_LTX1 LVDS_MXM_TXOUT1+ <41>
236K_0402_1% 79 80 227 226
RV93 1 0_0402_5%~D OEM OEM GPU_HDMI_TXD2- GND GND LVDS_MXM_TXOUT0-
SPDIF_OUT <43> FB_CLAMP
2 81
OEM GND
82 <36> GPU_HDMI_TXD2- 229
DP_C_L0# LVDS_LTX0#
228
LVDS_MXM_TXOUT0- <41>
83 84 PEG_HTX_C_GRX_N15 <36> GPU_HDMI_TXD2+ GPU_HDMI_TXD2+ 231 230 LVDS_MXM_TXOUT0+
PEG_GTX_HRX_N15 GND PEX_TX15# PEG_HTX_C_GRX_P15 DP_C_L0 LVDS_LTX0 LVDS_MXM_TXOUT0+ <41>
85 86 233 232
+3V_MXM PEG_GTX_HRX_P15 PEX_RX15# PEX_TX15 GPU_HDMI_TXD1- GND GND MXM_TX0N
87 88 <36> GPU_HDMI_TXD1- 235 234 MXM_TX0N <32>
PEX_RX15 GND PEG_HTX_C_GRX_N14 GPU_HDMI_TXD1+ DP_C_L1# DP_D_L0# MXM_TX0P
89 90 <36> GPU_HDMI_TXD1+ 237 236 MXM_TX0P <32>
PEG_GTX_HRX_N14 GND PEX_TX14# PEG_HTX_C_GRX_P14 DP_C_L1 DP_D_L0
91 92 239 238
PEX_RX14# PEX_TX14 GND GND
2

PEG_GTX_HRX_P14 +3V_MXM GPU_HDMI_TXD0- MXM_TX1N


93
PEX_RX14 GND
94
PEG_HTX_C_GRX_N13
HDMI <36> GPU_HDMI_TXD0-
GPU_HDMI_TXD0+
241
DP_C_L2# DP_D_L1#
240
MXM_TX1P
MXM_TX1N <32>
RV82
10K_0402_5%~D PEG_GTX_HRX_N13
95
97
GND PEX_TX13#
96
98 PEG_HTX_C_GRX_P13
<36> GPU_HDMI_TXD0+ 243
245
DP_C_L2 DP_D_L1
242
244
MXM_TX1P <32> eDP
PEG_GTX_HRX_P13 PEX_RX13# PEX_TX13 GPU_HDMI_TXC- GND GND MXM_TX2N
99 100 <36> GPU_HDMI_TXC- 247 246 MXM_TX2N <32>
PEX_RX13 GND DP_C_L3# DP_D_L2#

0_0402_5%~D
101 102 PEG_HTX_C_GRX_N12 <36> GPU_HDMI_TXC+ GPU_HDMI_TXC+ 249 248 MXM_TX2P MXM_TX2P <32>
1

GND PEX_TX12# DP_C_L3 DP_D_L2

2
PEG_GTX_HRX_N12 103 104 PEG_HTX_C_GRX_P12 251 250
PEX_RX12# PEX_TX12 GND GND

RV83
B+_MXM_A0 PEG_GTX_HRX_P12 105 106 <36> GPU_HDMI_SDATA GPU_HDMI_SDATA 253 252 MXM_TX3N MXM_TX3N <32>
PEX_RX12 GND PEG_HTX_C_GRX_N11 @ GPU_HDMI_SCLK DP_C_AUX# DP_D_L3# MXM_TX3P
107 108 <36> GPU_HDMI_SCLK 255 254 MXM_TX3P <32>
PEG_GTX_HRX_N11 GND PEX_TX11# PEG_HTX_C_GRX_P11 DP_C_AUX DP_D_L3
109 110 257 256
PEX_RX11# PEX_TX11 RSVD GND
2

PEG_GTX_HRX_P11 111 112 259 258 MXM_DPB_AUXN/DDC MXM_DPB_AUXN/DDC <32>

1
RV84 @ PEX_RX11 GND PEG_HTX_C_GRX_N10 VGA_PS_0 RSVD DP_D_AUX# MXM_DPB_AUXP/DDC
113 114 261 260 MXM_DPB_AUXP/DDC <32>
10K_0402_5%~D PEG_GTX_HRX_N10 GND PEX_TX10# PEG_HTX_C_GRX_P10 RSVD DP_D_AUX VGA_HDMI_DET
115 116 263 262 VGA_HDMI_DET <36>
PEG_GTX_HRX_P10 PEX_RX10# PEX_TX10 RSVD DP_C_HPD MXM_DPB_HPD
117 118 265 264 MXM_DPB_HPD <32>
PEX_RX10 GND RSVD DP_D_HPD
0_0402_5%~D

119 120 PEG_HTX_C_GRX_N9 267 266


1

GND PEX_TX9# RSVD RSVD


2

PEG_GTX_HRX_N9 121 122 PEG_HTX_C_GRX_P9 269 268


PEX_RX9# PEX_TX9 RSVD RSVD
RV85

PEG_GTX_HRX_P9 123 124 271 270


PEX_RX9 GND PEG_HTX_C_GRX_N8 @ RSVD RSVD
125 126 273 272
+3V_MXM PEG_GTX_HRX_N8 GND PEX_TX8# PEG_HTX_C_GRX_P8 RSVD GND VGA_DPC_N0
127 128 275 274 VGA_DPC_N0 <30>
PEG_GTX_HRX_P8 PEX_RX8# PEX_TX8 RSVD DP_B_L0# VGA_DPC_P0
129 130 277 276 VGA_DPC_P0 <30>
1

PEX_RX8 GND PEG_HTX_C_GRX_N7 RSVD DP_B_L0


131 132 279 278
GND PEX_TX7# RSVD GND
2

PEG_GTX_HRX_N7 133 134 PEG_HTX_C_GRX_P7 281 280 VGA_DPC_N1


PEX_RX7# PEX_TX7 GND DP_B_L1# VGA_DPC_N1 <30>
@ RV86 PEG_GTX_HRX_P7 135 136 <39> VGA_DPD_N0 VGA_DPD_N0 283 282 VGA_DPC_P1 VGA_DPC_P1 <30>
10K_0402_5%~D PEX_RX7 GND PEG_HTX_C_GRX_N6 VGA_DPD_P0 DP_A_L0# DP_B_L1
137 138 <39> VGA_DPD_P0 285 284
B
PEG_GTX_HRX_N6 GND PEX_TX6# PEG_HTX_C_GRX_P6 DP_A_L0 GND VGA_DPC_N2
B

PEG_GTX_HRX_P6
139
141
PEX_RX6# PEX_TX6
140
142 VGA_DPD_N1
287
289
GND DP_B_L2#
286
288 VGA_DPC_P2
VGA_DPC_N2 <30> mDP
<39> VGA_DPD_N1 VGA_DPC_P2 <30>
1

PEX_RX6 GND PEG_HTX_C_GRX_N5 VGA_DPD_P1 DP_A_L1# DP_B_L2


143 144 <39> VGA_DPD_P1 291 290
B+_MXM_A1 PEG_GTX_HRX_N5 GND PEX_TX5# PEG_HTX_C_GRX_P5 DP_A_L1 GND
PEG_GTX_HRX_P5
145
147
PEX_RX5# PEX_TX5
146
148
DMC VGA_DPD_N2
293
295
GND DP_B_L3#
292
294
VGA_DPC_N3
VGA_DPC_P3
VGA_DPC_N3 <30>
PEX_RX5 GND <39> VGA_DPD_N2 DP_A_L2# DP_B_L3 VGA_DPC_P3 <30>
149 150 PEG_HTX_C_GRX_N4 <39> VGA_DPD_P2 VGA_DPD_P2 297 296
GND PEX_TX4# DP_A_L2 GND
2

PEG_GTX_HRX_N4 151 152 PEG_HTX_C_GRX_P4 299 298 VGA_DPC_AUXN/DDC VGA_DPC_AUXN/DDC <30>


RV87 PEG_GTX_HRX_P4 PEX_RX4# PEX_TX4 VGA_DPD_N3 GND DP_B_AUX# VGA_DPC_AUXP/DDC
153 154 301 300
10K_0402_5%~D 155
PEX_RX4 GND
156 PEG_HTX_C_GRX_N3 Place CV9, CV10, CV11 <39> VGA_DPD_N3
<39> VGA_DPD_P3 VGA_DPD_P3 303
DP_A_L3# DP_B_AUX
302 VGA_DPC_HPD
VGA_DPC_AUXP/DDC <30>
PEG_GTX_HRX_N3 GND PEX_TX3# PEG_HTX_C_GRX_P3 DP_A_L3 DP_B_HPD VGA_DMC_HPD VGA_DPC_HPD <30>
PEG_GTX_HRX_P3
157
PEX_RX3# PEX_TX3
158 close MXM connector 305
GND DP_A_HPD
304 VGA_DMC_HPD <39>
159 160 <39> VGA_DPD_AUXN/DDC 307 306 +3V_MXM
1

PEX_RX3 GND DP_A_AUX# 3V3


161 <39> VGA_DPD_AUXP/DDC 309 308
GND VGA_PS_0 @ CV9 2 DP_A_AUX 3V3
1 0.01U_0402_16V7K~D <21> VGA_PRSNT_L# 310 40mil(1A)
VGA_PS_1 @ CV10 2 PRSNT_L#
1 0.01U_0402_16V7K~D
JAE_MM70-314-310B1-1-R300 VGA_PS_2 @ CV11 2 1 0.01U_0402_16V7K~D 311 312
CONN@ (Pull-UP 10K at PCH) GND GND
<63> VIN+ 1 2
JAE_MM70-314-310B1-1-R300
RV88 0_0402_5%~D For B+_MXM CONN@
1 slave address : 1000010
@ CV12
UV5
please placemnet near R-sense
.1U_0402_16V7K~D
2 1 8 B+_MXM_A1
VIN+ A1 B+_MXM_A0
<63> VIN- 1 2 2 7
VIN- A0 MXM_CURI2C_DATA
RV89 0_0402_5%~D 3 6 0_0402_5%~D 2 1 RV90 VGA_SMB_DA1
GND SDA MXM_CURI2C_CLK
+3V_MXM 4 5 0_0402_5%~D 2 1 RV91 VGA_SMB_CK1
VS SCL
HPA00900AIDCNR_SOT23-8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXMIII Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 26 of 61
5 4 3 2 1
5 4 3 2 1

DP Redriver
www.laptopblue.vn +3VS

12
25
32
36
1
6
UV6

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VGA_DPC_P0 CV13 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P0_R 38 23 CPU_MXM_MDP_P0_C CV14 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P0
<29> VGA_DPC_P0 IN0p OUT0p
VGA_DPC_N0 CV15 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N0_R 39 22 CPU_MXM_MDP_N0_C CV16 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N0
D <29> VGA_DPC_N0 IN0n OUT0n D
VGA_DPC_P1 CV17 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P1_R 41 20 CPU_MXM_MDP_P1_C CV18 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P1
<29> VGA_DPC_P1 IN1p OUT1p
VGA_DPC_N1 CV19 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N1_R 42 19 CPU_MXM_MDP_N1_C CV20 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N1
<29> VGA_DPC_N1 IN1n OUT1n
VGA_DPC_P2 CV21 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P2_R 44 17 CPU_MXM_MDP_P2_C CV22 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P2
<29> VGA_DPC_P2 VGA_DPC_N2 CPU_MXM_MDP_N2_R IN2p OUT2p CPU_MXM_MDP_N2_C CPU_MXM_MDP_N2
CV23 2 1 0.1U_0402_10V6K~D 45 16 CV24 2 1 0.1U_0402_10V6K~D
<29> VGA_DPC_N2 IN2n OUT2n
VGA_DPC_P3 CV25 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P3_R 47 14 CPU_MXM_MDP_P3_C CV26 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P3
<29> VGA_DPC_P3 IN3p OUT3p
VGA_DPC_N3 CV27 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N3_R 48 13 CPU_MXM_MDP_N3_C CV28 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N3
<29> VGA_DPC_N3 IN3n OUT3n
+3VS
3 40 DP_CFG1_INPUT
I2C_ADDR CFG1
DP_PEQ 4 46
4.7K_0402_5%~D DP_PEQ DP_CFG0 SCL_CTL/PEQ NC
2 1 RV98 @ 5
4.7K_0402_5%~D DP_CFG1_INPUT SDA_CTL/CFG0 DP_RST# CV29
2 1 RV99 @ RST#
35 2 1 2.2U_0402_6.3V6M~D
4.7K_0402_5%~D 2 1 RV100 @ DP_CFG0
4.7K_0402_5%~D 2 1 RV101 DP_POWER_DOWN# DP_POWER_DOWN# 26 10 CAB_DET_SINK
10K_0402_1%~D DP_RST# PD# CAD_SNK
2 1 RV102
4.99K_0402_1% 1 2 RV103 7 11 DISP_HPD_SINK
REXT HPD_SINK
4.7K_0402_5%~D 2 1 RV104 @ DP_PEQ MDP_CAB_DET 8
4.7K_0402_5%~D DP_CFG1_INPUT CAD_SRC
2 1 RV105 @
4.7K_0402_5%~D 2 1 RV106 @ DP_CFG0 <16> DP_PCH_HPD DP_PCH_HPD 9 28 CPU_MXM_MDP_AUXP
4.7K_0402_5%~D DP_POWER_DOWN# HPD_SRC AUX_SNKP CPU_MXM_MDP_AUXN
2 1 RV108 @ 27
AUX_SNKN
VGA_DPC_AUXP/DDC 33
VGA_DPC_AUXN/DDC 34 SCL_DDC
SDA_DDC 2.2U_0402_6.3V6M~D 1
CEXT
2 2 CV30
0.1U_0402_10V6K~D 15
VGA_DPC_AUXP/DDC CV31 2 NC2
<29> VGA_DPC_AUXP/DDC 1CPU_MXM_MDP_AUXP_L_C 30 21
VGA_DPC_AUXN/DDC CV32 2 AUX_SRCP NC3
<29> VGA_DPC_AUXN/DDC 1 CPU_MXM_MDP_AUXN_L_C 29 37
AUX_SRCN NC4
43
0.1U_0402_10V6K~D NC5

GND1
GND2
GND3
EPAD
+3VS_DP

18
24
31
49
2 1 VGA_DPC_HPD PS8330BQFN48GTR2-A0_QFN48_7X7
RV398 100K_0402_5%~D
CPU_MXM_MDP_AUXN RV112 2 1 100K_0402_5%~D
C CPU_MXM_MDP_AUXP RV113 1 2 100K_0402_5%~D C

+3VS_DP
+3VS Co-lay Need apply CIS part
CV487 FV4

22U_0805_6.3V6M~D

0.1U_0402_25V6K~D
0.1U_0402_16V4Z~D +3VS 1 2
UV37 1 2 1 1 1 1

10U_0603_6.3V6M~D

CV35

.1U_0402_16V7K~D
CV36

CV37

CV38
SN74AHC1G08DCKR_SC70-5 1.5A_6V_1206L150PR~D

5
1 @ RV114 2 1 0_1206_5%~D

P
VGA_DPC_HPD IN1 DGPU_PWROK <29,43> 2 2 2 2
<29> VGA_DPC_HPD 4
O DP_PCH_HPD
2
IN2

G
+5VS +3VS

0.1U_0402_16V4Z~D
Mini DP CONN

4.7K_0402_5%~D

4.7K_0402_5%~D
2 1 0_0402_5%~D

2
RV655 @ +3VS
1

100K_0402_5%~D

CV41

RV115

RV116
1
2

RV117
UV8

1
VGA_DPC_AUXN/DDC 2 8
VGA_DPC_AUXP/DDC 1A VCC
5 3
2A 1B JMDP1
1 6

2
MDP_CAB_DET# 1OE# 2B
7 4 1
2OE# GND 0_0402_5% DISP_HPD_SINK GND
2
CBTD3306PW_TSSOP8 CPU_MXM_MDP_P0 HPD
3
LANE0_P

1
D CAB_DET_SINK
1 2 4
MDP_CAB_DET QV9 <17> DP_CBL_DET CPU_MXM_MDP_N0 CONFIG1
2 5
B
G BSS138_SOT23~D RV118 DISP_CEC LANE0_N B
6
CONFIG2
S 7

3
GND
8
CPU_MXM_MDP_P1 GND
9
CPU_MXM_MDP_P3 LANE1_P
10
CPU_MXM_MDP_N1 LANE3_P
11
CPU_MXM_MDP_N3 LANE1_N
12
LANE3_N
13
GND
14
CPU_MXM_MDP_P2 GND
15
CPU_MXM_MDP_AUXP LANE2_P
16
CPU_MXM_MDP_N2 AUX_CH_P
17 21
CPU_MXM_MDP_AUXN LANE2_N GND1
18 22
AUX_CH_N GND2
19 23
GND GND3
+3VS_DP 20 24
DP_PWR GND4
PS_613002-020121
CONN@

@ RV121
1 2 DISP_HPD_SINK
1M_0402_5%~D

RV124
1 2 CAB_DET_SINK
1M_0402_5%~D

RV125
VGA_DPC_AUXP/DDC 1 2 DISP_CEC
5.1M_0402_5%
1

RV126
VGA_DPC_AUXN/DDC 100K_0402_5%~D
6 2
1

A A
RV127
100K_0402_5%~D QV5A
DMN66D0LDW-7_SOT363-6~D
2
2

DP_MXM_CARD_SEL <32,43>
1
3

DMN66D0LDW-7_SOT363-6~D
5 MXM_MFG_SEL GPU Source
QV5B Security Classification Compal Secret Data Compal Electronics, Inc.
0 NVDIA Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title
4

1 ATI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini DP/Thunder Bolt power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 27 of 61
5 4 3 2 1
A B C D E

www.laptopblue.vn
CPU to EDP & LVDS MUX
+3VS

1 1

CV312

0.01U_0402_16V7K

CV313

0.01U_0402_16V7K

CV314

0.1U_0402_16V4Z

CV315

0.1U_0402_16V4Z

CV316

0.1U_0402_16V4Z
1 1 1 1 1

2 2 2 2 2 UV7

5
VDD33 CPU_EDP_P0_S CPU_EDP_P0_C
21 50 1 2
VDD33 OUT1_D0p CPU_EDP_N0_S CV323 1 CPU_EDP_N0_C CPU_EDP_P0_C <40>
30 VDD33 OUT1_D0n 49 2 0.1U_0402_16V7K
CV324 0.1U_0402_16V7K CPU_EDP_N0_C <40>
51 VDD33
57 47 CPU_EDP_P1_S 1 2 CPU_EDP_P1_C
VDD33 OUT1_D1p CPU_EDP_N1_S CV325 1 CPU_EDP_N1_C CPU_EDP_P1_C <40>
2 0.1U_0402_16V7K
OUT1_D1n 46
CV326 0.1U_0402_16V7K CPU_EDP_N1_C <40> LVDS Panel
CPU_EDP_P0 1 2 CPU_EDP_C_P0 6 45
<8> CPU_EDP_P0 CPU_EDP_N0 CV340 1 CPU_EDP_C_N0 IN_D0p OUT1_D2p
<8> CPU_EDP_N0 2 0.1U_0402_16V7K 7 IN_D0n OUT1_D2n 44
CV339 0.1U_0402_16V7K
CPU_EDP_P1 1 2 CPU_EDP_C_P1 9 42
<8> CPU_EDP_P1 CPU_EDP_N1 CV342 1 CPU_EDP_C_N1 IN_D1p OUT1_D3p
<8> CPU_EDP_N1 2 0.1U_0402_16V7K 10 41
CV341 0.1U_0402_16V7K IN_D1n OUT1_D3n
CPU_EDP_P2 CPU_EDP_C_P2
CPU <8> CPU_EDP_P2 1
CPU_EDP_N2 CV344 1
2
2 0.1U_0402_16V7K CPU_EDP_C_N2
12
13
IN_D2p
40 8338_EDP_P0_S 1 2 8338_EDP_P0
<8> CPU_EDP_N2 IN_D2n OUT2_D0p 8338_EDP_N0_S 8338_EDP_N0 8338_EDP_P0 <32>
CV343 0.1U_0402_16V7K 39 CV331 1 2 0.1U_0402_16V7K
CPU_EDP_P3 CPU_EDP_C_P3 OUT2_D0n CV332 0.1U_0402_16V7K 8338_EDP_N0 <32>
<8> CPU_EDP_P3 1 2 15 IN_D3p
CPU_EDP_N3 CV346 1 2 0.1U_0402_16V7K CPU_EDP_C_N3 16 37 8338_EDP_P1_S 1 2 8338_EDP_P1
<8> CPU_EDP_N3 IN_D3n OUT2_D1p 8338_EDP_N1_S 8338_EDP_N1 8338_EDP_P1 <32>
CV345 0.1U_0402_16V7K 36 CV333 1 2 0.1U_0402_16V7K
OUT2_D1n CV334 0.1U_0402_16V7K 8338_EDP_N1 <32>
8338_EDP_P2_S 8338_EDP_P2
HPD_GPU 4
OUT2_D2p 35
34 8338_EDP_N2_S
1
CV335 1
2
2 0.1U_0402_16V7K 8338_EDP_N2 8338_EDP_P2 <32> eDP Panel
CPU_EDP_HPD# IN_CA_DET OUT2_D2n CV336 0.1U_0402_16V7K 8338_EDP_N2 <32>
3 IN_HPD
2 <8> CPU_EDP_HPD# CTL_EN 8338_EDP_P3_S 8338_EDP_P3 2
2 I2C_CTL_EN OUT2_D3p 32 1 2
PL1 8338_EDP_N3_S CV337 1 8338_EDP_N3 8338_EDP_P3 <32>
1 Pl1/SCL_CTL OUT2_D3n 31 2 0.1U_0402_16V7K
PL0 CV338 0.1U_0402_16V7K 8338_EDP_N3 <32>
60 Pl0/SDA_CTL
26 CPU_EDP_AUX_C
OUT1_AUXp_SCL CPU_EDP_AUX#_C CPU_EDP_AUX_C <40>
22 IN_DDC_SCL OUT1_AUXn_SDA 27 CPU_EDP_AUX#_C <40>
23 IN_DDC_SDA
CPU_EDP_AUX 0.1U_0402_10V6K~D 2 1 CV105 CPU_EDP_AUXP 24 28 8338_EDP_AUX
<8> CPU_EDP_AUX CPU_EDP_AUX# CPU_EDP_AUXN IN_AUXp OUT2_AUXp_SCL 8338_EDP_AUX# 8338_EDP_AUX <32>
0.1U_0402_10V6K~D 2 1 CV106 25 29
<8> CPU_EDP_AUX# IN_AUXn OUT2_AUXn_SDA 8338_EDP_AUX# <32>
CFG_0 59 43 8338_CA_DET
CFG_1 CFG0 OUT1_CA_DET 2136_HPD#
58 48 2136_HPD# <40>
PC10 CFG1 OUT1_HPD
56
PC11 PC10 8338_CA_DET 8338_CA_DET RV405
55 33 1 2 1M_0402_5%~D
PC20 PC11 OUT2_CA_DET 8338_EDP_HPD#
54 38 8338_EDP_HPD# <32>
HPD_GPU RV403 1 @ PC21 PC20 OUT2_HPD CPU_EDP_HPD# @ RV503 1
2 100K_0402_5% 53 2 100K_0402_5%
PC21 SW 10K_0402_5% 2
18 1 RV416 +3VS
CPU_EDP_HPD# RV404 1 SW PEQ
2 100K_0402_5% 11 8
GND PEQ PWDN PAD~D T143
19 14
GND PD

1
@ D
52 17
GND CEXT
61 20 2 PANEL_SW <19,34>
PAD(GND) REXT G
1

1
PS8338BQFN60GTR-A0_QFN60_5X9 S

3
RV504 CV317 QV54 SSM3K7002FU_SC70-3
2.2U_0402_6.3V6M
2
4.99K_0402_1% SEL PANEL_SW

2
L LVDS Panel

3 H eDP Panel 3
PC10 @ 1 2 +3VS
RV512 4.7K_0402_5%
@ 1 2
RV513 4.7K_0402_5%
CTL_EN @ 1 2 +3VS
RV505 4.7K_0402_5% AUX interception disable for Port y (y = 1, 2). Internal pull
Auto test enable; Internal pull down at ~150K Ohm, 3.3V I/O.
1 2 PC20 @ 1 2 down at ~150K Ohm, 3.3V I/O;
L: Auto test disable & input offset cancellation enable (default) +3VS
RV506 4.7K_0402_5% RV514 4.7K_0402_5% L: AUX interception enable, driver configuration is set by
H: Auto test enable & input offset cancellation enable
@ 1 2 link training (default)
M: Auto test disable & input offset cancellation disable
RV515 4.7K_0402_5% H: AUX interception disable, driver output with fixed 800mV
PL1 @ 1 2 +3VS and 0dB
RV507 4.7K_0402_5% M: AUX interception disable, driver output with fixed 400mV
1 2 PC11 @ 1 2 and 0dB
+3VS
RV508 4.7K_0402_5% RV516 4.7K_0402_5%
@ 1 2
Automatic EQ disable; Internal pull down at ~150K Ohm, 3.3V IO RV520 4.7K_0402_5%
L: Automatic EQ enable (default)
H: Automatic EQ disable
PC21 @ 1 2 +3VS Output swing adjustment for Port y (y = 1, 2).
RV521 4.7K_0402_5%
Internal pull down at ~150K Ohm, 3.3V I/O;
PL0 @ 1 2 +3VS @ 1 2 L: default
RV510 4.7K_0402_5% Chip operational mode configuration; RV517 4.7K_0402_5%
H: +20%
Internal pull down at ~150K Ohm, 3.3V I/O.
M: -16.7%
L: Control switching mode (default)
H: Automatic switching mode

Chip operational mode configuration; Programmable input equalization levels; Internal pull down at
CFG_0 @ 1 Internal pull down at ~150K Ohm, 3.3V I/O. ~150K Ohm, 3.3V I/O.
2 +3VS
RV509 4.7K_0402_5% L: Automatic power down enable (default) PEQ @ 1 L: default, LEQ, compensate channel loss up to 11.5dB @
2 +3VS
CFG_1 @ 1 H: Automatic power down disable RV518 4.7K_0402_5% HBR2
2
RV511 4.7K_0402_5% 1 2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2
4 RV519 4.7K_0402_5% 4
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
@ 1 2 +3VS
RV522 4.7K_0402_5%

Security Classification Compal Secret Data


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU to EDP & LVDS MUX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 28 of 61
A B C D E
5 4 3 2 1

www.laptopblue.vn

D D

+3VS +3VS

CPU & MXM SW for EDP RV128 2 1 4.7K_0402_1%~D DP_IN3_AEQ#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 1 RV129 2 1 4.7K_0402_1%~D DP_IN4_AEQ#

CV61

CV62
UV9
2 2 INy_AEQ# (y=1, 2),Automatic RX equalization enable
54
VDD L:Disable input automatic equalization
31 47 DGPU_EDIDSEL# <21,36,42>
VDD SW_AUX
CPU_MXM_EDP_AUXP
H:Enable input automatic equalization
28 CPU_MXM_EDP_AUXP <33>
OUT_AUXp_SCL CPU_MXM_EDP_AUXN
27 CPU_MXM_EDP_AUXN <33>
DP_IN3_PEQ# OUT_AUXn_SDA
49
DP_IN4_PEQ# IN2_PEQ/SDA_CTL CPU_MXM_EDP_AUXP_L CV63 2
50 30 1 0.1U_0402_10V6K~D
DP_IN3_AEQ# IN1_PEQ/SCL_CTL AC_AUXp CPU_MXM_EDP_AUXN_L CV64 2
3 29 1 0.1U_0402_10V6K~D +3VS +3VS
DP_IN4_AEQ# IN1_AEQ# AC_AUXn
51
IN2_AEQ#

2
37
0.1U_0402_10V6K~D CV65 MXM_C_TX0P I2C_CTL_EN RV130 @ RV131 @
<29> MXM_TX0P 2 1 52
IN1_D0p

MXM
0.1U_0402_10V6K~D 2 1 CV66 MXM_C_TX0N 53 4.7K_0402_1%~D 4.7K_0402_1%~D
<29> MXM_TX0N IN1_D0n
0.1U_0402_10V6K~D 2 1 CV67 MXM_C_TX1P 55 34 CFG_OUTPUT_1
<29> MXM_TX1P IN1_D1p CFG_OUTPUT
0.1U_0402_10V6K~D 2 1 CV68 MXM_C_TX1N 56

1
<29> MXM_TX1N IN1_D1n
0.1U_0402_10V6K~D 2 1 CV69 MXM_C_TX2P 1 44 RV406 1 2 1M_0402_5%~D DP_IN3_PEQ# DP_IN4_PEQ#
<29> MXM_TX2P MXM_C_TX2N IN1_D2p CA_DET
0.1U_0402_10V6K~D 2 1 CV70 2
<29> MXM_TX2N IN1_D2n
C 0.1U_0402_10V6K~D 2 1 CV71 MXM_C_TX3P 4 C
<29> MXM_TX3P IN1_D3p

1
0.1U_0402_10V6K~D 2 1 CV72 MXM_C_TX3N 5 42 CPU_MXM_EDP_A0P CPU_MXM_EDP_A0P <33>
<29> MXM_TX3N IN1_D3n OUT_D0p
41 CPU_MXM_EDP_A0N CPU_MXM_EDP_A0N <33> RV132 @ RV133 @
0.1U_0402_10V6K~D CV73 2 MXM_DPB_AUXP/DDC_C 24 OUT_D0n CPU_MXM_EDP_A1P 4.7K_0402_1%~D 4.7K_0402_1%~D
<29> MXM_DPB_AUXP/DDC 1 IN1_AUXp OUT_D1p
39 CPU_MXM_EDP_A1P <33>
0.1U_0402_10V6K~D CV74 2 1 MXM_DPB_AUXN/DDC_C 23 38 CPU_MXM_EDP_A1N CPU_MXM_EDP_A1N <33>
<29> MXM_DPB_AUXN/DDC IN1_AUXn OUT_D1n
20 36 CPU_MXM_EDP_A2P CPU_MXM_EDP_A2P <33>

2
IN1_SCL OUT2_D2p CPU_MXM_EDP_A2N
19 35 CPU_MXM_EDP_A2N <33>
IN1_SDA OUT2_D2n CPU_MXM_EDP_A3P
33 CPU_MXM_EDP_A3P <33>
OUT_D3p CPU_MXM_EDP_A3N
32 CPU_MXM_EDP_A3N <33>
0.1U_0402_10V6K~D CV75 8338_EDP_P0_C OUT_D3n
<31> 8338_EDP_P0 2 1 7
0.1U_0402_10V6K~D CV76 8338_EDP_N0_C IN2_D0p
<31> 8338_EDP_N0 2 1 8 INy_PEQ(y = 1, 2),Programmable input
IN2_D0n

PS8338
0.1U_0402_10V6K~D 2 1 CV77 8338_EDP_P1_C 10
<31> 8338_EDP_P1 IN2_D1p equalization level setting
0.1U_0402_10V6K~D 2 1 CV78 8338_EDP_N1_C 11 48 DGPU_SELECT# DGPU_SELECT# <17,36,42>
<31> 8338_EDP_N1 IN2_D1n SW_ML/I2C_ADDR
0.1U_0402_10V6K~D 2 1 CV308 8338_EDP_P2_C 13
<31> 8338_EDP_P2
0.1U_0402_10V6K~D CV307 8338_EDP_N2_C IN2_D2p L:Low EQ setting (LEQ), default
<31> 8338_EDP_N2 2 1 14
0.1U_0402_10V6K~D CV305 8338_EDP_P3_C IN2_D2n CFG_HPD_1 H:High EQ setting (HEQ)
<31> 8338_EDP_P3 2 1 15 46
0.1U_0402_10V6K~D CV306 8338_EDP_N3_C IN2_D3p CFG_HPD LV_DP_HPD
<31> 8338_EDP_N3 2 1 16 43 LV_DP_HPD <33> M:No EQ
IN2_D3n OUT_HPD
0.1U_0402_10V6K~D 2 1 CV79 8338_EDP_AUX_C 26
<31> 8338_EDP_AUX 8338_EDP_AUX#_C25 IN2_AUXp
0.1U_0402_10V6K~D 2 1 CV80 18 CFG_OUTPUT: output configuration
<31> 8338_EDP_AUX# IN2_AUXn REXT
22 17
IN2_SCL CEXT L:Output is tracking DPCD register setting (auto interception)
21
IN2_SDA
H:Output swing level fixed at 600mV and no pre-emphasis

2.2U_0402_6.3V6M~D
45

4.99K_0402_1%
GND

1
<29> MXM_DPB_HPD 6
IN1_HPD GND
12 1 M:Output swing level is fixed at 400mV and no pre-emphasis

CV81
9 57

RV134
<31> 8338_EDP_HPD# IN2_HPD Epad
40
PD
2

2
PS8321QFN56GTR-A0_QFN56_7X7 +3VS +3VS
MXM_DPB_AUXP/DDC

2
MXM_DPB_AUXN/DDC
1

RV135 @ RV136
RV137 4.7K_0402_1%~D 4.7K_0402_1%~D
100K_0402_5%~D
AUX_SEL/SEL1&2 Chanel Source

1
1

6 2

RV138 0 IN1 PS8838


100K_0402_5%~D CFG_OUTPUT_1 CFG_HPD_1
B B
QV1A 1 IN2 MXM
DMN66D0LDW-7_SOT363-6~D
2

2 DP_MXM_CARD_SEL <30,43>

1
RV139 RV140
1

@ 4.7K_0402_1%~D 4.7K_0402_1%~D

2
3

DMN66D0LDW-7_SOT363-6~D
5
QV1B
MXM_MFG_SEL GPU Source
CFG_HPD,HPD switching configuration
4

0 NVDIA L:HPD is switched by SW_ML


1 ATI H:HPD is switched by SW_AUX
M:HPD is switched with overlap

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP SW-CPU & MXM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 29 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn
+3VS +3VS +3VS +3VS

eDP POWER

2
W=60mils
RV142 @ RV143 @ RV144 @
+EDPVDD +EDPVDD +INVPWR_B+ +EDPVDD +5VS RV141 4.7K_0402_1%~D 4.7K_0402_1%~D 4.7K_0402_1%~D
QV10 4.7K_0402_1%~D
FDS4435BZ_SO8~D

1
D D
8 CFG_HPD_2 DP_IN5_PEQ# DP_IN6_PEQ# CFG_OUTPUT_2
7 1

1
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

100_0402_5%~D

4.7U_0805_10V4Z~D
6 2

47K_0402_5%~D

4.7U_0805_10V4Z~D
1 1 1 1 1 5 3 RV146 @ RV147 @

1
CV83

RV149
4.7K_0402_1%~D 4.7K_0402_1%~D

CV84

CV85
1 RV145 @ RV148
CV82

RV150

CV86
4.7K_0402_1%~D 4.7K_0402_1%~D

CV87
4

2
2 2 2 2 2

2
2

2
CFG_HPD,HPD switching configuration INy_PEQ(y = 1, 2),Programmable input CFG_OUTPUT: output configuration

6
L:HPD is switched by SW_ML equalization level setting L:Output is tracking DPCD register setting (auto interception)
QV4A
H:HPD is switched by SW_AUX L:Low EQ setting (LEQ), default H:Output swing level fixed at 600mV and no pre-emphasis

0.1U_0603_25V7K~D
Close to JEDP1 DMN66D0LDW-7_SOT363-6~D
2 2 1 M:HPD is switched with overlap H:High EQ setting (HEQ) M:Output swing level is fixed at 400mV and no pre-emphasis
RV151 2 M:No EQ

200K_0402_5%
220K_0402_1%

CV88
1

1
RV152
<BOM Structure> +3VS
1 +3VS

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
@ RV153 2 1 4.7K_0402_1%~D DP_IN5_AEQ#
1 1 CPU/GPU & 4028 SW for DPB

CV89

CV90
QV4B @ RV155 2 1 4.7K_0402_1%~D DP_IN6_AEQ#
0_0402_5%~D 1 2 RV154 5 DMN66D0LDW-7_SOT363-6~D
<34,41,42> LCDVDD_ON
UV10
0_0402_5%~D 1 2 RV156 @ INy_AEQ# (y=1, 2),Automatic RX equalization enable 2 2

4
<42,43> EC_ENVDD
L:Disable input automatic equalization 54
VDD
31 47
H:Enable input automatic equalization VDD SW_AUX HDMI_IN_SELECT# <42,43>
28 EDP_AUX+
OUT_AUXp_SCL EDP_AUX-
27
DP_IN5_PEQ# OUT_AUXn_SDA
49
QV11 DP_IN6_PEQ# IN2_PEQ/SDA_CTL EDP_AUX+_C CV91 1
50
IN1_PEQ/SCL_CTL AC_AUXp
30 2 0.1U_0402_10V7K~D
B+ FDC654P-G_SSOT-6~D DP_IN5_AEQ# 3 29 EDP_AUX-_C CV92 1 2 0.1U_0402_10V7K~D
DP_IN6_AEQ# IN1_AEQ# AC_AUXn
Back light power 80 mil 51
IN2_AEQ#
80 mil
D
6 +INVPWR_B+
S

4 5 37
4028_EDP_L0P I2C_CTL_EN
C 2 <38> 4028_EDP_L0P 52 C
IN1_D0p
1000P_0402_50V7K~D

1 <38> 4028_EDP_L0N 4028_EDP_L0N 53


IN1_D0n
G

1 4028_EDP_L1P 55 34 CFG_OUTPUT_2
<38> 4028_EDP_L1P IN1_D1p CFG_OUTPUT
1

1 <38> 4028_EDP_L1N 4028_EDP_L1N 56


3

RV157 CV93 4028_EDP_L2P IN1_D1n EDP_CAB_DET#_R


4028 <38> 4028_EDP_L2P 1
IN1_D2p CA_DET
44
CV94

100K_0402_5%~D 0.1U_0603_50V4Z~D 4028_EDP_L2N 2


2 <38> 4028_EDP_L2N IN1_D2n
<38> 4028_EDP_L3P 4028_EDP_L3P 4
2 4028_EDP_L3N IN1_D3p EDP_A0P_L 0.1U_0402_10V7K~D CV95 EDP_A0P
<38> 4028_EDP_L3N 5 42 1 2
2

IN1_D3n OUT_D0p EDP_A0N_L 0.1U_0402_10V7K~D CV96 EDP_A0N


41 1 2
PWR_SRC_ON OUT_D0n
<38> 4028_EDP_AUXP
0.1U_0402_10V7K~D 1 2 CV974028_EDP_AUXP_C 24 39 EDP_A1P_L 0.1U_0402_10V7K~D 1 2 CV98 EDP_A1P
IN1_AUXp OUT_D1p
<38> 4028_EDP_AUXN
0.1U_0402_10V7K~D 1 2 CV994028_EDP_AUXN_C 23 38 EDP_A1N_L 0.1U_0402_10V7K~D 1 2 CV100 EDP_A1N
QV12 IN1_AUXn OUT_D1n EDP_A2P_L 0.1U_0402_10V7K~D CV101 EDP_A2P
20 36 1 2
SSM3K7002FU_SC70-3~D IN1_SCL OUT2_D2p EDP_A2N_L 0.1U_0402_10V7K~D CV102 EDP_A2N
19 35 1 2
Inverter power IN1_SDA OUT2_D2n
OUT_D3p
33 EDP_A3P_L 0.1U_0402_10V7K~D 1 2 CV103 EDP_A3P
1 2 1 3 32 EDP_A3N_L 0.1U_0402_10V7K~D 1 2 CV104 EDP_A3N
D

RV158 47K_0402_5%~D CPU_MXM_EDP_A0P OUT_D3n


<32> CPU_MXM_EDP_A0P 7
CPU_MXM_EDP_A0N IN2_D0p
<32> CPU_MXM_EDP_A0N 8
B+ +INVPWR_B+ CPU_MXM_EDP_A1P IN2_D0n
10
G

<32> CPU_MXM_EDP_A1P
2

CPU_MXM_EDP_A1N IN2_D1p HDMI_IN_SELECT#


<32> CPU_MXM_EDP_A1N 11 48
@ LV1 1 CPU_MXM_EDP_A2P IN2_D1n SW_ML/I2C_ADDR
2
FBMA-L11-201209-221LMA30T_0805
CPU/MXM <32> CPU_MXM_EDP_A2P
CPU_MXM_EDP_A2N
13
14
IN2_D2p
<43> LCD_BKL_EN <32> CPU_MXM_EDP_A2N IN2_D2n
80 mil <32> CPU_MXM_EDP_A3P CPU_MXM_EDP_A3P 15 46 CFG_HPD_2
CPU_MXM_EDP_A3N IN2_D3p CFG_HPD EDP_HPD
FDC654P: P CHANNAL <32> CPU_MXM_EDP_A3N 16
IN2_D3n OUT_HPD
43
CPU_MXM_EDP_AUXP
AUX_SEL/SEL1&2 Chanel Source
Panel backlight power control by EC <32> CPU_MXM_EDP_AUXP 26
IN2_AUXp
CPU_MXM_EDP_AUXN 25 18 0 A 4028
<32> CPU_MXM_EDP_AUXN IN2_AUXn REXT
22 17
+3VS IN2_SCL CEXT
21
IN2_SDA 1 B CPU/MXM

2.2U_0402_6.3V6M~D
2 1 EDP_HPD
JEDP1 1 2 EDP_AUX- CV107 0.1U_0402_16V4Z~D 45

4.99K_0402_1%
GND

1
45 44 EDP_A0P_CONN RV159 100K_0402_5%~D 2 1 DISPOFF# 6 12 1
MGND1 CONNTST <38> DP_4028_HPD IN1_HPD GND

RV161
EDP_A0N_CONN @ 2 EDP_HPD CV108 0.1U_0402_16V4Z~D

CV110
46 43 1 <32> LV_DP_HPD 9 57
MGND2 GND RV160 100K_0402_5%~D IN2_HPD Epad
47 42 40
MGND3 LANE1_N EDP_A1P_CONN PD
48
MGND4 LANE1_P
41 1 2 EDP_AUX+
49 40 EDP_A1N_CONN RV162 100K_0402_5%~D 2
Close to JEDP1

2
MGND5 GND
50 39 2 1 EDP_CAB_DET#_R PS8321QFN56GTR-A0_QFN56_7X7
MGND6 LANE0_N EDP_A2P_CONN RV163 1M_0402_5%~D
51 38
MGND7 LANE0_P EDP_A2N_CONN
52 37
MGND8 GND
53 36
MGND9 AUX_CH_P EDP_A3P_CONN DV3
54 35
B MGND10 AUX_CH_N EDP_A3N_CONN USB20_P11_CONN 1 DMIC0_CONN RV164 1 @
B
55 34 6 2 0_0402_5%~D
MGND11 GND V I/O V I/O RV165 1 @
56
MGND12 LCD_VCC
33 2 0_0402_5%~D
57 32 EDP_AUX+_CONN 2 5
MGND13 LCD_VCC Ground V BUS +5VS
31 EDP_AUX-_CONN LV2
LCD_VCC USB20_N11_CONN 3 DMIC_CLK_CONN LV3 EDP_A3P EDP_A3P_CONN
30 4 4 3
TEST EDP_HPD V I/O V I/O LV4 EDP_A0P EDP_A0P_CONN
29 4 3
GND LCD_TEST IP4223CZ6_SO6~D DMIC0_CONN
28 LCD_TEST <42,43>+3VS <42,45> DMIC0 1 2
HPD EDP_A3N EDP_A3N_CONN
27 1 2
BL_GND
1

26 USB20_N11_CONN BLM18BB221SN1D_2P~D @ CV111 EDP_A0N 1 2 EDP_A0N_CONN


BL_GND USB20_P11_CONN DLW21SN670HQ2L_4P~D
25 10P_0402_50V8J~D
BL_PWR
1

24 DLW21SN670HQ2L_4P~D
2

BL_PWR DMIC_CLK_CONN @ RV166 RV167 @


23 1 2 0_0402_5%~D
BL_PWR DMIC0_CONN 10K_0402_5%~D LV5 RV168 @
22 1 2 0_0402_5%~D
BL_PWR DMIC_CLK_CONN RV169 1 @
BL_GND
21 <42,45> DMIC_CLK 1 2 2 0_0402_5%~D
20 EDP_CAB_DET# RV170 1 @ 2 0_0402_5%~D
2

BL_GND EDP_CAB_DET# <21>


1

19 LV6 BLM18BB221SN1D_2P~D @ CV112


BL_PWM 10P_0402_50V8J~D LV7
18 1 2 INV_PWM <42>
SMBUS_CLK BLM18BB221SN1D_2P~D LV8 EDP_AUX+ EDP_AUX+_CONN
17 4 3
2

SMBUS_DATA CAM_DET# EDP_A1P EDP_A1P_CONN


16 CAM_DET# <18,42> 1 4 3
ALS_VCC DISPOFF# CV113 @
15 DISPOFF# <42>
ALS_INT# 120P_0402_50VNPO~D EDP_AUX- EDP_AUX-_CONN
14 1 2
GND
13
Reserve @ EDP_A1N 1 2 EDP_A1N_CONN
CAM_MIC_CBL_DET# 2 RV171 1
USB+
12 2 0_0402_5%~D DLW21SN670HQ2L_4P~D
11 +3VS DLW21SN670HQ2L_4P~D RV172
USB- @
10 +3VS_CAM 1 2 0_0402_5%~D
USB_VCC LV9 RV173 @
9 1 2 0_0402_5%~D
MIC_CLK USB20_P11 USB20_P11_CONN
8 <20> USB20_P11 1 2
MIC_GND 1 2 RV174 1 @
7 2 0_0402_5%~D
MIC_DAT
6
GND USB20_N11 USB20_N11_CONN
5 +EDPVDD 4 3
PWR_LED
4 +EDPVDD +3VS_CAM <20> USB20_N11 4 3 LV10
BATT2_LED DLW21SN900SQ2L_0805_4P~D EDP_A2P EDP_A2P_CONN
3 4 3
BATT1_LED @
2 1 1
GND CV114 CV115 RV175 1
1 +INVPWR_B+ 2 0_0402_5%~D
CONNTST EDP_A2N EDP_A2N_CONN
1 2
1 2 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
I-PEX_20505-044E-011G~D 2 2 DLW21SN670HQ2L_4P~D
CONN@ CV116
0.1U_0603_50V4Z~D RV176 1 @ 2 0_0402_5%~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP SW-eDP CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 30 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn
STDP6038 to EDP & LVDS MUX

D D

UV31

16 PANEL_SW
SLE1 PANEL_SW <19,31>

2 5 LVDS_6038_TXOUT0- <37>
<42> LVDS_TXOUT0- 0B1 A0
1 6 LVDS_6038_TXOUT0+ <37>
<42> LVDS_TXOUT0+ 1B1 A1
80
<38> EDP_TXOUT0- 0B2
79 1B2
<38> EDP_TXOUT0+
78 2B1 A2 8 LVDS_6038_TXOUT1- <37>
<42> LVDS_TXOUT1-
77 3B1 A3 9 LVDS_6038_TXOUT1+ <37>
<42> LVDS_TXOUT1+
76 2B2
<38> EDP_TXOUT1-
75 3B2
<38> EDP_TXOUT1+
73 4B1 A4 11 LVDS_6038_TXOUT2- <37>
<42> LVDS_TXOUT2-
<42> LVDS_TXOUT2+ 72 5B1 A5 12 LVDS_6038_TXOUT2+ <37>
71 4B2
<38> EDP_TXOUT2-
70 5B2
<38> EDP_TXOUT2+

<42> LVDS_TXCLK- 68 6B1 A6 14 LVDS_6038_TXCLK- <37>


67 7B1 A7 15 LVDS_6038_TXCLK+ <37>
<42> LVDS_TXCLK+
66 6B2
<38> EDP_TXCLK-
65 7B2
<38> EDP_TXCLK+
64 8B1 A8 17
C C
63 9B1 A9 18
LVDS PANEL
62 8B2 Input
eDP PANEL Output 61 9B2
34 PANEL_SW
SEL2

60 23 LVDS_6038_TZOUT0- <37>
<42> LVDS_TZOUT0- 10B1 A10
59 24 LVDS_6038_TZOUT0+ <37>
<42> LVDS_TZOUT0+ 11B1 A11
58
<38> EDP_TZOUT0- 10B2
57
<38> EDP_TZOUT0+ 11B2
56 26 LVDS_6038_TZOUT1- <37>
<42> LVDS_TZOUT1- 12B1 A12
<42> LVDS_TZOUT1+ 55 27 LVDS_6038_TZOUT1+ <37>
13B1 A13
54
<38> EDP_TZOUT1- 12B2
<38> EDP_TZOUT1+ 53
13B2
51 29 LVDS_6038_TZOUT2- <37>
<42> LVDS_TZOUT2- 14B1 A14
50 30 LVDS_6038_TZOUT2+ <37>
<42> LVDS_TZOUT2+ 15B1 A15
49
<38> EDP_TZOUT2- 14B2
48
<38> EDP_TZOUT2+ 15B2
46 32 LVDS_6038_TZCLK- <37>
<42> LVDS_TZCLK- 16B1 A16
45 33 LVDS_6038_TZCLK+ <37>
<42> LVDS_TZCLK+ 17B1 A17
44
<38> EDP_TZCLK- 16B2
43
<38> EDP_TZCLK+ 17B2
B B
42 35
18B1 A18
41 36
19B1 A19
40 +3VS
18B2
39
19B2
+3VS
3 4
GND1 VDD1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D
13 10
GND2 VDD2
1

<33,41,42> LCDVDD_ON 20 19 1 1 1
GND3 VDD3

CV311

CV310

CV309
RV397 21 22
GND4 VDD4
2 100K_0402_5%~D 31 28
GND5 VDD5
G

38 37
GND6 VDD6 2 2 2
52 47
2

GND7 VDD7
74 69
GND8 VDD8
S

3 1 25
OE2#
7
OE1#

QV29
SSM3K7002F_SC59-3~D PI3LVD1012BE_BQSOP80

PANEL_SW Y
L LVDS
H eDP
A A

Security Classification Compal Secret Data


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
STDP6038 to EDP & LVDS MUX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 31 of 61
5 4 3 2 1
A B C D E

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1 1

+5VALW

QV13
SI3456DDV-T1-GE3_TSOP6~D +HDMI_5V_OUT

D
6

S
+3.3VS UV11 5 4
1 2

10U_0603_6.3V6M~D
CV117
42 22 HDMI_IN_CK- HDMI_IN_CK- <37> 1 1
VDD BTMDSCLK- HDMI_IN_CK+
40 23 HDMI_IN_CK+ <37>

G
VDD BTMDSCLK+
0.1U_0402_16V4Z~D

10U_1206_16V4Z

0.1U_0402_16V4Z~D

1U_0402_6.3V6K~D
CV118
30 24 HDMI_IN_D0- HDMI_IN_D0- <37>

3
VDD BMTDS0- HDMI_IN_D0+ 2
20 25
1 1 1 VDD BTMDS0+ HDMI_IN_D0+ <37>
STDP6038 2
CV119

CV120

CV121

18 26 HDMI_IN_D1- HDMI_IN_D1- <37>


VDD BTMDS1- HDMI_IN_D1+
16 27 HDMI_IN_D1+ <37>
VDD BMTDS1+ HDMI_IN_D2-
8 28 HDMI_IN_D2- <37>
2 2 2 VDD BTMDS2- HDMI_IN_D2+
2 29 HDMI_IN_D2+ <37>
VDD BTMDS2+ RV178
31 HDMI_OUT_TXC- 1 2
ATMDSCLK- HDMI_OUT_TXC- <36> <43> HDMI_OUT_EN
32 HDMI_OUT_TXC+ RV177
ATMDSCLK+ HDMI_OUT_TXC+ <36>
33 HDMI_OUT_TXD0- 102K_0402_1% 0_0402_5%~D 1
ATMDS0- HDMI_OUT_TXD0- <36>
HDMI_IN_OUT_TXC-_R 15 34 HDMI_OUT_TXD0+ @
TMDSCLK- ATMDS0+ HDMI_OUT_TXD0+ <36>

0.1U_0603_50V7K~D
CV122

0_0402_5%~D
RV179
HDMI_IN_OUT_TXC+_R 14 35 HDMI_OUT_TXD1-
TMDSCLK+ ATMDS1- HDMI_OUT_TXD1- <36>
CPU/MXM

1
HDMI_IN_OUT_TXD0-_R HDMI_OUT_TXD1+ D
12 36
HDMI CONN HDMI_IN_OUT_TXD0+_R
HDMI_IN_OUT_TXD1-_R
11
7
TMDS0-
TMDS0+
ATMDS1+
ATMDS2-
37
38
HDMI_OUT_TXD2-
HDMI_OUT_TXD2+
HDMI_OUT_TXD1+ <36>
HDMI_OUT_TXD2- <36> <43,56> PCH_PWR_EN
PCH_PWR_EN 2
G
2

TMDS1- ATMDS2+ HDMI_OUT_TXD2+ <36>


HDMI_IN_OUT_TXD1+_R 6 QV14 S

3
HDMI_IN_OUT_TXD2-_R TMDS1+ +1.5VS SSM3K7002FU_SC70-3~D
4
HDMI_IN_OUT_TXD2+_R TMDS2- @ RV180 1
3 39 2 0_0402_5%~D
TMDS2+ VSS

0.1U_0402_16V4Z~D

10U_1206_16V4Z

0.1U_0402_16V4Z~D
2 41 LV11 2
VSS DLW21SN900HQ2L_0805_4P~D
21 1 1 1
VSS
CV123

CV124

CV125
19 HDMI_IN_OUT_TXD2+_R 2 HDMI_IN_OUT_TXD2+
HDMI_SW VSS 2 1 1
<43> HDMI_SW 9 17
SEL VSS
13
VSS 2 2 2 HDMI_IN_OUT_TXD2-_R HDMI_IN_OUT_TXD2-
10 3 4
VSS 3 4
43 5
GND_PAD VSS
1 1 2
+1.5VS
VSS
TS3DV421RUAR_WQFN42_9X3P5
@ RV181 0_0402_5%~D HDMI Input/Output Connector
@ RV182 1 2 0_0402_5%~D +HDMI_5V_OUT
LV12
DLW21SN900HQ2L_0805_4P~D
SEL OUTPUT HDMI_IN_OUT_TXD1-_R 3 3 HDMI_IN_OUT_TXD1- JHDMI1
4 4 HDMI_IN_OUT_HPD 19
HP_DET
18
HDMI_IN_OUT_TXD1+_R HDMI_IN_OUT_TXD1+ HDMI_IN_OUT_DDC +5V
L A 2
2 1
1
HDMI_IN_OUT_SDATA
17
16
DDC/CEC_GND
HDMI_IN_OUT_SCLK SDA
1 2 15
+5VS SCL
H B @ RV183 0_0402_5%~D
<37> UART_TX_6038
RV184 1 2 0_0402_5%~D HDMI_UART_TX 14
Reserved
<37> UART_RX_6038
RV185 1 2 0_0402_5%~D HDMI_UART_RX 13
HDMI_IN_OUT_TXC- CEC
12 20
+5VS CK- GND
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
@ RV186 1 2 0_0402_5%~D 11 21
LV13 HDMI_IN_OUT_TXC+ CK_shield GND
1 1 10 22
UV12 CK+ GND
CV126

CV127
DLW21SN900HQ2L_0805_4P~D HDMI_IN_OUT_TXD0- 9 23
HDMI_IN_OUT_TXD0+_R HDMI_IN_OUT_TXD0+ D0- GND
16 2 2
1 1
8
HDMI_IN_OUT_SDATA Vcc HDMI_IN_OUT_TXD0+ D0_shield
4 7
HDMI_IN_OUT_SCLK 1A DVI_SDATA 2 2 HDMI_IN_OUT_TXD1- D0+
7 2 DVI_SDATA <36> 6
HDMI_IN_OUT_HPD 2A 1B1 HDMI_DAT HDMI_IN_OUT_TXD0-_R HDMI_IN_OUT_TXD0- D1-
9 3 HDMI_DAT <37> 3 4 5
HDMI_IN_OUT_DDC 3A 1B2 DVI_SCLK 3 4 HDMI_IN_OUT_TXD1+ D1_shield
12 5 DVI_SCLK <36> 4
4A 2B1 HDMI_CLK HDMI_IN_OUT_TXD2- D1+
6 HDMI_CLK <37> 1 2 3
2B2 HDMI_SINK_HPD_R @ RV187 0_0402_5%~D D2-
15 11 HDMI_SINK_HPD_R <36> 2
HDMI_SW OE# 3B1 HDMI_IN_HPD_R HDMI_IN_OUT_TXD2+ D2_shield
1 10 HDMI_IN_HPD_R <37> 1
S 3B2 D2+
14
4B1 HDMI_IN_DET# @ RV188 1
8 13 HDMI_IN_DET# <37> 2 0_0402_5%~D SUYIN_100042GR019M23UZL
GND 4B2 CONN@
LV14
HDMI_IN_OUT_TXC-_R 3 4 HDMI_IN_OUT_TXC-
SN74CBT3257CPWR_TSSOP16~D 3 4
3 3

HDMI_IN_OUT_TXC+_R 2 HDMI_IN_OUT_TXC+ 46@ ROYALTY HDMI W/LOGO


2 1 1
DLW21SN900HQ2L_0805_4P~D Part Number Description
1 2 RO0000002HM HDMI W/Logo:RO0000002HM
SEL OUTPUT @ RV189 0_0402_5%~D

L B1 HDMI_IN_OUT_TXC- CV349 1 2 3.3P_0402_50V8C~D

Reserve for EMI please close to JHDMI2 HDMI_IN_OUT_TXC+ CV350 1 2 3.3P_0402_50V8C~D


H B2 HDMI_IN_OUT_TXD0- CV351 1 2 3.3P_0402_50V8C~D

HDMI_IN_OUT_TXD0+ CV352 1 2 3.3P_0402_50V8C~D

HDMI_IN_OUT_TXD1- CV353 1 2 3.3P_0402_50V8C~D


+5VS
HDMI_IN_OUT_TXD1+ CV354 1 2 3.3P_0402_50V8C~D
4.7K_0402_5%~D

HDMI_IN_OUT_TXD2- CV355 1 2 3.3P_0402_50V8C~D


2
RV120

HDMI_IN_OUT_TXD2+ CV356 1 2 3.3P_0402_50V8C~D

20120531 EMI ADD


1

<43> HDMI_IN_OUT_DDC HDMI_IN_OUT_DDC

<43> HDMI_IN_OUT_HPD HDMI_IN_OUT_HPD


1
100K_0402_5%~D
RV119
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI In/Out SW/Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 32 of 61
A B C D E
5 4 3 2 1

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+3VS

+3VS +3VS
@ RV402 1 2 4.7K_0402_5%~D +3VS
Close to UV2 VCC pins

1
@ RV401 1 2 4.7K_0402_5%~D HDMI_PWDN

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D
RV190
RV191 1 2 4.7K_0402_5%~D @ RV193 LV15 100K_0402_5%~D 1 1 1 1

1
+3VS C 200K_0402_5% MBK1608221YZF_2P

CV128

CV129

CV130

CV131
@ RV192 1 2 4.7K_0402_5%~D HDMI_DDCBUF @QV15 2 1 2 1 2 HDMI_SINK_HPD

2
220P_0402_50V7K~D
MMST3904-7-F_SOT323-3~D B HDMI_OE#
@ RV194 1 2 4.7K_0402_5%~D E +3VS 2 2 2 2
1

BAV99-7-F_SOT23-3

CV132
2 1

.1U_0402_16V7K~D

.1U_0402_16V7K~D

200K_0402_5%
@ RV195 1 2 4.7K_0402_5%~D HDMI_CFG_HPD HDMI_SW_DETECT QV16 D

G
1 2

2
D D

10U_0603_6.3V6M~D

10K_0402_5%~D

DV4
RV196 0_0402_5%~D QV17

11
15
21
33
40
46
1 1 1 2

CV135

RV198

@
RV197 1 2 4.7K_0402_5%~D 2 SSM3K7002F_SC59-3~D UV13

2
CV133

CV134

@
G

S
1 3

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
RV199 1 2 4.7K_0402_5%~D HDMI_IN2_PEQ

RV200

3
2 2 2 S HDMI_TXD2+ 38

1
RV201 1 3 HDMI_TXD2- IN1p
2 4.7K_0402_5%~D SSM3K7002F_SC59-3~D 39
HDMI_TXD1+ IN1n
41

1
RV202 1 HDMI_IN1_PEQ HDMI_TXD1- IN2p
2 4.7K_0402_5%~D +5VS 42
IN2n
HDMI_TXD0+ 44 23 HDMI_OUT_TXD2+ HDMI_OUT_TXD2+ <35>
HDMI_TXD0- IN3p OUT1p HDMI_OUT_TXD2-
45 22 HDMI_OUT_TXD2- <35>
HDMI_TXC+ IN3n OUT1n HDMI_OUT_TXD1+
47 20 HDMI_OUT_TXD1+ <35>
DGPU_HPD_INT# HDMI_TXC- IN4p OUT2p HDMI_OUT_TXD1-
Close to U3 VCC pins 48 19
<21,39> DGPU_HPD_INT# IN4n OUT2n
OUT3p
17
16
HDMI_OUT_TXD0+
HDMI_OUT_TXD0-
HDMI_OUT_TXD1- <35>
HDMI_OUT_TXD0+ <35> CONN
OUT3n HDMI_OUT_TXD0- <35>
PS8271 +3VS 2
POW OUT4p
14 HDMI_OUT_TXC+ HDMI_OUT_TXC+ <35>
13 HDMI_OUT_TXC- HDMI_OUT_TXC- <35>
PEQ=L, Middle level receiving equalization selection HDMI_SINK_HPD_R 30
OUT4n
<35> HDMI_SINK_HPD_R HPD_SINK
PEQ=H, High level receiving equalization selection
+3VS RV203 1 2 4.7K_0402_5%~D
PEQ=M, Low level receiving equalization selection +3VS 26
I2C_CTL_EN#
UV14 HDMI_DDCBUF 32
PS121 NC/DDCBUF_EN#
When DDCBUF_EN# is HIGH, the DDC channel is disabled, HDMI_OE# 25 7 HDMI_SINK_HPD
NC/OE# HPD
6
SCL/SDA and SCLZ/SDAZ are disconnected VDD DVI_SDATA_R
31 8
VDD DVI_SCLK_R SDA
9
+3VS SCL HDMI_SW_SDA
29
HDMI_PWDN HDMI_CFG1 SDAZ HDMI_SW_SCL
25 34 28
GPU_HDMI_TXD2- CV136 2 .1U_0402_16V7K~D GPU_HDMI_TXD2-_C PWDN_ASQ HDMI_CFG0 SDA_CTL/CFG1 SCLZ
<29> GPU_HDMI_TXD2- 1 44 35
GPU_HDMI_TXD2+ CV137 2 .1U_0402_16V7K~D GPU_HDMI_TXD2+_C IN1_D1n HDMI_CFG_HPD SCL_CTL/CFG0
<29> GPU_HDMI_TXD2+ 1 45 28
GPU_HDMI_TXD1- CV138 2 .1U_0402_16V7K~D GPU_HDMI_TXD1-_C IN1_D1p CFG_HPD RV204 @ HDMI_PC0
<29> GPU_HDMI_TXD1- 1 47 3
GPU_HDMI_TXD1+ CV139 2 .1U_0402_16V7K~D GPU_HDMI_TXD1+_C IN1_D2n HDMI_DDCBUF 4.7K_0402_5%~D HDMI_PC1 I2C_ADDR0/PC0
MXM <29>
<29>
GPU_HDMI_TXD1+
GPU_HDMI_TXD0-
GPU_HDMI_TXD0- CV140 2
1
1 .1U_0402_16V7K~D GPU_HDMI_TXD0-_C
48
1
IN1_D2p
IN1_D3n
DDCBUF
PRE_EMI
40
34 1 2
4
I2C_ADDR1/PC1
GPU_HDMI_TXD0+ CV141 2 1 .1U_0402_16V7K~D GPU_HDMI_TXD0+_C 2 7 HDMI_PC2 1
<29> GPU_HDMI_TXD0+ IN1_D3p RTERM GND/PC2

2
GPU_HDMI_TXC- CV142 2 1 .1U_0402_16V7K~D GPU_HDMI_TXC-_C 4
<29> GPU_HDMI_TXC- IN1_D4n
GPU_HDMI_TXC+ CV143 2 1 .1U_0402_16V7K~D GPU_HDMI_TXC+_C 5 RV399
<29> GPU_HDMI_TXC+ IN1_D4p @ 4.7K_0402_5%~D 499_0402_1%~D 2 1 RV205 6
REXT

GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
2.2U_0402_6.3V6M~D2 1 CV144 10

1
C
CEXT C

CPU_HDMI_N2 CV145 1 2 .1U_0402_16V7K~D CPU_HDMI_N2_C 8 PS121QFN48G_QFN48_7X7

5
12
18
24
27
31
36
37
43
49
<8> CPU_HDMI_N2 IN2_D1n
CPU_HDMI_P2 CV146 1 2 .1U_0402_16V7K~D CPU_HDMI_P2_C 9
<8> CPU_HDMI_P2 CPU_HDMI_N1 CPU_HDMI_N1_C IN2_D1p
CV147 1 2 .1U_0402_16V7K~D 11
<8> CPU_HDMI_N1 IN2_D2n
CPU_HDMI_P1 CV148 .1U_0402_16V7K~D CPU_HDMI_P1_C HDMI_TXD2-
CPU <8>
<8>
CPU_HDMI_P1
CPU_HDMI_N0
CPU_HDMI_N0 CV149
1
1
2
2 .1U_0402_16V7K~D CPU_HDMI_N0_C
12
13
IN2_D2p
IN2_D3n
OUT_D1n
OUT_D1p
36
35 HDMI_TXD2+
CPU_HDMI_P0 CV150 1 2 .1U_0402_16V7K~D CPU_HDMI_P0_C 14 33 HDMI_TXD1-
<8> CPU_HDMI_P0 IN2_D3p OUT_D2n
CPU_HDMI_N3 CV151 1 2 .1U_0402_16V7K~D CPU_HDMI_N3_C 16 32 HDMI_TXD1+ PS121 CFG0/ CFG1
<8> CPU_HDMI_N3 CPU_HDMI_P3 CPU_HDMI_P3_C IN2_D4n OUT_D2p HDMI_TXD0-
CV152 1 2 .1U_0402_16V7K~D 17 30
<8> CPU_HDMI_P3 IN2_D4p OUT_D3n
29 HDMI_TXD0+ SCLZ/SDAZ output voltage select;
OUT_D3p HDMI_TXC- CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V
27
OUT_D4n HDMI_TXC+
OUT_D4p
26 PS121 PC0/PC1/PC2
Inputs equalization control, default inputs equalization setting at 12 dB
<29> VGA_HDMI_DET 46
IN1_HPD
000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
<17> PCH_HDMI_HPD 10 100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB
GPU_HDMI_SCLK IN2_HPD
<29> GPU_HDMI_SCLK 41
GPU_HDMI_SDATA IN1_SCL
<29> GPU_HDMI_SDATA 42
PCH_DPB_HDMI_CLK IN1_SDA
<17> PCH_DPB_HDMI_CLK 19
PCH_DPB_HDMI_DAT IN2_SCL
<17> PCH_DPB_HDMI_DAT 20
IN2_SDA +3VS
+3VS DGPU_EDIDSEL#_R 22 39 HDMI_SW_DETECT
DGPU_SEL# SW_DDC OUT_HPD HDMI_SW_SCL 4.7K_0402_5%~D HDMI_CFG1
21 38 2 1 RV206 @
2.2K_0402_5%~D 2 PCH_DPB_HDMI_DAT SW_MAIN OUT_SCL HDMI_SW_SDA HDMI_CFG0
1 RV207 37 4.7K_0402_5%~D 2 1 RV208 @
OUT_SDA 4.7K_0402_5%~D HDMI_PC0
2 1 RV209
2.2K_0402_5%~D 2 PCH_DPB_HDMI_CLK
1 RV210 HDMI_IN1_PEQ 3 4.7K_0402_5%~D 2 1 RV211 @ HDMI_PC1
HDMI_IN2_PEQ IN1_PEQ 4.7K_0402_5%~D HDMI_PC2
15 2 1 RV212
IN2_PEQ 2.2K_0402_5%~D HDMI_SW_SDA
2 1 RV213
2.2K_0402_5%~D 2 1 RV214 HDMI_SW_SCL
23
CEXT
24
+3V_MXM REXT
2.2U_0603_10V7K~D

4.7K_0402_5%~D 2 1 RV215 @ HDMI_CFG1


1
CV153

2.2K_0402_5%~D 2 1 RV216GPU_HDMI_SDATA 1 4.7K_0402_5%~D 2 1 RV217 @ HDMI_CFG0


499_0402_1%~D

RV218

18 4.7K_0402_5%~D 2 1 RV219 @ HDMI_PC0


2.2K_0402_5%~D 2 GPU_HDMI_SCLK GND HDMI_PC1
1 RV220 43
GND
4.7K_0402_5%~D 2 1 RV221 @
49 4.7K_0402_5%~D 2 1 RV222 @ HDMI_PC2
2 PAD
2

PS8271QFN48GTR-A1_QFN48_7X7
B B

8/25 change RV53 +HDMI_5V_OUT

+3VS from 430 to HDMI_SW_DET 0 1


CV154 499ohm +HDMI_5V_OUT
2 1

3
Y IN1 IN2
0.01U_0402_16V7K~D
5

@ DV5 @ DV6

1
1.5K_0402_5%

RV223

1.5K_0402_5%

RV224
1 DAN217T146_SC59-3 DAN217T146_SC59-3
P

<21,32,42> DGPU_EDIDSEL# IN1


4 DGPU_EDIDSEL#_R MXM PCH Place LC Filter
O
<21> PCH_GPIO35 2

1
IN2 closed to JHDMI
G

UV15
3

2
SN74AHC1G08DCKR_SC70-5
DVI_SDATA_R 1 2 DVI_SDATA DVI_SDATA <35>
DVI_SCLK_R RV225 1 0_0402_5%~D
2 DVI_SCLK DVI_SCLK <35>
DGPU_EDIDSEL# 0_0402_5%~D 2 1 RV227 DGPU_EDIDSEL#_R <39> RV226 0_0402_5%~D

10P_0402_50V8J~D

10P_0402_50V8J~D
@ 1 1
@ CV155 @ CV156
+5VS +HDMI_5V_OUT
DV7 W=40mils
BAT1000-7-F_SOT23-3~D 2 2
3 NC FV5
2 1 +HDMI_5V 1 2
5A_125V_R451005.MRL~D
1U_0603_10V6K~D

1U_0603_10V4Z~D

1
@

1
CV158

CV157

@
0_1206_5%~D 2 1 RV228 2
2

+3VS
CV159
2 1

A 0.01U_0402_16V7K~D A
5

1
P

<17,32,42> DGPU_SELECT# IN1


O 4 DGPU_SEL#
PCH_GPIO35 2 IN2
G

UV16
3

SN74AHC1G08DCKR_SC70-5

DGPU_SELECT#
Security Classification Compal Secret Data Compal Electronics, Inc.
0_0402_5%~D 2 1 RV229 DGPU_SEL# DGPU_SEL# <39> Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI SW-CPU & MXM/Re-driver
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 33 of 61
5 4 3 2 1
5 4 3 2 1

+3VS

1
LV16
2
+3.3VS_AVDD
+3.3VS_AVDD

1
LV17
2
+3.3V_AVDD_LVTX +1.2VS_HDMI

1
LV18
2
+1.2V_AVDD
www.laptopblue.vn +3VS +5VS +1.2VS_HDMI
LV19
+1.2VS
For 4028
LV20
+1.2VS_A
+3.3V_DVDD

RV230 1 2 10K_0402_5%~D BS_I2C_DEV_ID2

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0402_16V4Z~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
BLM18BD601SN1D_0603~D BLM18BD601SN1D_0603~D BLM18BD601SN1D_0603~D RV231 1 2 100K_0402_5%~D 2 1 2 1

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D
1 2 2 2 2 1 2 2 2 2 BLM18AG601SN1D_0603~D BLM18AG601SN1D_0603~D RV232 1 2 10K_0402_5%~D BS_I2C_DEV_ID1

CV160

1U_0402_6.3V6K~D
CV161

CV162

CV163

CV166

CV167

CV168

CV169
2 2 2 1

CV164

CV165

.1U_0402_16V7K~D

CV173
RV233 1 2 10K_0402_5%~D BS_I2C_DEV_ID0

CV170

CV171

CV172
1

CV174

10K_0402_5%~D
0_0402_5%~D
Can not place large capacitor to 1.2V

1
2 1 1 1 1 2 1 1 1 1

CV175
RV234
prevent pulse happened when LVDS 1 TDC 0.52A UV17 RV235 1 2 10K_0402_5%~D BS_UART_FUNCTION_SEL
1 1 2

RV236
power switch off/on Peak Current 0.73A 2 4 5 RV237 1 2 10K_0402_5%~D BS_RESERVED_R

2
VDD NC
OCP current 3.5A

2
3 6 RV238 1 2 10K_0402_5%~D BS_SPI_R

2
D +3VS +3.3V_DVDD VIN VOUT D

BS_I2C_SRC_R

10U_0805_4VAM~D
1 2 7 RV239 1 2 10K_0402_5%~D
EN ADJ

CV176
LV21
+1.2VS_HDMI +1.2V_DVDD

20K_0402_5%~D
1 2 1 8 RV240 1 2 10K_0402_5%~D BS_I2C_ON_R
PGOOD GND

1
22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
BLM18BD601SN1D_0603~D +3.3VS_AVDD 9
+3.3V_AVDD_RPLL 2 GND

RV241
1 2 2 2 LV22 RV242 1 2 10K_0402_5%~D BS_EXTKEY_EN
LV23 1 2 RT9025-25PSP_SO8 HDMI_SPI_CLK_R
CV178

CV179

CV180
CV177

1 2 BLM18AG601SN1D_0603~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

15_0402_5%~D 15P_0402_50V8J~D
BLM18BD601SN1D_0603~D RV243 1 2 10K_0402_5%~D BS_OCM_BOOT_SEL

1
2 1 1 1

@ RV244
1 2 1 2 2 2 2 2 2
RV245 1 2 10K_0402_5%~D BS_INTERFACE_SEL1

CV182

CV184

CV185

CV186

CV187

CV188

CV189
CV181

CV183
AVDD_RPLL pin10 C610 0.1uF
RV246 1 2 10K_0402_5%~D BS_INTERFACE_SEL0
to AVSS_RPLL pin7 2 1 2 1 1 1 1 1 1
Close to respective power Pins

2
RV247 1 2 10K_0402_5%~D BS_XTAL_TCLK_SEL
1

@
RV248 1 2 10K_0402_5%~D BS_OSC_SEL

CV190
RV249 1 2 10K_0402_5%~D HDMI_IN_AUD_CODEC
2

+3.3V_DVDD

.1U_0402_16V7K~D
RV250 1 2 22_0402_5% EC_HDMI_CLK
+3.3V_AVDD_RPLL <43> EC_SMB_CK2_R
RV251 1 2 22_0402_5% EC_HDMI_DAT
EC_HDMI_CLK <38>
2Mbit 2

CV191
<43> EC_SMB_DA2_R EC_HDMI_DAT <38>

SPI ROM
10P_0402_50V8J~D

10P_0402_50V8J~D

UV1
RV252 1
+3.3V_AVDD_RPLL 10 116 +1.2V_DVDD
VDDA_3V3 CVDD_12 15_0402_5%~D UV18
1 108
CVDD_12 HDMI_SPI_CS# 2 HDMI_SPI_CS#_R
1 46 1 1 8
CVDD_12 S# VCC
CV192

CV193

35 HDMI_SPI_SO 1 2 HDMI_SPI_SO_R 2 7 10K_0402_5%~D 2 1 RV254


CVDD_12 RV253 1 15_0402_5%~D Q RESET# HDMI_SPI_CLK_R 15_0402_5%~D 1 RV256 HDMI_SPI_CLK
+3.3V_AVDD_LVTX 11 +3.3V_DVDD 2 3 6 2
2 AVDD_OUT_33 RV255 10K_0402_5%~D W# C HDMI_SPI_SI_R 15_0402_5%~D 1 RV257 HDMI_SPI_SI
23 88 4 5 2
YV1 2 AVDD_OUT_33 ADC_DVDD_1V2 VSS D <BOM Structure>
TCLK 1 3 XTAL 50 MX25L2006EM1I-12G_SOP8
DPRX_VDDD_1V2
2 G2 4
G1
C
+3.3VS_AVDD 80 64 +1.2V_AVDD C
27MHZ_10PF_X3S027000BA1H-U~D HDMI_VDDA_3V3 DPRX_VDDA_1V2 +3.3V_DVDD
86 58
HDMI_VDDA_3V3 DPRX_VDDA_1V2 +3.3V_DVDD
90 52
ADC_AVDD_3V3 DPRX_VDDA_1V2
100
ADC_AVDD_3V3
6
VDDA_1V2

4.7K_0402_1%~D

0.1U_0402_16V4Z~D

4.7K_0402_1%~D

4.7K_0402_1%~D
38
+3.3V_DVDD RVDD_33
16KBit 1

1
@
109
+3.3V_DVDD RVDD_33

RV258

CV194

RV259

RV260
128
RVDD_33
NVRAM 2
2.2K_0402_5%~D 4700P_0402_25V7K~D

33 LVDS_6038_TXOUT0- LVDS_6038_TXOUT0- <34>


O_CH0N_LV / TTL_D29 / GPIO_67
2

32 LVDS_6038_TXOUT0+ LVDS_6038_TXOUT0+ <34> UV19

2
O_CH0P_LV / TTL_D28 / GPIO_66
RV261

XTAL 8 31 LVDS_6038_TXOUT1- LVDS_6038_TXOUT1- <34> 1 8


TCLK XTAL O_CH1N_LV / TTL_D27 / GPIO_65 LVDS_6038_TXOUT1+ E0 VCC
9 30 LVDS_6038_TXOUT1+ <34> 2 7
TCLK O_CH1P_LV / TTL_D26 / GPIO_64 LVDS_6038_TXOUT2- E1 WC RV262 1 DHMI_IN_NV_CLK_R
29 LVDS_6038_TXOUT2- <34> 3 6 2 22_0402_5%
O_CH2N_LV / TTL_D25 / GPIO_63 LVDS_6038_TXOUT2+ E2 SCL RV263 1 DHMI_IN_NV_DAT_R
36 28 LVDS_6038_TXOUT2+ <34> 4 5 2 22_0402_5%
1

NC O_CH2P_LV / TTL_D24 / GPIO_62 LVDS_6038_TXCLK- VSS SDA


27 LVDS_6038_TXCLK- <34>
HDMI_RST# O_CLKN_LV / TTL_D23 / GPIO_61 LVDS_6038_TXCLK+ CAT24C16WI-GT3_SO8
4 26 LVDS_6038_TXCLK+ <34>
RV264 1 RESETn O_CLKP_LV / TTL_D22 / GPIO_60
2 10K_0402_5%~D 125
STI_TM2 O_CH3N_LV / TTL_D21 / GPIO_59
25
24
CV195 0.1U_0402_16V4Z~D 92 O_CH3P_LV / TTL_D20 / GPIO_58
1 2
1 ADC_A_N LVDS
CV197

CV196 1 2 0.1U_0402_16V4Z~D 93 21 LVDS_6038_TZOUT0- +HDMI_5V_OUT +5VS


ADC_A_P E_CH0N_LV / TTL_D19 / GPIO_57 LVDS_6038_TZOUT0- <34>
CV198 1 2 0.1U_0402_16V4Z~D 95 20 LVDS_6038_TZOUT0+ LVDS_6038_TZOUT0+ <34>
CV199 0.1U_0402_16V4Z~D 96 ADC_B_N E_CH0P_LV / TTL_D18 / GPIO_56 LVDS_6038_TZOUT1-
1 2 19 LVDS_6038_TZOUT1- <34>
2 CV200 0.1U_0402_16V4Z~D 98 ADC_B_P E_CH1N_LV / TTL_D17 / GPIO_55 LVDS_6038_TZOUT1+
1 2 18 LVDS_6038_TZOUT1+ <34> 2 1 1 2
CV201 0.1U_0402_16V4Z~D 99 ADC_C_N E_CH1P_LV / TTL_D16 / GPIO_54 LVDS_6038_TZOUT2- DV8 2 1 1 2
1 2 17 LVDS_6038_TZOUT2- <34>
CV202 0.1U_0402_16V4Z~D 105 ADC_C_P E_CH2N_LV / TTL_D15 / GPIO_53 LVDS_6038_TZOUT2+ 1SS355TE-17_SOD323-2 DV9 1SS355TE-17_SOD323-2
1 2 16 LVDS_6038_TZOUT2+ <34>
CV203 0.1U_0402_16V4Z~D 106 HSYNC_IN E_CH2P_LV / TTL_D14 / GPIO_52 LVDS_6038_TZCLK- +5VS_HDMI_IN_EDID
1 2 15 LVDS_6038_TZCLK- <34>
VSYNC_IN E_CLKN_LV / TTL_D13 / GPIO_51 LVDS_6038_TZCLK+
14 LVDS_6038_TZCLK+ <34> 1
+3.3V_DVDD +3.3V_DVDD E_CLKP_LV / TTL_D12 / GPIO_50
1 2 70
VEDID_VDD_3V3 E_CH3N_LV / TTL_D11 / GPIO_49
13

4.7K_0402_1%~D

4.7K_0402_1%~D

4.7K_0402_1%~D
CV204 0.1U_0402_16V4Z~D 12 CV205
E_CH3P_LV / TTL_D10 / GPIO_48

1
EC_HDMI_DAT 71 EDID_WP 0.1U_0402_16V4Z~D
A_I2C_SDA
1

MMST3904-7-F_SOT323-3~D

RV265

RV266

RV267
EC_HDMI_CLK 72
HDMI_SW_DAT A_I2C_SCL
73
4.7K_0402_5%~D HDMI_SW_CLK D1_I2C_SDA / GPIO_28 HDMI_IN_BKL_EN
74 3 HDMI_IN_BKL_EN <42>
D1_I2C_SCL / GPIO_29 PBIAS / TTL_D9 / GPO_4

1
RV409 44 2 HDMI_IN_ENVDD C
HDMI_IN_ENVDD <42>

2
HDMI_IN_EN D2_I2C_SDA / GPIO_24 PPOWER / TTL_D8 / GPO_3 UV20
<43> HDMI_IN_EN 45 1 2 2
1 2

D2_I2C_SCL / GPIO_25

QV18
22_0402_5% RV268 B 1 8
BS_OCM_BOOT_SEL E E0 VCC RV269 1 EDID_WP
111 1 2 7 2 22_0402_5%

3
PAD~D T60 @ GPIO_44 / S_I2C_SCL GPO_2 / TTL_D7 / PWM2(BS_OCM_BOOT_SEL) HDMI_IN_AUD_CODEC RV270 1 E1 WC HDMI_SW_CLK
112 127 2 0_0402_5%~D HDMI_IN_AUDIO_CODEC <45> 3 6 RV271 1 2 100_0402_1%~D HDMI_CLK HDMI_CLK <35>
PAD~D T58 @ GPIO_43 / S_I2C_SDA STI_TM1 / PWM1 / TTL_D6 / GPO_1 HDMI_IN_PWM E2 SCL HDMI_SW_DAT
@ 4.7K_0402_5%~D 126 HDMI_IN_PWM <42> 4 5 RV272 1 2 100_0402_1%~D HDMI_DAT HDMI_DAT <35>
B RV410 GPO_0 / PWM0 / TTL_D5(BS_OSC_SEL) BS_I2C_DEV_ID2 VSS SDA B
124
TTL_D4 / GPIO_21(BS_I2C_DEV_ID2) BS_I2C_DEV_ID1 BS_OSC_SEL CAT24C02WI-GT3A_SO8
48 123 1 2
2

DPRX_AUXN TTL_D3 / GPIO_20(BS_I2C_DEV_ID1) BS_I2C_DEV_ID0 RV273 0_0402_5%~D


49 122
DPRX_AUXP TTL_D2 / GPIO_19(BS_I2C_DEV_ID0) DHMI_IN_NV_CLK_R DHMI_IN_NV_CLK +3.3V_DVDD
53
DPRX_ML_L0P TTL_D1 / GPIO18 / M_I2C_SCL
121 1 2 DHMI_IN_NV_CLK <42> 2Kbit
54 120 DHMI_IN_NV_DAT_R RV395
1 20_0402_5%~D DHMI_IN_NV_DAT
DPRX_ML_L0N TTL_D0 / GPIO17 / M_I2C_SDA DHMI_IN_NV_DAT <42>

10K_0402_5%~D
56 RV396 0_0402_5%~D
DPRX_ML_L1P HDMI_IN_CAB_DET# <43>

1
57 1 2 BS_XTAL_TCLK_SEL
DPRX_ML_L1N

RV275
59 RV274 0_0402_5%~D
+1.2V_AVDD 60
62
DPRX_ML_L2P
DPRX_ML_L2N
119 BS_EXTKEY_EN
2KBit +HDMI_5V_OUT
DPRX_ML_L3P TTL_CKOUT / GPIO16(BS_EXTKEY_EN) <BOM Structure>
63 118 UART_TX_6038

2
DPRX_ML_L3N UART_TX / TTL_SYNC1 / GPO_7(BS_XTAL_TCLK_SEL) UART_TX_6038 <35>
1 2 51 117 UART_RX_6038
DPRX_REXT UART_RX / TTL_SYNC2 / GPO_6 UART_RX_6038 <35>
RV276 300_0402_1% 43 HDMI_PLUG_IN_CAB_DET 2 1HDMI_IN_CAB_DET#
DPRX_HPD_OUT / GPO_5 +5VS RV277 33K_0402_5%

+HDMI_5V_OUT

.1U_0402_16V7K~D
5 1
VBUFC_RPLL

1
D

CV206
HDMI_IN_CK- RV278 1 2 10_0402_5%~D HDMI_IN_CK-_R 75
<35> HDMI_IN_CK- HDMI_RXCN

0.1U_0402_16V4Z~D

100K_0402_5%~D
HDMI_IN_CK+ RV279 1 2 10_0402_5%~D HDMI_IN_CK+_R 76 QV19 2
<35> HDMI_IN_CK+ HDMI_RXCP

2
HDMI_IN_D0- RV280 1 2 10_0402_5%~D HDMI_IN_D0-_R 78 1 SSM3K7002FU_SC70-3~D G
<35> HDMI_IN_D0- HDMI_RX0N

1
2
CV207

RV285
HDMI_IN_D0+ RV281 1 2 10_0402_5%~D HDMI_IN_D0+_R 79 RV282 RV283 S

3
<35> HDMI_IN_D0+ HDMI_RX0P 4.7K_0402_5%~D
HDMI_IN_D1- RV284 1 2 10_0402_5%~D HDMI_IN_D1-_R 81
<35> HDMI_IN_D1- HDMI_RX1N 1K_0402_1%~D
HDMI_IN_D1+ RV286 1 2 10_0402_5%~D HDMI_IN_D1+_R 82 103 RV287 2 1 10K_0402_5%~D
<35> HDMI_IN_D1+
HDMI_IN_D2- RV288 1 2 10_0402_5%~D HDMI_IN_D2-_R 84
HDMI_RX1P HDMI LBADC_IN4 / GPIO_35
104 HDMI_PLUG_IN_CAB_DET 2

1
<35> HDMI_IN_D2- HDMI_RX2N LBADC_IN3 / GPIO_34
HDMI_IN_D2+ RV289 1 2 10_0402_5%~D HDMI_IN_D2+_R 85 101 RV290 2 1 10K_0402_5%~D

2
<35> HDMI_IN_D2+ HDMI_RX2P LBADC_IN2 / GPIO_33 / TTL_SYNC4

MMST3904-7-F_SOT323-3~D
RV291
1 2 249_0402_1%~D 87 102 RV292 2 1 10K_0402_5%~D UART_RX_6038
+3.3VS_AVDD HDMI_REXT LBADC_IN1 / GPIO_32 / TTL_SYNC3
HDMI_IN_SW_HPD 113 HDMI_IN_HPD_R LV24
HDMI_HPD / GPIO_22 HDMI_IN_HPD_R <35>
114 HDMI_IN_SW_HPD 2 1 HDMI_IN_HPD
HDMI_CEC / GPIO_23

220P_0402_50V7K~D
110 MBK1608221YZF_2P
GPIO_45 HDMI_TOGGLE <43>
1

1
QV20
C

CV208
<45> I2S_DAT/SPDIF_IN @ RV293 1 20_0402_5%~D BS_RESERVED_R 39 HDMI_IN_HPD 1 2 2
BS_SPI_R I2S_0 (S/PDIF) / GPO_12(BS_RESERVED) 22_0402_5% RV294 B
40
BS_I2C_SRC_R I2S_AUMCLK / GPO_13(BS_SPI_FUN_SEL) E BAV99-7-F_SOT23-3 2
41 7

3
BS_I2C_ON_R I2S_WS / GPO_14(BS_I2C_SRC_SEL) VSSA_33 DV10 @
42
I2S_SCLK / GPO_15(BS_I2C_ON_SPI_EN)

2
34
HDMI_SPI_CS# LVVSS +HDMI_5V_OUT
65 22
BS_INTERFACE_SEL1 RV295 1 HDMI_SPI_CLK SPI_CSn / IRQ_IN / GPO_8 LVVSS
2 0_0402_5%~D 66
BS_INTERFACE_SEL0 RV296 1 HDMI_SPI_SO SPI_CLK / GPO_9(BS_INTERFACE_SEL1)
2 0_0402_5%~D 67
SPI_DI / GPO_10(BS_INTERFACE_SEL0) CRVSS
115
A BS_UART_FUNCTION_SEL RV297 1 2 0_0402_5%~D HDMI_SPI_SI 68 107 A
SPI_DO / GPO_11(BS_UART_FUNCTION_SEL) CRVSS
CRVSS 69
47 DPRX_VSSD CRVSS 37
55 DPRX_VSSA
61 HDMI_IN_CAB_DET# RV298 1 2 0_0402_5%~D HDMI_IN_DET#
DPRX_VSSA HDMI_IN_DET# <35>
ADC_VSSA 97
77 HDMI_VSSA ADC_VSSA 94
83 HDMI_VSSA ADC_VSSA 91
ADC_VSSD 89

STDP6038-AC_PQFP128_20X14~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI to LVDS-STDP6038
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 34 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

+1.2VS_A +3VS +AVDD_OUT_LV_33


D D
UV2C LV25
2 1

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
BLM18AG601SN1D_0603~D
C13 EC_HDMI_CLK_R @ RV299 2 1 0_0402_5%~D 1 2 2 2 2 2 2
AUX_I2C_SCL/GPIO_15 EC_HDMI_CLK <37>
0.1U_0603_25V7K~D

RV300 2 1 240_0402_1% C11 B14 EC_HDMI_DAT_R @ RV301 2 1 0_0402_5%~D


DPTX_REXT AUX_I2C_SDA_GPIO_16 EC_HDMI_DAT <37>

CV210

CV211

CV212

CV213

CV214

CV215
CV209
2 2 1 1 1 1 1 1
CV216

DP_4028_HPD C12 B13 I2C_SCL


<33> DP_4028_HPD DPTX_HPD_IN/GPIO_23 I2C_SCL/GPIO_24 I2C_SDA
A13
I2C_SDA/GPIO_25
1 4028_EDP_AUXN C10
<33> 4028_EDP_AUXN DPTX_AUXN
4028_EDP_AUXP D10
<33> 4028_EDP_AUXP DPTX_AUXP

4028_EDP_L0N B6 C2 UART_TX +1.2VS_A +VDD_RPLL_1V2 +3VS +AVDD_3V3 +1.2VS


<33> 4028_EDP_L0N DPTX_ML_L0N UART_TX/BOOT1/GPIO_13 UART_TX
4028_EDP_L0P C6 B1 UART_RX LV26 LV27
<33> 4028_EDP_L0P DPTX_ML_L0P UART_RX/GPIO_14 UART_RX
4028_EDP_L1N A7 2 1 2 1
<33> 4028_EDP_L1N DPTX_ML_L1N

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
4028_EDP_L1P B7 eDP BLM18AG601SN1D_0603~D BLM18AG601SN1D_0603~D
<33> 4028_EDP_L1P DPTX_ML_L1P +5VS

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
4028_EDP_L2N B12 AUX_UART_TX

SYS, Audio & DPTX


A8 1 2 2
<33> 4028_EDP_L2N 4028_EDP_L2P DPTX_ML_L2N AUX_UART_TX/BOOT4/GPIO_21
B8 A12 AUX_UART_RX 1 2 2 1 2 2 2 2
<33> 4028_EDP_L2P DPTX_ML_L2P AUX_UART_RX/GPIO_22

CV218

CV219
CV217
4028_EDP_L3N B9
<33> 4028_EDP_L3N DPTX_ML_L3N

CV221

CV222

CV224

CV225

CV226

CV227
0.1U_0402_16V4Z~D

CV220

CV223
4028_EDP_L3P C9
<33> 4028_EDP_L3P DPTX_ML_L3P 2 1 1

4.7K_0402_5%~D
1

2
2 1 1 2 1 1 1 1

CV228

RV302
2
D2

1
TX_XTAL I2S_0/GPIO_8
B4 F5
+AVDD_3V3 TX_XTAL I2S_1/GPIO_9 UART_RX +1.2VS_A +AVDD_LVRX_1V2 +3VS +1.2VS_A
F4
+3VS I2S_2/GPIO_10 LV28
D3
I2S_3/GPIO_11 +5VS 2 1
10P_0402_50V8J~D

10P_0402_50V8J~D

2.7K_0402_5%

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
BLM18AG601SN1D_0603~D
1

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
C1 1 2 2
TX_TCLK I2S_BCLK/GPIO_7
2 2 C4 1 2 2 1 2 2 2 2
TX_TCLK

CV230

CV231
RV303

0.1U_0402_16V4Z~D

4.7K_0402_5%~D

CV229

CV234
E4
I2S_WCLK/GPIO_4
CV232

CV233

CV235

CV236

CV238

CV239

CV240

CV241
2
@

CV237
1 2 1 1

CV242

RV304
2

1 1 RESET E6 E3 3D_VIDEO 2 1 1 2 1 1 1 1
C
RESETn CLK_OUT/GPIO_5/BOOT0 C
2
47P_0402_50V8J~D

1
TX_XTAL 1 3 TX_TCLK
CV243

2 SPI_DI_4028
G1 G2 4 SPI_DO_4028
D13
SPI_DI/HOST_D1/GPO_19 AUX_UART_RX +3VS
C14
1 SPI_CLK_4028 SPI_DO/HOST_D0/GPO_20
E12
SPI_CLK/HOST_CLK/GPIO_18 NC1
F12 20mils

0.1U_0402_16V4Z~D
SPI_CSN_4028 F10 G12
YV2 SPI_CSn/HOST_CS/GPIO_17 NC2 +3VS
D11
NC3

10K_0402_5%~D

10K_0402_5%~D
27MHZ_10PF_X3S027000BA1H-U~D E11 1
NC4

1
CV244
G4 B2
IR_IN/GPIO_6 NC5

RV306

RV307
B3 RV305 1 2 4.7K_0402_5%~D 3D_VIDEO
NC6 RV308 1 2 4.7K_0402_5%~D AUX_UART_TX 2Mbit
RV309 1 2 4.7K_0402_5%~D GPIO_3/BOOT6 UV3 2
IRQ/BOOT7 D12 RV310 1 2 4.7K_0402_5%~D I2C_SCL SPI_CSN_4028 1 8

2
IRQ/BOOT7/GPIO_12 GPIO_0/BOOT3 RV311 4.7K_0402_5%~D I2C_SDA SPI_DI_4028 S# VCC
E5 1 2 2 7
PWM0/GPIO_0/BOOT3 RV312 4.7K_0402_5%~D EC_HDMI_DAT_R Q RESET# SPI_CLK_4028
1 2 3 6
GPIO_1/BOOT2 RV313 4.7K_0402_5%~D EC_HDMI_CLK_R W# C SPI_DO_4028
D4 1 2 4 5
0_0402_5%~D GPIO_1/BOOT2 VSS D
2 1 RV314 C3
VBUFC_RPLL
G10 GPIO_2/BOOT5 RV315 1 2 4.7K_0402_5%~D UART_TX MX25L2006EM1I-12G_SOP8
GPIO_2/BOOT5 @ RV316 4.7K_0402_5%~D AUX_UART_TX
1 2
0_0402_5%~D 2 1 RV317 F3 F11 GPIO_3/BOOT6 RV318 1 2 4.7K_0402_5%~D GPIO_0/BOOT3
TESTMODE0 GPIO_3/BOOT6 RV319 4.7K_0402_5%~D GPIO_1/BOOT2 +1.2VS UV2D
1 2
RV320 1 2 4.7K_0402_5%~D GPIO_2/BOOT5
0_0402_5%~D 2 1 RV321 G3 @ RV322 1 2 4.7K_0402_5%~D GPIO_3/BOOT6 E7 A1
TESTMODE1 RV323 4.7K_0402_5%~D IRQ/BOOT7 PVDD1 PVSS3
1 2 E8 A14
PVDD1 PVSS3
K6
PVDD1
K9 F6
STDP4028-AB_LFBGA164 PVDD1 PVSS3
F7
+3VS PVSS3
F8
PVSS3
VEGA STDP4028 DPTx BootStraps PVSS3
F9
G11 G6
UV2B UV2A PVDD21 PVSS3
G7
PVSS3
G8
EDP_TZOUT0- EDP_TXOUT0- PVSS3
<34> EDP_TZOUT0- P8 M8 <34> EDP_TXOUT0- P2 M7 G9
EDP_TZOUT0+ O0_LVRX_CH0N_VIDIN23 O0_LVRX_CH5N_VIDIN_CLK EDP_TXOUT0+ E0_LVRX_CH0N_VIDIN13 E0_LVRX_CH5N_VIDIN_VSYNC PVSS3
<34> EDP_TZOUT0+ N8 L9 <34> EDP_TXOUT0+ N2 L6 G5 H6
O0_LVRX_CH0P_VIDIN22 O0_LVRX_CH5P_VIDIN_DE E0_LVRX_CH0P_VIDIN12 E0_LVRX_CH5P_VIDIN_HSYNC PVDD22 PVSS3
H7
EDP_TZOUT1- EDP_TXOUT1- PVSS3
<34> EDP_TZOUT1- N9 L11 <34> EDP_TXOUT1- P3 M3 H8
EDP_TZOUT1+ O0_LVRX_CH1N_VIDIN21 O0_LVRX_CH6N_VIDIN24 EDP_TXOUT1+ E0_LVRX_CH1N_VIDIN11 E0_LVRX_CH6N_VIDIN26 PVSS3
<34> EDP_TZOUT1+ M9 M12 <34> EDP_TXOUT1+ N3 L4 H9
O0_LVRX_CH1P_VIDIN20 O0_LVRX_CH6P_VIDIN25 E0_LVRX_CH1P_VIDIN10 E0_LVRX_CH6P_VIDIN27 PVSS3
J6
PVSS3

PWR & GND


EDP_TZOUT2- M10 EDP_TXOUT2- N4 +1.2VS_A J7
B <34> EDP_TZOUT2- O0_LVRX_CH2N_VIDIN19 <34> EDP_TXOUT2- E0_LVRX_CH2N_VIDIN9 PVSS3 B
EDP_TZOUT2+ L10 EDP_TXOUT2+ M4 J8
<34> EDP_TZOUT2+ O0_LVRX_CH2P_VIDIN18 <34> EDP_TXOUT2+ E0_LVRX_CH2P_VIDIN8 PVSS3
J9
EDP_TZCLK- EDP_TXCLK- PVSS3
<34> EDP_TZCLK- N11 <34> EDP_TXCLK- M5 B11
EDP_TZCLK+ O0_LVRX_CLKN_VIDIN17 EDP_TXCLK+ E0_LVRX_CLKN_VIDIN7 DPTX_VDDA_1V2
M11 L5 C7
O0 & O1 LVDS Input

E0 & E1 LVDS Input


<34> EDP_TZCLK+ O0_LVRX_CLKP_VIDIN16 <34> EDP_TXCLK+ E0_LVRX_CLKP_VIDIN6 DPTX_VDDA_1V2
C8
DPTX_VDDA_1V2
P12 N6 D9
O0_LVRX_CH3N_VIDIN15 E0_LVRX_CH3N_VIDIN5 DPTX_VDDA_1V2
N12 M6
O0_LVRX_CH3P_VIDIN14 E0_LVRX_CH3P_VIDIN4
D7
DPTX_VSSA
P13
N13
O0_LVRX_CH4N_VIDIN3
P7
N7
E0_LVRX_CH4N_VIDIN1 LVDS +AVDD_3V3
DPTX_VSSA
D8
E9
O0_LVRX_CH4P_VIDIN2 E0_LVRX_CH4P_VIDIN0 DPTX_VSSA
D6 E10
VDDA_3V3 DPTX_VSSA
D5
VDD33_TX
M13 G1
O1_LVRX_CH0N_VIDIN23 E1_LVRX_CH0N_VIDIN13 +VDD_RPLL_1V2
M14 G2 A2
O1_LVRX_CH0P_VIDIN22 E1_LVRX_CH0P_VIDIN12 VSS_RPLL
L12 H1 A3
O1_LVRX_CH1N_VIDIN21 E1_LVRX_CH1N_VIDIN11 VDD_RPLL
L13 H2 C5
O1_LVRX_CH1P_VIDIN20 E1_LVRX_CH1P_VIDIN10 VSSA_TX
K12 J2 +AVDD_LVRX_1V2
O1_LVRX_CH2N_VIDIN19 E1_LVRX_CH2N_VIDIN9
K11 J3 K7
O1_LVRX_CH2P_VIDIN18 E1_LVRX_CH2P_VIDIN8 AVSS_LVRX_12
J12 K3 L7
O1_LVRX_CLKN_VIDIN17 E1_LVRX_CLKN_VIDIN7 AVDD_LVRX_12
J13 K4
O1_LVRX_CLKP_VIDIN16 E1_LVRX_CLKP_VIDIN6 STDP4028-AB_LFBGA164 P1
AVSS_OUT_LVRX
H13 J10 L2 J5
O1_LVRX_CH3N_VIDIN15 O1_LVRX_CH5N_VIDIN_CLK E1_LVRX_CH3N_VIDIN5 E1_LVRX_CH5N_VIDIN_VSYNC +AVDD_OUT_LV_33
H14 H11 L3 H4
O1_LVRX_CH3P_VIDIN14 O1_LVRX_CH5P_VIDIN_DE E1_LVRX_CH3P_VIDIN4 E1_LVRX_CH5P_VIDIN_HSYNC
F2
AVSS_OUT_LVRX
G13 K10 M1 J4 H12 F13
O1_LVRX_CH4N_VIDIN3 O1_LVRX_CH6N_VIDIN24 E1_LVRX_CH4N_VIDIN1 E1_LVRX_CH6N_VIDIN26 AVDD_OUT_LVRX_33 AVSS_OUT_LVRX
G14 J11 M2 K5 H3 H10
O1_LVRX_CH4P_VIDIN2 O1_LVRX_CH6P_VIDIN25 E1_LVRX_CH4P_VIDIN0 E1_LVRX_CH6P_VIDIN27 AVDD_OUT_LVRX_33 AVSS_OUT_LVRX
L8 H5
AVDD_OUT_LVRX_33 AVSS_OUT_LVRX
N1 K8
AVDD_OUT_LVRX_33 AVSS_OUT_LVRX
N14 P14
STDP4028-AB_LFBGA164 STDP4028-AB_LFBGA164 AVDD_OUT_LVRX_33 AVSS_OUT_LVRX

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS to eDP-STDP4028
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 35 of 61
5 4 3 2 1
5 4 3 2 1

+3VS

+3V_MXM www.laptopblue.vn PCH_DPD_CLK


PCH_DPD_DAT
DMC_PWDN
DMC_CFG_HPD
RV30 2
RV31 2
@ RV324 1
@ RV325 1
1
1
2
2
2.2K_0402_5%~D
2.2K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
DMC_DDCBUF RV326 1 2 4.7K_0402_5%~D
1 2 VGA_DPD_AUXP/DDC +3VS DMC_PRE_EMI @ RV328 1 2 4.7K_0402_5%~D
RV327 2.2K_0402_5%~D DMC_IN1_PEQ RV329 1 2 4.7K_0402_5%~D
1 2 VGA_DPD_AUXN/DDC DMC_IN2_PEQ RV331 1 2 4.7K_0402_5%~D
RV330 2.2K_0402_5%~D
DMC_PWDN @ RV332 1 2 4.7K_0402_5%~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D
DMC_CFG_HPD @ RV333 1 2 4.7K_0402_5%~D

PCH/GPU AUX&LANE SW for DPB 1 2 DMC_DDCBUF @ RV334 1 2 4.7K_0402_5%~D

CV245

CV246
DMC_PRE_EMI @ RV335 1 2 4.7K_0402_5%~D
DMC_IN1_PEQ RV336 1 2 4.7K_0402_5%~D
D D
DMC_IN2_PEQ RV337 1 2 4.7K_0402_5%~D
UV21 2 1

6
VDD
31
VDD

25 DMC_PWDN
CV247 0.1U_0402_10V6K~D VGA_DPD_SW_P0 PWDN_ASQ
<29> VGA_DPD_P0 1 2 44
CV248 0.1U_0402_10V6K~D VGA_DPD_SW_N0 IN1_D1n DMC_CFG_HPD
<29> VGA_DPD_N0 1 2 45
IN1_D1p CFG_HPD
28
CV249 1 2 0.1U_0402_10V6K~D VGA_DPD_SW_P1 47
<29> VGA_DPD_P1 IN1_D2n
CV250 0.1U_0402_10V6K~D VGA_DPD_SW_N1 DMC_DDCBUF
MXM <29>
<29>
VGA_DPD_N1
VGA_DPD_P2
CV251
1
1
2
2 0.1U_0402_10V6K~D VGA_DPD_SW_P2
48
1
IN1_D2p
IN1_D3n
DDCBUF
PRE_EMI
40
34 DMC_PRE_EMI
CV252 1 2 0.1U_0402_10V6K~D VGA_DPD_SW_N2 2 7
<29> VGA_DPD_N2 IN1_D3p RTERM
CV253 1 2 0.1U_0402_10V6K~D VGA_DPD_SW_P3 4
<29> VGA_DPD_P3 IN1_D4n
CV254 1 2 0.1U_0402_10V6K~D VGA_DPD_SW_N3 5
<29> VGA_DPD_N3 IN1_D4p

CV255 1 2 0.1U_0402_16V4Z~D CPU_DPD_SW_P0 8 +3VS


<8> CPU_DPD_DMC_P0 CPU_DPD_SW_N0 IN2_D1n
CV256 1 2 0.1U_0402_16V4Z~D 9 Close to UV2 VCC pins
<8> CPU_DPD_DMC_N0 IN2_D1p
CV257 1 2 0.1U_0402_16V4Z~D CPU_DPD_SW_P1 11
<8> CPU_DPD_DMC_P1 IN2_D2n
CV258 0.1U_0402_16V4Z~D CPU_DPD_SW_N1 DMC_SW_P0 0_0402_5%~D DP_DMC_ML0P
CPU <8> CPU_DPD_DMC_N1 1 2 12
IN2_D2p OUT_D1n
36 RV338 1 2

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D
CV259 1 2 0.1U_0402_10V7K~D CPU_DPD_SW_P2 13 35 DMC_SW_N0 RV339 1 2 0_0402_5%~D DP_DMC_ML0N
<8> CPU_DPD_DMC_P2 IN2_D3n OUT_D1p
CV260 1 2 0.1U_0402_10V7K~D CPU_DPD_SW_N2 14 33 DMC_SW_P1 RV340 1 2 0_0402_5%~D DP_DMC_ML1P 1 1 1 1
<8> CPU_DPD_DMC_N2 CPU_DPD_SW_P3 IN2_D3p OUT_D2n DMC_SW_N1 DP_DMC_ML1N
CV261 1 2 0.1U_0402_10V7K~D 16 32 RV341 1 2 0_0402_5%~D
<8> CPU_DPD_DMC_P3 IN2_D4n OUT_D2p

CV263

CV264

CV265

CV266
CV262 1 2 0.1U_0402_10V7K~D CPU_DPD_SW_N3 17 30 DMC_SW_P2 RV342 1 2 0_0402_5%~D DP_DMC_ML2P
<8> CPU_DPD_DMC_N3 IN2_D4p OUT_D3n
29 DMC_SW_N2 RV343 1 2 0_0402_5%~D DP_DMC_ML2N
OUT_D3p DMC_SW_P3 0_0402_5%~D DP_DMC_ML3P +3VS 2 2 2 2
27 RV344 1 2
OUT_D4n DMC_SW_N3 0_0402_5%~D DP_DMC_ML3N
26 RV345 1 2
OUT_D4p

11
15
21
33
40
46
<29> VGA_DMC_HPD RV346 2 1 10K_0402_5%~D VGA_DMC_HPD_R 46 UV22
RV347 PCH_DMC_HPD_R IN1_HPD
2 1 10K_0402_5%~D 10

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
<17> PCH_DMC_HPD IN2_HPD
<29> VGA_DPD_AUXP/DDC 41
IN1_SCL DP_DMC_ML0P
<29> VGA_DPD_AUXN/DDC 42 38
IN1_SDA DP_DMC_ML0N IN1p
C
<17> PCH_DPD_CLK 19 39 C
IN2_SCL DP_DMC_ML1P IN1n
<17> PCH_DPD_DAT 20 41
IN2_SDA DP_DMC_ML1N IN2p
42
DGPU_EDIDSEL#_R DMC_SW_DETECT DP_DMC_ML2P IN2n CPU_MXM_DMC_P0
<36> DGPU_EDIDSEL#_R 22 39 44 23 CPU_MXM_DMC_P0 <51>
DGPU_SEL# SW_DDC OUT_HPD DP_DMC_AUXP DP_DMC_ML2N IN3p OUT1p CPU_MXM_DMC_N0
<36> DGPU_SEL# 21 38 45 22 CPU_MXM_DMC_N0 <51>
SW_MAIN OUT_SCL DP_DMC_AUXN DP_DMC_ML3P IN3n OUT1n CPU_MXM_DMC_P1
37 47 20 CPU_MXM_DMC_P1 <51>
OUT_SDA DP_DMC_ML3N IN4p OUT2p CPU_MXM_DMC_N1
48 19 CPU_MXM_DMC_N1 <51>
DMC_IN1_PEQ IN4n OUT2n CPU_MXM_DMC_P2
3 17 CPU_MXM_DMC_P2 <51>
DMC_IN2_PEQ IN1_PEQ OUT3p CPU_MXM_DMC_N2
15 16 CPU_MXM_DMC_N2 <51>
IN2_PEQ OUT3n CPU_MXM_DMC_P3
+3VS 2 14 CPU_MXM_DMC_P3 <51>
POW OUT4p CPU_MXM_DMC_N3
13 CPU_MXM_DMC_N3 <51>
DP_DMC_HPD OUT4n
23 <51> DP_DMC_HPD 30
CEXT HPD_SINK
24
REXT RV61 1
+3VS 2 4.7K_0402_5%~D 26
I2C_CTL_EN#
2.2U_0603_6.3V6K~D

499_0402_1%~D

1 DMC_DDCBUF 32
NC/DDCBUF_EN#
CV267

RV348

18
GND DMC_OE# DMC_SINK_HPD
43 25 7
GND NC/OE# HPD
49
2 PAD DMC_SDATA_R 8
2

PS8271QFN48GTR-A1_QFN48_7X7 DMC_SCLK_R SDA


9
SCL DP_DMC_AUXN
29
DMC_CFG1 SDAZ DP_DMC_AUXP
34 28
DMC_CFG0 SDA_CTL/CFG1 SCLZ
SEL Y 35
SCL_CTL/CFG0
DMC_PC0 3
DMC_PC1 I2C_ADDR0/PC0
0 IN1 4
I2C_ADDR1/PC1
1 IN2 DMC_PC2 1
GND/PC2

499_0402_1%~D 2 1 RV62 6
REXT

GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
2.2U_0402_6.3V6M~D2 1 CV268 10
CEXT

PS121QFN48G_QFN48_7X7

5
12
18
24
27
31
36
37
43
49
+3VS
+3VS
1

B B

RV349
@ RV350 LV29 100K_0402_5%~D PS121 CFG0/ CFG1
1

C 200K_0402_5% MBK1608221YZF_2P
@QV21 2 1 2 1 2 DMC_SINK_HPD SCLZ/SDAZ output voltage select;
2

CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V


220P_0402_50V7K~D

MMST3904-7-F_SOT323-3~D B DMC_OE#
E 1 PS121 PC0/PC1/PC2
3

1
@

BAV99-7-F_SOT23-3

CV269

2 1 Inputs equalization control, default inputs equalization setting at 12 dB


200K_0402_5%

DV11

DMC_SW_DETECT QV22 D
G

1 2
2
10K_0402_5%~D

RV351 0_0402_5%~D QV23 000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
2
RV352

2 SSM3K7002F_SC59-3~D 100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB


2

G
D

1 3
RV353

S
1

SSM3K7002F_SC59-3~D 3
1

+5VS
+3VS

DGPU_HPD_INT# 4.7K_0402_5%~D 2 1 RV354 @ DMC_CFG1


<21,36> DGPU_HPD_INT# 4.7K_0402_5%~D 2 1 RV355 @ DMC_CFG0
4.7K_0402_5%~D 2 1 RV356 DMC_PC0
4.7K_0402_5%~D 2 1 RV357 @ DMC_PC1
4.7K_0402_5%~D 2 1 RV358 DMC_PC2
2.2K_0402_5%~D 2 1 RV359 DP_DMC_AUXP
2.2K_0402_5%~D 2 1 RV360 DP_DMC_AUXN
+HDMI_5V_OUT

+HDMI_5V_OUT 4.7K_0402_5%~D 2 1 RV361 @ DMC_CFG1


4.7K_0402_5%~D 2 1 RV362 @ DMC_CFG0
2

4.7K_0402_5%~D 2 1 RV363 @ DMC_PC0


4.7K_0402_5%~D 2 1 RV364 @ DMC_PC1
@ DV12 @ DV13 4.7K_0402_5%~D 2 1 RV365 @ DMC_PC2
1

1
1.5K_0402_5%

RV366

1.5K_0402_5%

RV367

DAN217T146_SC59-3 DAN217T146_SC59-3
Place LC Filter
closed to JHDMI
1

A A
2

DMC_SDATA_R 1 2 CPU_MXM_DMC_AUXN CPU_MXM_DMC_AUXN <51>


DMC_SCLK_R RV368 1 0_0402_5%~D
2 CPU_MXM_DMC_AUXP CPU_MXM_DMC_AUXP <51>
RV369 0_0402_5%~D
10P_0402_50V8J~D

10P_0402_50V8J~D

1 1
@ CV270 @ CV271

2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DP SW for DMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 36 of 61
5 4 3 2 1
5 4 3 2 1

+3VS +3VS_RT +1.2VS

www.laptopblue.vn
+DVCC33
30mil 60 mils 30mil EEROM
1 2 1 LVDS@
2 +SWR_V12
RV7 0_0805_5% RV8 0_0805_5%

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
LVDS@ UV23
1 1 1 1 8 VCC A0 1
0_0402_5% 7 2
WP A1

CV272

CV273

CV274

CV275
LVDS@ MIIC_SCL RV23 1 LVDS@ 2 FW_ROM_SCL 6 3
MIIC_SDA RV24 FW_ROM_SDA SCL A2
1 LVDS@ 2 5 4
2 2 2 2 0_0402_5% SDA GND
EDID_CLK RV25 1 LVDS@ 2 0_0402_5% CAT24C64WI-GT3_SO8
EDID_DATA RV26 1 LVDS@ 2 0_0402_5% Addr: A8 (1010 100X)
D D
LVDS@
Close to LV11 Close to 11 pin Close to 43 pin
LVDS@ LVDS@ LVDS@

UV24

RTD2136S
+DVCC33 35 LVDS_ACLK
+3VS_RT LVDS@ TXOC+ LVDS_ACLK# LVDS_ACLK <41>
22 PVCC TXOC- 36
LVDS@ LVDS_ACLK# <41>
LV30 2 1 +DVCC33 40 mils 18 41 LVDS_A0
FBMA-L11-201209-221LMA30T_0805 SWR_VDD TXO0+ LVDS_A0# LVDS_A0 <41>
TXO0- 42
LVDS_A0# <41>

PWR
LV31 2 1 +AVCC33 5
FBMA-L11-201209-221LMA30T_0805 DP_V33 LVDS_A1
TXO1+ 39
+SWR_V12 LV32 1 +SW_LX 60 mils LVDS_A1# LVDS_A1 <41>
2 17 SWR_LX TXO1- 40
4.7UH_PG031B-4R7MS_1.1A_20% LVDS_A1# <41>
60 mils 15 37 LVDS_A2
LVDS@ SWR_VCCK TXO2+ LVDS_A2# LVDS_A2 <41>
TXO2- 38 LVDS_A2# <41>
43 VCCK
+AVCC33 +DVCC33 33
TXO3+
11 DP_V12 TXO3- 34
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1
25 LVDS_BCLK

LVDS
TXEC+ LVDS_BCLK <41>
CV276

CV277

CV278

CV279

CV280

CV281

CV282

CV283
CPU_EDP_P0_C 7 26 LVDS_BCLK#
<31> CPU_EDP_P0_C CPU_EDP_N0_C LANE0P TXEC- LVDS_BCLK# <41>
<31> CPU_EDP_N0_C 8 LANE0N
2 2 2 2 2 2 2 2 LVDS_B0
TXE0+ 31
CPU_EDP_P1_C LVDS_B0# LVDS_B0 <41>
<31> CPU_EDP_P1_C 9 LANE1P TXE0- 32 LVDS_B0# <41>
CPU_EDP_N1_C 10
<31> CPU_EDP_N1_C LANE1N

DP
C LVDS_B1 C
TXE1+ 29
CPU_EDP_AUX_C LVDS_B1# LVDS_B1 <41>
Close to LV9 Close to 5 pin Close to LV10 Close to 18 pin Close to 22 pin <31> CPU_EDP_AUX_C 4 AUX-CH_P TXE1- 30
LVDS_B1# <41>
CPU_EDP_AUX#_C 3
<31> CPU_EDP_AUX#_C AUX-CH_N
LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ 27 LVDS_B2
2136_HPD# TXE2+ LVDS_B2# LVDS_B2 <41>
1 DP_HPD TXE2- 28
<31> 2136_HPD# LVDS_B2# <41>

TXE3+ 23
24
TXE3-
PCH_EDP_PWM 21
<17> PCH_EDP_PWM PWMIN EDID_CLK
Vendor advise reserve it 1 2
2
12
TESTMODE
DP_REXT
MIICSCL1
MIICSDA1
46
45 EDID_DATA
EDID_CLK <42>
EDID_DATA <42>

OTHERS
RV9 12K_0402_1%
20 TL_ENVDD
LVDS@ PANEL_VCC TL_ENVDD <42,43>
@ 19 TL_INVT_PWM
RV14 MIIC_SCL 48 PWMOUT TL_BKOFF#_R TL_INVT_PWM <42>
1 2 0_0402_5% 44
ENBKL <42,43> MIIC_SDA 47 MIICSCL0 BL_EN
MIICSDA0

LVDS@ CSCL 1 RV11 2 0_0402_5% CIICSCL 13 6


TL_BKOFF#_R RV12 CSDA CIICSDA CIICSCL1 DP_GND
1 2 0_0402_5% 1 RV20 2 0_0402_5% 14
CIICSDA1
LVDS@
TL_INVT_BL <42>

GND
LVDS@ 16 1 2
CV284 GND RV15 0_0402_5%
LVDS@
+3VS_RT 0.1U_0402_16V7K 49
+DVCC33 PAD
1 2
LVDS@ RTD2136S-VE-CG_QFN48_6X6
5

+3VS_RT

2
2
P

B RV50
4
Y
1

<42,43> BKOFF# 1
A 4.7K_0402_5% EEPROM
G

UV25 LVDS@ RV16 LVDS@


3

1
B MC74VHC1G08DFT2G SC70 5P 100K_0402_5% MIIC_SCL +DVCC33 B
LVDS@
2

2
CPU_EDP_AUX#_C

2
CPU_EDP_AUX_C RV18
4.7K_0402_5% ROMLESS RV45
LVDS@ 4.7K_0402_5%
1

LVDS@

1
+3VS_RT

1
RV19 MIIC_SDA
100K_0402_5%
LVDS@
2

+DVCC33
Pull-Low 100K
2

2
LVDS@
EDID_DATA RV52 1 2 4.7K_0402_5% RV46
CSDA 1 6 EC_SMB_DA2 AUX termination LVDS@ 4.7K_0402_5%
EC_SMB_DA2 <19,43,53,54>
EDID_CLK RV21 1 2 4.7K_0402_5% @

1
QV2A
5

DMN66D0LDW-7_SOT363-6~D TL_BKOFF#_R

1
CSCL 4 3 EC_SMB_CK2
EC_SMB_CK2 <19,43,53,54>
LVDS@ CSCL RV47 1 LVDS@ 2 4.7K_0402_5% RV22 LVDS@
QV2B 100K_0402_5%
DMN66D0LDW-7_SOT363-6~D CSDA RV51 1 LVDS@ 2 4.7K_0402_5%

2
LVDS@

A A

Security Classification Compal Secret Data


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Translator RTD2136S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 37 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn
STDP6038 SW STDP4028 PCH/GPU AUX for LVDS

D UV26 D

16 EDP_DETECT#
SLE1 EDP_DETECT# <21>

LVDS_A0# 2 5 LVDS_MUX_TXOUT0-
<40> LVDS_A0# LVDS_A0 0B1 A0 LVDS_MUX_TXOUT0+ LVDS_MUX_TXOUT0- <42>
<40> LVDS_A0 1 6
1B1 A1 LVDS_MUX_TXOUT0+ <42>
LVDS_MXM_TXOUT0- 80
<29> LVDS_MXM_TXOUT0- 0B2
LVDS_MXM_TXOUT0+ 79
<29> LVDS_MXM_TXOUT0+ 1B2
LVDS_A1# 78 8 LVDS_MUX_TXOUT1-
<40> LVDS_A1# LVDS_A1 2B1 A2 LVDS_MUX_TXOUT1+ LVDS_MUX_TXOUT1- <42>
<40> LVDS_A1 77 3B1 A3 9
LVDS_MUX_TXOUT1+ <42>
LVDS_MXM_TXOUT1- 76
<29> LVDS_MXM_TXOUT1- LVDS_MXM_TXOUT1+ 2B2
<29> LVDS_MXM_TXOUT1+ 75 3B2
LVDS_A2# 73 11 LVDS_MUX_TXOUT2-
<40> LVDS_A2# 4B1 A4 LVDS_MUX_TXOUT2- <42>
LVDS_A2 72 12 LVDS_MUX_TXOUT2+
<40> LVDS_A2 5B1 A5 LVDS_MUX_TXOUT2+ <42>
LVDS_MXM_TXOUT2- 71
<29> LVDS_MXM_TXOUT2- LVDS_MXM_TXOUT2+ 4B2
<29> LVDS_MXM_TXOUT2+ 70 5B2
LVDS_ACLK# 68 14 LVDS_MUX_TXCLK-
<40> LVDS_ACLK# LVDS_ACLK 6B1 A6 LVDS_MUX_TXCLK+ LVDS_MUX_TXCLK- <42>
<40> LVDS_ACLK 67 7B1 A7 15
LVDS_MUX_TXCLK+ <42>
LVDS_MXM_TXCLK- 66
<29> LVDS_MXM_TXCLK- LVDS_MXM_TXCLK+ 6B2
<29> LVDS_MXM_TXCLK+ 65 7B2
64 8B1 A8 17
63 9B1 A9 18
RTD2136
C
Input 62 8B2 Output C

DGPU_MXM 61 9B2
34 EDP_DETECT#
SEL2

LVDS_B0# 60 23 LVDS_MUX_TZOUT0-
<40> LVDS_B0# 10B1 A10 LVDS_MUX_TZOUT0- <42>
LVDS_B0 59 24 LVDS_MUX_TZOUT0+
<40> LVDS_B0 11B1 A11 LVDS_MUX_TZOUT0+ <42>
LVDS_MXM_TZOUT0- 58
<29> LVDS_MXM_TZOUT0- LVDS_MXM_TZOUT0+ 10B2
<29> LVDS_MXM_TZOUT0+ 57
11B2
LVDS_B1# 56 26 LVDS_MUX_TZOUT1-
<40> LVDS_B1# 12B1 A12 LVDS_MUX_TZOUT1- <42>
LVDS_B1 55 27 LVDS_MUX_TZOUT1+
<40> LVDS_B1 13B1 A13 LVDS_MUX_TZOUT1+ <42>
LVDS_MXM_TZOUT1- 54
<29> LVDS_MXM_TZOUT1- LVDS_MXM_TZOUT1+ 12B2
<29> LVDS_MXM_TZOUT1+ 53
13B2
LVDS_B2# 51 29 LVDS_MUX_TZOUT2-
<40> LVDS_B2# LVDS_B2 14B1 A14 LVDS_MUX_TZOUT2+ LVDS_MUX_TZOUT2- <42>
<40> LVDS_B2 50 30
15B1 A15 LVDS_MUX_TZOUT2+ <42>
LVDS_MXM_TZOUT2- 49
<29> LVDS_MXM_TZOUT2- 14B2
LVDS_MXM_TZOUT2+ 48
<29> LVDS_MXM_TZOUT2+ 15B2
LVDS_BCLK# 46 32 LVDS_MUX_TZCLK-
<40> LVDS_BCLK# LVDS_BCLK 16B1 A16 LVDS_MUX_TZCLK+ LVDS_MUX_TZCLK- <42>
<40> LVDS_BCLK 45 33
17B1 A17 LVDS_MUX_TZCLK+ <42>
LVDS_MXM_TZCLK- 44
<29> LVDS_MXM_TZCLK- LVDS_MXM_TZCLK+ 16B2
<29> LVDS_MXM_TZCLK+ 43
17B2
42 35
18B1 A18
41 36
B 19B1 A19 B
40 +3VS
18B2
39
19B2
+3VS
3 4
GND1 VDD1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D
13 10
GND2 VDD2
1

<33,34,42> LCDVDD_ON 20 19 1 1 1
GND3 VDD3

CV285

CV286

CV287
RV370 21 22
GND4 VDD4
2 100K_0402_5%~D 31 28
GND5 VDD5
G

38 37
GND6 VDD6 2 2 2
52 47
2

GND7 VDD7
74 69
GND8 VDD8
S

3 1 25
OE2#
7
OE1#

QV24
SSM3K7002F_SC59-3~D PI3LVD1012BE_BQSOP80

SEL Y
L RTD2136
H DGPU_MXM

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS SW- 1 to 2 & GPU/PCH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 38 of 61
5 4 3 2 1
5 4 3 2 1

+3VS

LCD Backlight Selector PCH/GPU MUX & 6038 MUX SW for LVDS

1
www.laptopblue.vn RV371 @
10K_0402_5%~D

UV27

2
DGPU_SELECT# @ RV372 1 2 0_0402_5%~D RV373
16 HDMI_IN_SELECT#_R 1 2
SLE1 HDMI_IN_SELECT# <33,43>
RV374 1 2 0_0402_5%~D HDMI_IN_PWM_SELECT#
<17> HDMI_IN_PWMSEL#
0_0402_5%~D DV14
+3VS

0.1U_0402_16V4Z~D
LVDS_MUX_TXOUT0- 2 5 TXOUT0- USB20_P12_CONN 1 6
+3VS <41> LVDS_MUX_TXOUT0- 0B1 A0 V I/O V I/O
LVDS_MUX_TXOUT0+ 1 6 TXOUT0+
<41> LVDS_MUX_TXOUT0+ 1B1 A1
2 5 +5VS
D LVDS_TXOUT0- Ground V BUS D
1 <34> LVDS_TXOUT0- 80
0B2

1
LVDS_TXOUT0+ 79 USB20_N12_CONN 3 4
<34> LVDS_TXOUT0+ 1B2 V I/O V I/O

CV288
@ RV375 1 2 0_0402_5%~D @ RV376
<43> EC_INV_PWM
UV28 10K_0402_5%~D LVDS_MUX_TXOUT1- 78 8 TXOUT1- IP4223CZ6_SO6~D
2 <41> LVDS_MUX_TXOUT1- 2B1 A2
0_0402_5%~D 6 16 LVDS_MUX_TXOUT1+ 77 9 TXOUT1+
1B1 VCC <41> LVDS_MUX_TXOUT1+ 3B1 A3
RV377 1 2 VGA_EC_PWM 5
<29> VGA_PNL_PWM

2
HDMI_IN_PWM 1B2 HDMI_IN_PWM_SELECT# LVDS_TXOUT1-
<37> HDMI_IN_PWM 4 14 <34> LVDS_TXOUT1- 76
TL_INVT_PWM 1B3 S0 LVDS_TXOUT1+ 2B2 +3VS +3VS_CAM
<40> TL_INVT_PWM 3 2 DGPU_BKL_PWM_SEL# <21> <34> LVDS_TXOUT1+ 75
1B4 S1 3B2 QV25
RV400 1 @ 2 0_0402_5%~D 10 7 INV_PWM LVDS_MUX_TXOUT2- 73 11 TXOUT2- SI2301CDS-T1-GE3_SOT23-3~D
<43> EC_INV_PWM 2B1 1A INV_PWM <33> <41> LVDS_MUX_TXOUT2- 4B1 A4
11 9 ENBKL LVDS_MUX_TXOUT2+ 72 12 TXOUT2+
<29> DGPU_BKL_EN 2B2 2A ENBKL <40,43> <41> LVDS_MUX_TXOUT2+ 5B1 A5

D
<37> HDMI_IN_BKL_EN 12 3 1
2B3

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
13 15 LVDS_TXOUT2- 71
<40> TL_INVT_BL 2B4 2OE <34> LVDS_TXOUT2- 4B2

100K_0402_5%~D

100K_0402_5%~D

100K_0402_5%~D

10U_0805_10V4Z~D
LVDS_TXOUT2+ 70
<34> LVDS_TXOUT2+ 5B2

G
1 8 2 2 1

2
1OE GND

RV379

RV380

CV289

RV381

CV290

CV291
1 2 LVDS_MUX_TXCLK- 68 14 TXCLK-
<17,43> SG_AMD_BKL <41> LVDS_MUX_TXCLK- 6B1 A6
RV378 0_0402_5%~D SN74CB3Q3253PWR_TSSOP16 LVDS_MUX_TXCLK+ 67 15 TXCLK+
<41> LVDS_MUX_TXCLK+ 7B1 A7
LVDS_TXCLK- 66 1 1 2
<34> LVDS_TXCLK-

2
LVDS_TXCLK+ 6B2
<34> LVDS_TXCLK+ 65
7B2
S1 S0 1A 2A Y
64 17
8B1 A8

SSM3K7002F_SC59-3~D
0 0
63
9B1 A9
18 Output D
1
1B1 2B1 HDMI IN (D) CPU/MXM(MUX) Input 62
8B2

QV26
0 1 1B2 2B2 DSC HDMI IN(1:2) 61
9B2 <43> EN_CAM 2
G
1 0 1B3 2B3 HDMI IN (I) 34 HDMI_IN_SELECT#_R
SEL2 S
1 1 1B4 2B4 UMA LCD DDC Selector <41> LVDS_MUX_TZOUT0-
LVDS_MUX_TZOUT0-
LVDS_MUX_TZOUT0+
60
10B1 A10
23 TZOUT0-
TZOUT0+
3

EN_CAM control circuit


<41> LVDS_MUX_TZOUT0+ 59 24
C @ RV382 11B1 A11 C
0_0402_5%~D LVDS_TZOUT0- 58 +LCDVDD
<34> LVDS_TZOUT0- 10B2 +3VS
DGPU_SELECT# 1 2 LVDS_TZOUT0+ 57
+3VS <34> LVDS_TZOUT0+ 11B2

0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D

LVDS_MUX_TZOUT1- 56 26 TZOUT1- 1
<41> LVDS_MUX_TZOUT1- 12B1 A12

CV292

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D
RV383 LVDS_MUX_TZOUT1+ 55 27 TZOUT1+
<41> LVDS_MUX_TZOUT1+ 13B1 A13
0_0402_5%~D 1 1 1
SEL Y
CV293

CV294

CV295
1 2 DGPU_EDIDSEL_R# LVDS_TZOUT1- 54
<21,32,36> DGPU_EDIDSEL# <34> LVDS_TZOUT1- 12B2 2
LVDS_TZOUT1+ 53
<34> LVDS_TZOUT1+ 13B2 L B1
UV29 2 LVDS_MUX_TZOUT2- 51 29 TZOUT2- 2 2
6 16
<41> LVDS_MUX_TZOUT2-
<41> LVDS_MUX_TZOUT2+
LVDS_MUX_TZOUT2+ 50
14B1 A14
30 TZOUT2+ H B2
VGA_LCD_CLK 1B1 VCC 15B1 A15
<29> VGA_LCD_CLK 5
1B2 Close to JLVDS1
DHMI_IN_NV_CLK 4 14 HDMI_IN_SELECT# LVDS_TZOUT2- 49
<37> DHMI_IN_NV_CLK 1B3 S0 <34> LVDS_TZOUT2- 14B2
EDID_CLK 3 2 DGPU_EDIDSEL_R# LVDS_TZOUT2+ 48
<40> EDID_CLK 1B4 S1 <34> LVDS_TZOUT2+ 15B2
10 7 I2CC_SCL LVDS_MUX_TZCLK- 46 32 TZCLK- BKOFF# 1 @ 2 DISPOFF#
2B1 1A <41> LVDS_MUX_TZCLK- 16B1 A16 <40,43> BKOFF#
VGA_LCD_DAT 11 9 I2CC_SDA LVDS_MUX_TZCLK+ 45 33 TZCLK+ RV384 0_0402_5%~D
<29> VGA_LCD_DAT
<37> DHMI_IN_NV_DAT
<40> EDID_DATA
DHMI_IN_NV_DAT
EDID_DATA
12
13
2B2
2B3
2B4 2OE
2A
15
<41> LVDS_MUX_TZCLK+

<34> LVDS_TZCLK-
LVDS_TZCLK- 44
17B1

16B2
A17
LVDS Conn.
LVDS_TZCLK+ 43 JLVDS1
<34> LVDS_TZCLK+ 17B2
1 8 55 44 TXOUT0-
1OE GND GND11 44 TXOUT0+
42 35 54 43
SN74CB3Q3253PWR_TSSOP16 18B1 A18 GND10 43
41 36 53 42
19B1 A19 GND9 42 TXOUT1-
52 41
GND8 41 TXOUT1+
S1 S0 1A 2A Y 40
18B2 +3VS
51
GND7 40
40
39 50 39
19B2 GND6 39 TXOUT2-
49 38
+3VS GND5 38 TXOUT2+
0 0 1B1 2B1 HDMI IN (D) 48
GND4 37
37
3 4 47 36
GND1 VDD1 GND3 36

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D
0 1 1B2 2B2 DSC 13 10 46 35 TXCLK-
GND2 VDD2 GND2 35

1
20 19 1 1 1 45 34 TXCLK+
GND3 VDD3 GND1 34

CV296

CV297
B RV385 B
1 0 1B3 2B3 HDMI IN (I) LCDVDD_ON 21 22 33

CV298
GND4 VDD4 33 1 1
2 100K_0402_5%~D 31 28 32 TZOUT0- @ @
GND5 VDD5 32
G

10P_0402_50V8J~D
CV318

10P_0402_50V8J~D
CV319
1 1 1B4 2B4 UMA 38
GND6 VDD6
37
2 2 2 31
31 TZOUT0+
52 47 30

2
GND7 VDD7 30 TZOUT1- 2 2
74 69 29
GND8 VDD8 29
S

3 1 25 28 TZOUT1+
OE2# 28
7 27
LCD POWER QV27
SSM3K7002F_SC59-3~D
OE1# 27
26
25
26
25
TZOUT2-
TZOUT2+
24
PI3LVD1012BE_BQSOP80 24 TZCLK-
23
23
+LCDVDD W=60mils +3VS
22
22 TZCLK+
+LCDVDD QV28 +3VS +3VS 21
21 1 1
+5VALW SI2301CDS-T1-GE3_SOT23-3~D 20 I2CC_SCL @ @
20

10P_0402_50V8J~D
CV320

10P_0402_50V8J~D
CV321
19 I2CC_SDA
19

1
DMIC_CLK
S

1 3 1 18
D

18 2 2
100_0603_5%~D

47K_0402_5%~D

CV299 @ RV386 1 17 USB20_N12_CONN


17
1

1
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D 10K_0402_5%~D @ 16 USB20_P12_CONN


4.7U_0805_10V4Z~D

1 16
RV388

RV387

10P_0402_50V8J~D
CV322
1 1 1 UV30 15
G
2

2 15
CV302

CV303

CV300

6 16 14 CAM_DET#
CV301

2
1B1 VCC 2 14 DMIC_CLK CAM_DET# <18,33>
5 13 DMIC_CLK <33,45>
2 1B2 HDMI_IN_SELECT# 13 DMIC0
4 14 12 DMIC0 <33,45>
2

2 2 2 1B3 S0 DGPU_SELECT# 12 DISPOFF#


3 2 DGPU_SELECT# <17,32,36> 11 DISPOFF# <33>
1B4 S1 11 INV_PWM
10
10
6

10 7 @ 9 LVDS_CAB_DET#
QV3A 2B1 1A RV389 9 LVDS_CAB_DET# <21>
<29> DGPU_ENVDD 11 9 LCDVDD_ON
LCDVDD_ON <33,34,41> 1 2 0_0402_5%~D 8 +3VS_CAM
2B2 2A 8
.047U_0402_16V7K~D

DMN66D0LDW-7_SOT363-6~D 12 7 LCD_TEST
RV390 <37> HDMI_IN_ENVDD 2B3 7 LCD_TEST <33,43>
2 2 1 13 15 LV33 6 +3VS
<40,43> TL_ENVDD 2B4 2OE 6
220K_0402_1% 1 USB20_P12 4 3 USB20_P12_CONN 5 +LCDVDD
<20> USB20_P12 4 3 5
CV304

1 8 4 W=60mils +INVPWR_B+
1

1OE GND 4
3

3 B+
SN74CB3Q3253PWR_TSSOP16 USB20_N12 USB20_N12_CONN 3 @ LV34
<20> USB20_N12 1 2 2
A QV3B 2 1 2 2 A
1 1 2
LCDVDD_ON 0_0402_5%~D 1
1 2 RV391 5 DMN66D0LDW-7_SOT363-6~D DLW21SN900SQ2L_0805_4P~D W=80mils FBMA-L11-201209-221LMA30T_0805
JAE_FI-TD44SB-E-R750~D
0_0402_5%~D 1 2 RV393
@ RV392 1 2 0_0402_5%~D CONN@
<33,43> EC_ENVDD
4

S1 S0 1A 2A Y
DELL CONFIDENTIAL/PROPRIETARY
100K_0402_5%~D

@
1
RV394

0 0 1B1 2B1 HDMI IN Compal Electronics, Inc.


0 1 1B2 2B2 DSC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, Title
TRADE SECRET, AND OTHER PROPRIETARY INFORMATION
LVDS SW- 6038/SYSTEM & CONN
2

1 0 1B3 2B3 HDMI IN OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN
AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS Size Document Number Rev
1 1 1B4 2B4 UMA SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT 0.1
DELL'S EXPRESS WRITTEN CONSENT. LA-9331P
Date: Friday, June 22, 2012 Sheet 39 of 61
5 4 3 2 1
5 4 3 2 1

+3VS +3VALW
@
www.laptopblue.vn
LE3
FBMA-L11-160808-800LMT_0603
EC_ESB_CLK
TP_CLK 4.7K_0402_5%~D 2 1 RE35
+5VS

2
RE36 1 2 10K_0402_5%~D BKOFF# 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K +3VALW_EC 1 2 +EC_VCCA
RE38 1 2 10K_0402_5%~D EC_SCI# RE37 0_0805_1%
1 1 1 1 2 2 @ RE40 TP_DATA 4.7K_0402_5%~D 2 1 RE41

2
RE42 1 2 10K_0402_5%~D M_THERMAL# CE35 CE31 CE32 CE34 CE37 CE36 1 33_0402_5%~D

22P_0402_50V8J~D
KB930@
RE43 1 2 2.2K_0402_5%~D EC_SMB_CK2 RE44 0.1U_0402_16V7K
RE45 1 2 2.2K_0402_5%~D EC_SMB_DA2 1000P_0402_50V7K 0_0402_5% CE33

1
2 2 2 2 1 1

@
ECAGND 1
+3VALW_EC 2

CE39
0.1U_0402_16V7K 0.1U_0402_16V7K 1000P_0402_50V7K

1
@
RE46 1 2 2.2K_0402_5%~D EC_SMB_CK1 1 2 +3VLP
RE48 1 2 2.2K_0402_5%~D EC_SMB_DA1 RE47 0_0402_1% 2
D D
RE49 1 2 47K_0402_5%~D KSO1 Reserve for EMI

111
125
RE50 1 2 47K_0402_5%~D KSO2 +3VALW_EC +3VALW_EC Reserved for KB9012

22
33
96

67
UE1 please close to UE2

9
RE51 1 2 10K_0402_5%~D EC_MUTE#

47K_0402_5%~D

47K_0402_5%~D
@ RE52 1 2 1K_0402_1%~D EC_SMI#

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
2

1
RE53 1 2 100K_0402_5%~D DEPOP#
RE54 4.7K_0402_5%~D EC_ESB_CLK

RE55
1 2

RE56
RE57 1 2 4.7K_0402_5%~D EC_ESB_DAT
RE58 1 2 10K_0402_5%~D LID_SW_IN# <21> GATEA20 GATEA20 1 21 EN_TPLED# EN_TPLED# <48>
RE59 10K_0402_5%~D EN_WOL# KB_RST# GATEA20/GPIO00 GPIO0F BEEP#
2 1 <21> KB_RST# 2 23 BEEP# <45>

2
@ RE60 10K_0402_5%~D EAPD#_R SERIRQ KBRST#/GPIO01 BEEP#/GPIO10 SYSTEM_FAN_PWM
1 2 <19> SERIRQ 3 26 SYSTEM_FAN_PWM <54>
EC_RST# RST# LPC_FRAME# SERIRQ GPIO12 MXM1_FAN_PWM
<19,51> LPC_FRAME# 4 27 MXM1_FAN_PWM <53>
LPC_AD3 LPC_FRAME# ACOFF/GPIO13 ECAGND
<19,51> LPC_AD3 5 2 1 ECAGND <57>
LPC_AD3

0.1U_0402_16V4Z~D

.1U_0402_16V7K~D
LPC_AD2 7 PWM Output CE42 100P_0402_50V8J~D
EC_ESB_CLK <19,51> LPC_AD2 LPC_AD2
1 2 EC_ESB_CLK_R 1 2 <19,51> LPC_AD1
LPC_AD1 8
LPC_AD1 BATT_TEMP/AD0/GPIO38
63 BATT_TEMP
BATT_TEMP <57,63>
RE62

CE43
RE61 0_0402_5%~D LPC_AD0 10 LPC & MISC 64 EAPD#_R RE63 2 @ 1 0_0402_5%~D 0_0402_5%~D
<19,51> LPC_AD0 LPC_AD0 AD1/GPIO39 PM_SLP_SUS# <17>

CE44
65 ADP_I RE64 2 1 0_0402_5%~D 1 2 DEPOP# DEPOP# <45>
KSI[0..7] ADP_I/AD2/GPIO3A ADP_I <57,63> EAPD# <45>
CLK_PCI_LPC 12 AD Input 66 AD_BID0
<53> KSI[0..7] 2 1 <18> CLK_PCI_LPC CLK_PCI_EC AD3/GPIO3B
PLT_RST# 13 75 USBCHG_DET_EC# 1
KSO[0..17] <6,17,44,51,53> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 ENBKL D
<53> KSO[0..17] 37 76 ENBKL <40,42>
EC_SCI# EC_RST# IMON/AD5/GPIO43
<21> EC_SCI# 20
ACOFF EC_SCII#/GPIO0E DEPOP#_EC
<63> ACOFF 38 2
GPIO1D G

10K_0402_5%~D
68 RE68 2 1 0_0402_5%~D ODD_EJECT# <50> @ QE21
DAC_BRIG/GPIO3C

2
DA Output 70 M_THERMAL# M_THERMAL# <12,13,14,15> S SSM3K7002F_SC59-3~D
KSI0_EC EN_DFAN1/GPIO3D EC_ENVDD @ 3
55 71 EC_ENVDD <33,42>
KSI0/GPIO30 IREF/GPIO3E

RE65
KSI1_EC 56 72 LCD_TEST LCD_TEST <33,42>
CLK_PCI_LPC KSI2_EC KSI1/GPIO31 CHGVADJ/GPIO3F
57
KSI3_EC KSI2/GPIO32 EC_MUTE#
58 83 EC_MUTE# <45>

1
KSI4_EC KSI3/GPIO33 EC_MUTE#/GPIO4A IMVP_PWRGD
59 84 IMVP_PWRGD <6,17,62>
KSI4/GPIO34 USB_EN#/GPIO4B

1
RP1 RP2 KSI5_EC 60 85 LCD_BKL_EN LCD_BKL_EN <33>
KSI0 KSI0_EC KSO4 KSO4_EC RE66 @ KSI6_EC KSI5/GPIO35 CAP_INT#/GPIO4C EC_LID_OUT#
1 8 1 8 61
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
86 EC_LID_OUT# <19>
KSI1 2 7 KSI1_EC KSO5 2 7 KSO5_EC 33_0402_5%~D KSI7_EC 62 87 TP_CLK TP_CLK <53>
KSI2 KSI2_EC KSO6 KSO6_EC KSO0_EC KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA
3 6 3 6 39 88 TP_DATA <53>
KSI3 KSI3_EC KSO7 KSO7_EC KSO1_EC KSO0/GPIO20 TP_DATA/GPIO4F
4 5 4 5 40
Board ID
2
KSO2_EC KSO1/GPIO21
41
KSO2/GPIO22
22P_0402_50V8J~D
0_0804_8P4R_5% 0_0804_8P4R_5% 1 KSO3_EC 42 97 CPU1.5V_S3_GATE CPU1.5V_S3_GATE <10>
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 +3VALW_EC
@
KSO4_EC 43 98 EN_WOL#
KSO4/GPIO24 WOL_EN/GPXIOA01 EN_WOL# <44>
CE45

KSO5_EC HDA_SDO
KSO5/GPIO25 Int. K/B
44 99 HDA_SDO <16>
RP3 RP4 KSO6_EC ME_EN/GPXIOA02 VCIN0_PH
45 109
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <57>

2
KSI4 KSI4_EC KSO8 8 KSO8_EC 2 KSO7_EC
C 1 8 1 46
KSO7/GPIO27 SPI Device Interface C
KSI5 2 7 KSI5_EC KSO9 2 7 KSO9_EC Reserve for KSO8_EC 47
KSI6 KSI6_EC KSO10 KSO8/GPIO28
3 6 3 6 KSO10_EC KSO9_EC 48 119 PWRSHARE_EN_EC# PWRSHARE_EN_EC# <52> RE67
KSI7 KSI7_EC KSO11 EMI please KSO9/GPIO29 SPIDI/GPIO5B
4 5 4 5 KSO11_EC KSO10_EC 49
KSO10/GPIO2A SPIDO/GPIO5C
120 PWRSHARE_OE#
PWRSHARE_OE# <52> Ra 100K_0402_5%~D
KSO11_EC 50 SPI Flash ROM 126 VPK_EN
close to UE1

1
KSO11/GPIO2B SPICLK/GPIO58 VPK_EN <53>
0_0804_8P4R_5% 0_0804_8P4R_5% KSO12_EC 51 128 3V_F347_ON 3V_F347_ON <47>
KSO13_EC KSO12/GPIO2C SPICS#/GPIO5A AD_BID0
52
KSO14_EC KSO13/GPIO2D
53
KSO14/GPIO2E

2
RP5 RP6 KSO15_EC 54 73 KB_DET#_EC RE114 1 2 0_0402_5%~D 1
KSO0 1 KSO15/GPIO2F ENBKL/AD6/GPIO40 KB_DET# <53>
8 KSO0_EC KSO12 1 8 KSO12_EC KSO16_EC 81 74 PCIE_WAKE#_EC RE82 1 2 0_0402_5%~D PCIE_WAKE# <17,44,51>
RE70 CE46
KSO1 2 KSO16/GPIO48 PECI_KB930/AD7/GPIO41
7 KSO1_EC KSO13 2 7 KSO13_EC KSO17_EC 82 89 PCH_DPWROK
PCH_DPWROK <17> Rb 0_0402_5% 0.1U_0402_16V4Z~D
KSO2 3 KSO17/GPIO49 FSTCHG/GPIO50
6 KSO2_EC KSO14 3 6 KSO14_EC BATT_CHG_LED#/GPIO52
90 BATT_CHG_LED# BATT_CHG_LED# <47>
KSO3 4 5 KSO3_EC KSO15 4 5 KSO15_EC 91 CAPS_LED# 2
CAPS_LED# <53>

1
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED#
<29> EC_SMB_CK1 77
EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54
92 PWR_LED#
0_0804_8P4R_5% 0_0804_8P4R_5% EC_SMB_DA1 78 93 BATT_LOW_LED# BATT_LOW_LED# <47>
<29> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55
RE75 1 2 0_0402_5%~D EC_SMB_CK2 79 SM Bus 95 SYSON SYSON <56,59,60>
<37> EC_SMB_CK2_R EC_SMB_CK2/GPIO46 SYSON/GPIO56
RE76 1 2 0_0402_5%~D EC_SMB_DA2 80 121 IMVP_VR_ON IMVP_VR_ON <62>
<37> EC_SMB_DA2_R EC_SMB_DA2/GPIO47 VR_ON/GPIO57
<19,40,53,54> EC_SMB_CK2 127 PM_SLP_S4#_R RE81 1 2 0_0402_5%~D
PM_SLP_S4#/GPIO59 PM_SLP_S4# <17>
<19,40,53,54> EC_SMB_DA2
2 0_0402_5%~D PM_SLP_S3#_R
RE77 1 6 100 PCH_RSMRST# PCH_RSMRST# <17>
BOARD ID Table
<17,47> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03
KSO16 RE115 1 2 0_0402_5%~D KSO16_EC 2 0_0402_5%~D PM_SLP_S5#_R
RE78 1 14 101 Board PCB
<17,47> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04
KSO17 RE116 1 2 0_0402_5%~D KSO17_EC EC_SMI# VCIN1_PH
<21> EC_SMI# PS_ID
15
16
EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05
102
103 H_PROCHOT#_EC
VCIN1_PH <57> ID Revision Rb
<57> PS_ID EC_ESB_CLK_R GPIO0A H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH#
EC_ESB_DAT
17
18
GPIO0B VCOUT0_PH/GPXIOA07
GPO BKOFF#/GPXIOA08
104
105 BKOFF#
VCOUT0_PH# <58>
* 0 0.1 (SSI) 0
GPIO0C BKOFF# <40,42>
SUSPWRDNACK GPIO PBTN_OUT#
<17> SUSPWRDNACK 19
25
GPIO0D PBTN_OUT#/GPXIOA09
106
107 PCH_PWR_EN
PBTN_OUT# <6,17> 1 0.2 (PT) 8.2K +/- 5%
EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <35,56>
SYSTEM_FAN_FB VPK_DET#
<54> SYSTEM_FAN_FB MXM1_FAN_FB
28
29
FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
108 VPK_DET# <53> 2 0.3 (ST) 18K +/- 5%
<53> MXM1_FAN_FB EC_PME#/GPIO15
<50> E51TXD_P80DATA
E51TXD_P80DATA 30 CE47 2 1100P_0402_50V8J~D 3 0.4 (QT) 33K +/- 5%
E51RXD_P80CLK EC_TX/GPIO16 ACIN
<50> E51RXD_P80CLK 31 110 ACIN <17,29,47,57,63>
PCH_PWROK EC_RX/GPIO17 AC_IN/GPXIOD01 EC_ON
<17> PCH_PWROK
WLES ON/OFF LED#
32
34
PCH_PWROK/GPIO18 EC_ON/GPXIOD02
112
114 ON/OFF
EC_ON <58> 4 1.0 (MP) 56K +/- 5%
<53> WLES ON/OFF LED# SG_AMD_BKL SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW_IN# ON/OFF <55>
<17,42> SG_AMD_BKL 36
NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 115 LID_SW_IN# <19,47,48,53> 5 100K +/- 5%
116 SUSP# SUSP# <10,56,59,61>
SUSP#/GPXIOD05 USB_PWR_EN#
GPXIOD06
117
118 EC_PECI RE74 1
USB_PWR_EN# <52,53>
2 43_0402_1%
6
PECI_KB9012/GPXIOD07 H_PECI <6,21>

AGND/AGND
FB_CLAMP_TGL_REQ# 122
<29> FB_CLAMP_TGL_REQ#
FB_CLAMP 123
XCLKI/GPIO5D +V18R
Please place RE74 7
GND/GND
GND/GND
GND/GND
GND/GND

<29> FB_CLAMP 124


B XCLKO/GPIO5E V18R close to EC with in 750mil B

4.7U_0805_10V4Z~D
1
GND0

2 1

CE48
CE51 47P_0402_50V8J~D
2 @
PCH_PWR_EN H_PROCHOT#_EC need add
11
24
35
94
113

69

20mil
1 2 TH_OVERT#_EC
KB9012QF-A3_LQFP128_14X14 <29> TH_OVERT#
2 ECAGND

H_PROCHOT# 1 2 RE79 0_0402_5%~D


<6,63> H_PROCHOT# VR_HOT# <62>
RE80 0_0402_5%~D

1
D
RE89 10K_0402_5%~D
2 H_PROCHOT#_EC 1 2 PCH_PWROK LE44 UE2
G FBMA-L11-160808-800LMT_0603 EC_ESB_CLK 1 13
SSM3K7002F_SC59-3~D ESB_CLK TEST_EN#
S <37> HDMI_TOGGLE HDMI_TOGGLE 2 14 HDMI_IN_OUT_HPD
1

3 GPIO00 GPIO08/CAS_DAT HDMI_IN_OUT_HPD <35>


QE22
RST# 3 15 HDMI_SW
RST# GPIO09 HDMI_SW <35>
EC_ESB_DAT 4 16 HDMI_OUT_EN
ESB_DAT GPIO0A HDMI_OUT_EN <35>
DEPOP#_EC 5 17 TL_ENVDD
GPIO01 GPIO0B TL_ENVDD <40,42>

<33,42> HDMI_IN_SELECT# HDMI_IN_SELECT# 6 18 EC_INV_PWM EC_INV_PWM <42>


GPIO02 GPIO0C/PWM0
<37> HDMI_IN_CAB_DET# HDMI_IN_CAB_DET#7 19 HDMI_IN_EN HDMI_IN_EN <37>
DE83 RE85 10K_0402_5%~D GPIO03 GPIO0D/PWM1
BAT54CW_SOT323-3 1 2 +3VALW_EC DGPU_PWR_EN 8 20 TH_OVERT#_EC
<29,56> DGPU_PWR_EN GPIO04 GPIO0E/PWM2
3 USBCHG_DET_EC# DGPU_PWROK 9 21 DP_MXM_CARD_SEL DP_MXM_CARD_SEL <30,32>
<29,30> DGPU_PWROK GPIO05 GPIO0F/PWM3
1 <17> DGPU_HOLD_RST# DGPU_HOLD_RST#10 22 EC_AC_BAT# EC_AC_BAT# <29>
<52> USBCHG_DET# VL +3VLP GPIO06 GPIO10/ESB_RUN#
2 HDMI_IN_OUT_DDC11 23 EN_CAM EN_CAM <42>
<35> HDMI_IN_OUT_DDC GPIO07/CAS_CLK GPIO11/BaseAddOpt
2

12 24

GND
GND VCC +3VALW_EC
RE86

0.1U_0402_16V4Z~D
1

100K_0402_5%~D 1 60 mil

CE50
A RE87 KC3810_QFN24_4X4 A

25
100K_0402_5%~D
1

USBCHG_DET_D <58> 2
2

D
USBCHG_DET_PWR_EN# 2 QE321
G SSM3K7002FU_SC70-3~D
S
3
2

RE88
150K_0402_1%~D
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9012QF,KC3810
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 40 of 61
5 4 3 2 1
5 4 3 2 1

UL1

PCIE_PRX_GLANTX_P1_C
W=40mils
2 1 30 1 +LAN_IO
<20> PCIE_PRX_GLANTX_P1 CL1 0.1U_0402_16V7K~D TX_P VDD33
16

www.laptopblue.vn
PCIE_PRX_GLANTX_N1_C AVDD33
2 1 29
+LAN_IO <20> PCIE_PRX_GLANTX_N1 CL4 0.1U_0402_16V7K~D TX_N
PCIE_PTX_GLANRX_P1 35 13 +AVDDL
<20> PCIE_PTX_GLANRX_P1 RX_P AVDDL

1
19
RL7 PCIE_PTX_GLANRX_N1 AVDDL
<20> PCIE_PTX_GLANRX_N1 36 31
0_0402_5%~D RX_N AVDDL
34
CLK_PCIE_LAN AVDDL
<18> CLK_PCIE_LAN 33 6
REFCLK_P AVDDL_REG

2
CLK_PCIE_LAN# 32
<18> CLK_PCIE_LAN# REFCLK_N
22 +AVDDH
CLKREQ_LAN#_R AVDDH
2 1 4 9
<18> LANCLK_REQ# RL12 0_0402_5%~D CLKREQ# AVDDH_REG
4.7K_0402_5%~D 2 1 PLT_RST# PLT_RST# 2
<6,17,43,51,53> PLT_RST# PERST#
RL10 37 +DVDDL
D
4.7K_0402_5%~D PCIE_WAKE# PCIE_WAKE# DVDDL_REG D
2 1 3
RL11 <17,43,51> PCIE_WAKE# WAKE#
4.7K_0402_5%~D 2 1 CLKREQ_LAN#_R 11 LAN_MDIP0 LAN_MDIP0 <53>
RL15 TRXP0 LAN_MDIN0
25 12 LAN_MDIN0 <53>
SMCLK TRXN0 LAN_MDIP1
26 14 LAN_MDIP1 <53>
SMDATA TRXP1 LAN_MDIN1
The pull-up resisters might not be 28
TRXN1
15
17 LAN_MDIP2
LAN_MDIN1 <53>
NC TRXP2 LAN_MDIP2 <53>
necessory due to existence 27
TESTMODE TRXN2
18 LAN_MDIN2
LAN_MDIP3
LAN_MDIN2 <53>
41 20 LAN_MDIP3 <53>
on PCH side. GND TRXP3
TRXN3
21 LAN_MDIN3 LAN_MDIN3 <53>
XTLI 8
XTLO XTLI
7
XTLO
40
LX

25MHZ_10PF_7V25000014
+LAN_IO 1 2 5
RL13 30K_0402_5% ISOLAT#
24
PPS

4
1
LAN_ACTIVITY# 38 10 +RBIAS 1 RL14 2

0_0402_5%

GND

GND
<53> LAN_ACTIVITY# LAN_LINK#_R LED_0 RBIAS 2.37K_0402_1%~D
39
RL28 <53> LAN_LINK#_R LAN_LED2#_R LED_1
23
<53> LAN_LED2#_R LED_2

OSC

OSC
2
YL1 LAN_LINK#_R E2201-BL3A-R_QFN40_5X5

2
15P_0402_50V8J~D

15P_0402_50V8J~D
2 2 RL29
5.1K_0402_1%~D
CL51 CL52

1
1 1

W=40mils
C W=40mils W=20mils W=20mils W=20mils C

+3VALW QL1
FDC655BN_NL_SSOT6~D
+LAN_IO
close to Lan pin31 close to Lan pin19
D

6 1A +AVDDL +AVDDH +DVDDL


S

1 5 4 +LAN_IO_R RL16 1 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
4.7U_0603_6.3V6K~D
CL20 2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
1000P_0402_50V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
1U_0402_6.3V6K~D 1 0_0805_5%~D 1 1 1 1 1 1 1 1 1 1 1 1 1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CL54
G

B+_BIAS 2 CL35 CL28 CL29 CL53 CL30 CL31 CL32 CL33 CL26 CL34 CL39 CL27
1 1 1 1 1 1 1
3

+3VALW
CL21 CL22 CL23 CL24 CL25 CL50 CL41 2 2 2 2 2 2 2 2 2 2 2 2 2
2

2 2 2 2 2 2 2
RL17
2

470K_0402_5%~D
RL18 close to Lan pin6 close to Lan pin34
10K_0402_5%~D close to Lan pin9 close to Lan pin22 close to Lan pin37
1

EN_WOL close to Pin 1 close to Pin 16 close to Lan pin13


1

D
1
1.5M_0402_5%~D

2 QL2
<43> EN_WOL#
G SSM3K7002FU_SC70-3 RL19 CL36
S 0.1U_0402_25V6
3

2
1

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GLAN AR8151 AL1A/ RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9331P
Date: Friday, June 22, 2012 Sheet 41 of 61
5 4 3 2 1
A B C D E F G H

+3V_DVDD
Close to Pin39 +3V_DVDD +3.3V_AVDD
+3VS +5VS
S1 (Out + In) : Front L/R + HP1 + MIC (auto-sense)
RA360

0.1U_0402_10V6K~D

4.7U_0805_25V6-K
1 2 2 LINE2-VREFO 2 1

1
www.laptopblue.vn
RA1 0_0805_5%~D RA2 1 2 0_0402_5%
CA2 CA1 RA3 1 2 0_0402_5% 2.2K_0402_5%~D
+3V_DVDD RA4 1 2 0_0402_5% JHP1

2
1 LA2 SLEEVE 6

10U_0805_10V4Z~D

0.1U_0402_10V6K~D
RA76 18_0402_5%~D 0_0603_5%~D RING2 1
HP1_A_L 1 2 HP1_A_L_L 1 2 HP1_A_L_C 2
CA3 CA4 1
1 2 3
CA61 100P_0402_50V8J~D HPOUT-JD 4
G 7
2 5 8
2 1 G
UA1
CA5 C-H_13-18200610CP
+3V_DVDD
0.1U_0402_10V6K~D

10U_0805_10V4Z~D
2 1 2 PC_BEEP HP1_A_R 1 2 HP1_A_R_L 1 2 1 HP1_A_R_C CONN@
+3V_DVDD LA1 PCBEEP
CA8 CA9 23 LA3
1 HVDD 1

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

4.7U_0805_25V6-K
2 1 39 RA77 18_0402_5%~D 0_0603_5%~D
LDO-IN 0.1U_0402_10V6K~D
2 1 46
CA10 CA11 CA12 LINE1-R CA60 2 100P_0402_50V8J~D
45
LINE1-L SLEEVE RA361
2 2 11 32
DVDD LINE2-IN-R/SLEEVE

1
7 31 RING2 LINE2-VREFO 2 1 DA6
1 2 DVDD-IO LINE2-IN-L/RING2 RING2
25 2
FBMA-L11-201209-221LMA30T_0805 DVDD-IO-CP 2.2K_0402_5%~D 1

2
1 1 UA2 3 HP1_A_L_C
CA13

22P_0402_50V8J~D
<16> PCH_AZ_CODEC_SDIN0 RA6 1 2 HDA_SDIN0_R 8
SDATA-IN MIC1-R
37
22_0402_5% 4 36 1 2 HP1_A_L_L RA5 1 2100_0402_1% A1 AZ5125-02S.R7G_SOT23-3
<16> PCH_AZ_CODEC_SDOUT SDATA-OUT MIC1-L/MIC-CAP INL
RA8 1 2 5 48 MIC2-R
<16> PCH_AZ_CODEC_BITCLK
<16> PCH_AZ_CODEC_SYNC 0_0402_5%
2
9
BCLK MIC2-R
47 MIC2-L HP1_A_R_L RA7 1 2100_0402_1% A3 Place close to Jack
CA15 SYNC MIC2-L 10U_0805_10V4Z~D INR +3.3V_AVDD DA8
<16> PCH_AZ_CODEC_RST# 6 B1
RESETB HP_MUTE# /MUTE HP1_A_R_C
2
1 RA9 1
RA11
1U_0402_6.3V6K~D

MIC2-VREFO-L 1 34 1 2 MIC_B_PLUG# B2 3 SLEEVE


LINE2-VREFO MIC2-VREFO SENSE A 39.2K_0402_1% HPOUT2-JD VDD
29 33 1 2 2 1 B3
MIC2-VREFO-R LINE2-VREFO SENSE B SET AZ5125-02S.R7G_SOT23-3
1 30

GND
MIC1-VREFO CA14
CA16 27 HP1_A_R 10K_0402_1% 0.1U_0402_16V4Z~D Place close to Jack
SURR-R HP1_A_L MAX9892ERT+T_UCSP6~D DA11
24 26

A2
2 CBP SURR-L HP2_D_L HPOUT-JD
21
CBN CEN
19 RA12 Setting the Turn-Off Time: 2
35 18 HP2_D_R 1
JDREF LFE HPOUT-JD
Ton (ms) = 0.02 x Cset (pF)
40 1 2 3
LDO-CAP
41
VREF
1
20K_0402_1%~D

RA14 1 2 38 44 INT-SPK-R <46> AZ5125-02S.R7G_SOT23-3


CA17 CA18 CA19 VRP FRONT-R 5.1K_0402_1%
43
2 1 FRONT-L INT-SPK-L <46> Place close to Jack
10U_0805_10V4Z~D

0.1U_0402_10V6K~D

2.2U_0402_6.3V6M~D

+ CA20
2 1 100U_B3_6.3VM_R55M 15
S2 (Out) :Center + HP2
2

1 SPDIF-OUT
20 CPVEE 16 I2S_DAT/SPDIF_IN <37>
2 SPDIF-in

100P_0402_50V8J~D
10 REGREF
10U_0805_10V4Z~D

CA22
1 JHP2
1U_0402_6.3V6K~D

1 CA23 12 DMIC_CLK <33,42> LA4 6


GPIO/DMIC-CLK RA78 18_0402_5%~D 0_0603_5%~D
28 13 DMIC0 <33,42> 1
CPVREF GPIO1/DMIC-DATA HP2_D_L 1 HP2_D_L_R HP2_D_L1_JK
22 17 2 1 2 1 2
2 AVSS1 GPIO2/Combo-Jack1 GPIO3
42 3
2 AVSS2 GPIO3/Combo-Jack2 CA63 3
49 HPOUT2-JD 4
Thermal PAD 2 G
2 14 EAPD# <43> 7 2
EAPD LA5 5 G 8
RA79 18_0402_5%~D 0_0603_5%~D
HP2_D_R 1 2 HP2_D_R_R 1 2 HP2_D_R1_JK C-H_13-18200610CP
ALC3661-CG_MQFN48_6X6~D CONN@

100P_0402_50V8J~D
1
CA62
2
CA68 1 2 0.1U_0402_16V7K
RA44 1 2 0_0402_5%~D CA69 1 2 0.1U_0402_16V7K
RA45 1 2 0_0402_5%~D CA70 1 2 0.1U_0402_16V7K DA7
RA47 1 2 0_0402_5%~D CA71 1 2 0.1U_0402_16V7K 2 HP2_D_L1_JK
RA48 1 2 0_0402_5%~D UA3 MAX9892ERT+T_UCSP6~D 1
3 HP2_D_R1_JK
HP2_D_L_R RA15 1 2 100_0402_1% A1
INL AZ5125-02S.R7G_SOT23-3
HP2_D_R_R RA16 1 2 100_0402_1% A3
GND AGND B1
INR +3.3V_AVDD
GND AGND HP_MUTE# /MUTE Place close to Jack
B2 DA12
VDD HPOUT2-JD
2 1 B3 2
SET
1

GND
CA25 3 MIC_B_PLUG#
0.1U_0402_16V4Z~D
AZ5125-02S.R7G_SOT23-3

A2
+3V_DVDD Setting the Turn-Off Time:
+3.3V_AVDD
Ton (ms) = 0.02 x Cset (pF)
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

10U_0603_6.3V6M~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

10U_0603_6.3V6M~D

RA362 @
1 1 1 1 1
S3 (Out) : Rear L/R MIC2-VREFO-L 2 1
CA27

CA28

CA29

CA30

CA31

1 1 1
CA59

CA37

CA35

DA9 RA802.2K_0402_5%~D JHP3


BAT54CW_SOT323-3 LA6 6
2 2 2 2 2 75_0402_1%~D 0_0603_5%~D 1
3 2 2 2 3
3 EC_MUTE# EC_MUTE# <43> MIC2-L 1 2 LINE_B_L_R 1 2 LINE_B_L_RR 1 2 LINEIN_B_L_C
100P_0402_50V8J~D 2
CA21 4.7U_0805_25V6-K 1
SPK_MUTE# 1 3
<46> SPK_MUTE# MIC_B_PLUG# 4
2 EAPD# G 7
CA64 2 5 G 8
2

C-H_13-18200610CP
RA13 MIC2-R 1 2 LINE_B_R_R 1 2 LINE_B_R_RR 1 2 LINEIN_B_R_C CONN@
CA24 4.7U_0805_25V6-K LA7

100P_0402_50V8J~D
10K_0402_1% 1
RA81 0_0603_5%~D
75_0402_1%~D
1

RA363 @
MIC2-VREFO-R 2 1 CA65 2

2.2K_0402_5%~D
RA60
0_0402_5%~D
1 2 BEEP_C# 1 RA59 2 1 2 PC_BEEP
<43> BEEP#
CA38 0.1U_0402_16V4Z~D 100K_0402_5%~D
DA3
2

1 2 PCH_SPKR_C 1 RA61 2 2 LINEIN_B_L_C


<16> HDA_SPKR
CA39 0.1U_0402_16V4Z~D 100K_0402_5%~D UA7 MAX9892ERT+T_UCSP6~D 1
RA62 @ 3 LINEIN_B_R_C
10K_0402_5%~D LINE_B_L_R RA54 1 2 100_0402_1% A1
INL
1 2 1 RA82 2 AZ5125-02S.R7G_SOT23-3
1

<37> HDMI_IN_AUDIO_CODEC +3V_DVDD


CA58 0.1U_0402_16V4Z~D 100K_0402_5%~D LINE_B_R_R RA55 1 2 100_0402_1% A3
HP_MUTE# INR
1 2 DEPOP#_R B1 +3.3V_AVDD
RA57 0_0402_5% /MUTE Place close to Jack
2

B2
RA17 VDD
2 1 B3
SET
10K_0402_1%

GND
CA40
DA10
0.1U_0402_16V4Z~D
1

3 DEPOP#
DEPOP# <43>

A2
Setting the Turn-Off Time:
HP_MUTE# 1 Ton (ms) = 0.02 x Cset (pF)
4 2 GPIO3 4

BAT54AW_SOT323-3~D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio ALC3661
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 42 of 61
A B C D E F G H
5 4 3 2 1

LA8 LA9
FBMA-L11-160808-121LMA30T_0805
1 2 +PVDD
40mil OUTPL
HCB2012KF-121T50_0805
1 2 SPK_L2+_CONN
B+

www.laptopblue.vn
1 1 5A/120ohm/100MHz

1U_0603_25V6K

1U_0603_25V6K

1U_0603_25V6K

1U_0603_25V6K

1U_0603_25V6K
CA43

CA44

CA45

CA46

CA47
1

1
CA41 CA42 LA10
10U_1206_25V6M 0.1U_0402_25V6K~D UA8 CA48 HCB2012KF-121T50_0805
2 2 +AVCC 7 0.22U_0603_25V7K OUTNL 1 2 SPK_L1-_CONN

2
AVCC BSPL 5A/120ohm/100MHz
BSPL 26 1 2
+PVDD 15 PVCCR OUTPL
16 PVCCR OUTPL 25
Close to UA2 27 PVCCL
LA11
Pin7,15,16,27,28 28 23 OUTNL HCB2012KF-121T50_0805
PVCCL OUTNL OUTPR SPK_R2+_CONN
CA67 1 2
RA63 CA50 22 BSNL 1 2 CA49 5A/120ohm/100MHz
D SPK_CD_L BSNL D
<45> INT-SPK-L 1 2 1 2 1 2 0.027U_0402_16V6K AMP_LEFT_C 3
LINP
0.22U_0603_25V7K

1
LA12
240K_0402_1% RA64 1 2 4 CA52 HCB2012KF-121T50_0805
470P_0402_50V7K~D
10K_0402_5% 0.027U_0402_16V6K LINN 17 BSPR 1 2 0.22U_0603_25V7K OUTNR 1 2 SPK_R1-_CONN
CA51 BSPR 5A/120ohm/100MHz
@ 18 OUTPR
CA66

2
RA65 CA53 OUTPR
1 2 SPK_CD_R 1 2 1 2 0.027U_0402_16V6K AMP_RIGHT_C 12 20 OUTNR
<45> INT-SPK-R RINP OUTNR

1
+GVDD
240K_0402_1% RA66 1 2 11 21 BSNR 1 2
470P_0402_50V7K~D
10K_0402_5% 0.027U_0402_16V6K RINN BSNR

1
CA54 CA55
@ RA68 0.22U_0603_25V7K RA67

2
100K_0402_5% 28.7K_0402_1% Speaker amp impedance of JBL is 4 ohm.
@ GIN0 5 14
GAIN0 PBTL
1 2
+3VALW Speaker Connector

2
GIN1 6 10 PLIMIT
RA69 GAIN1 PLIMIT +GVDD JSPK1
0_0402_5% SPK_L1-_CONN 15 mils trace 1 1

1
1U_0603_25V6K

1U_0603_25V6K
TPA3113 for Speaker 1 2 EAPD_R 1 9 +GVDD SPK_L2+_CONN 2
<45> SPK_MUTE# SD# GVDD 2

CA56
RA70 SPK_R1-_CONN 3 3

CA57
1 RA83 2 2 10K_0402_1% SPK_R2+_CONN 4
+5VS RA71 0_0402_5% FAULT# 4
24

2
100K_0402_5% PGND
13 19 5

2
NC PGND GND
INPUT 29 GND AGND 8 6 GND
GAIN1 GAIN0 AV(inv) IMPEDANCE

2
2

3
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
@ @ TPA3113D2PWPR_HTSSOP28 ACES_50279-0040N-001

AZ5125-02S.R7G_SOT23-3

AZ5125-02S.R7G_SOT23-3
RA72 RA73 1 1 1 1 CONN@

CA36

CA34

CA33

CA32
100K_0402_1% 100K_0402_1% 0 0 20dB 60Kohm
DA4 DA5
2 1

2 1

GIN0 GIN1 2 2 2 2
C
0 1 26dB 30Kohm C
RA74 RA75
100K_0402_1% 100K_0402_1% 1 0 32dB 15Kohm

1
1

1 1 36dB 9Kohm
B+ RA364 1 2 10_0402_5%~D +AVCC

10U_0603_6.3V6M~D
CA72
2

B B

A A

Security Classification Compal Secret Data


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Speaker AMP/CardReaser B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 43 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

+3.3V_F347
D D
R1 1 20_0603_5%~D +3.3V_F347_R

0.1U_0402_16V4Z~D

22P_0402_50V8J~D
1U_0805_10V7

0.1U_0402_16V4Z~D
1 2

C1

C2
1 1

C3
+3.3V_F347

C4
2 1 I2C_DAT 4.7K_0402_5%~D 2 1 R2
2 2
place R1564 as close as U602 I2C_CLK 4.7K_0402_5%~D 2 1 R3
U1
6 2 SPI_MOCLK 1 2 SPI_MOCLK_R
VDD P0.0 SPI_MOSO R4 0_0402_5%~D
1
USB20_P6 P0.1 SPI_MOSI
<20> USB20_P6 4 32
USB20_N6 D+ P0.2 SPI_MOCS#
<20> USB20_N6 5 31
R5 D- P0.3 I2C_DAT
+5VALW 1 2 0_0603_5%~D 30 I2C_DAT <48,53>
P0.4 I2C_CLK
W=40mils +3.3V_F347 7
REGIN P0.5
29 I2C_CLK <48,53>
+5VS R6 1 @ 2 0_0603_5%~D 8 28 C5 @ 1 2 0.1U_0402_16V4Z~D
VBUS P0.6 R7
27 1 2 1K_0402_5%~D +3.3V_F347
P0.7
+3.3V_F347 1 2 9
R8 RST#/C2CK SLP_S3
10 26
P3.0/C2D P1.0

1U_0805_10V7

0.1U_0402_16V4Z~D
1 1 1K_0402_1%~D 25 BATT_CHG_LED 10K_0402_5% 2 1 R9 +3.3V_F347
P1.1

C6

C7
18 24 ACIN#
P2.0 P1.2 LID_SW_IN#_D LID_SW_IN#
17 23 2 1 LID_SW_IN# <19,43,48,53>
P2.1 P1.3 BATT_LOW_LED D70
16 22
2 2 P2.2 P1.4 SLP_S5 SDMK0340L-7-F_SOD323-2~D
15 21
P2.3 P1.5 C8 @ 1
14
P2.4 P1.6
20 2 0.1U_0402_16V4Z~D
13 19 C9 @ 1 2 0.1U_0402_16V4Z~D
P2.5 P1.7
12
+3.3V_F347 P2.6
11 3
P2.7 GND
+3.3V_F347 JP1 C8051F347-GQ_LQFP32_7X7

@
1
1
0.1U_0402_16V4Z

C11

C12

C13

C14

C15

C16

C17

C18
2
2
3
1 3 We are Green SA00003IR20
C10

4
4 U2
5 1 1 1 1 1 1 1 1
5 SPI_MOSI 15_0402_5% SPI_MOSO
6 2 1 R10 5 2 R11 1 2 15_0402_5%
2 6 +3.3V_F347 DI SO
7 SPI_MOCLK_R 15_0402_5% 2 1 R12 6
GND1 2 2 2 2 2 2 2 2 CLK
C 8 C
GND2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
Cloase to JP1 CONN@ 1 2 SPI_MOCS# 1
R13 10K_0402_5%~D CS
AMPHE_G846A06201EU
1 2 7 HOLD
R14 10K_0402_5%~D
1 2 3
R15 10K_0402_5%~D WP
+3.3V_F347 8 4
VCC VSS

0.1U_0402_16V4Z~D

22P_0402_50V8J~D
1 EN25Q80A-100HIP_SO8

C19
1

C20
2
2

+3.3V_F347
1

R16
100K_0402_1%~D
DEVICE SMBUS ADDRESS
MAXIM - LED 0100 000b
2

SLP_S3 MAXIM - GPIO 0100 001b


1
D
Q1 +3.3V_F347
I2C EEPROM 1010 000b
2 SSM3K7002F_SC59-3~D
<17,43> PM_SLP_S3# G
1

+3VALW +3.3V_F347
S R17
3 100K_0402_1%~D J11 @
2 1
2 1
2

SLP_S5 JUMP_43X118
1 Q3
+3.3V_F347 D
B B
Q2 SI3456DDV-T1-GE3_TSOP6~D
2 SSM3K7002F_SC59-3~D
<17,43> PM_SLP_S5#
1

D
G 6

S
R18 5 4

4.7U_0603_6.3V6M~D
100K_0402_1%~D S 2
3

0.1U_0402_25V6K~D

100K_0402_1%~D
1

1
1 1

G
2

R19

C22
C21
ACIN#

3
D
1
B+_BIAS +3.3V_F347 behavior
Q4 2 2
STATE

2
2 SSM3K7002F_SC59-3~D +3.3V_F347 +3VALW
<17,29,43,57,63> ACIN G R20
100K_0402_1%~D
S0 S3 S4 S5
1

S 1 2
3 R21 R22

SSM3K7002F_SC59-3~D
100K_0402_1%~D 100K_0402_1%~D 1 AC IN ON ON ON ON

300K_0402_5%~D

0.1U_0402_25V6K~D
D

2
1
2

Q5

R23

C23
+3.3V_F347 BATT_LOW_LED 2 BAT only ON ON OFF OFF
1 1 G
D D
AC mode battery full in S5:turn off ELC controller
1

Q6 Q7 S 2

1
R24 2 SSM3K7002F_SC59-3~D 2 SSM3K7002F_SC59-3~D 3
<43> BATT_LOW_LED# <43> 3V_F347_ON
100K_0402_1%~D

100K_0402_1%~D G G
1
R25

S S
2

BATT_CHG_LED 3 3
1
D
2

Q8
2 SSM3K7002F_SC59-3~D
<43> BATT_CHG_LED# G

S
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC (1)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 44 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn

<53> 7313_INT#
L/R Tron, Logo, Alien Head, TP
+3.3V_F347
D D
+3.3V_F347

0.1U_0402_16V4Z~D
1 R26 2 1

C24
4.7K_0402_1%~D
4.7K_0402_1%~D
1 U3
2
R27

22 21
INT#/O16 V+
I2C_CLK 19 1 LTRON_LED_R_DRV#
<47,53> I2C_CLK SCL P0
I2C_DAT 20 2 LTRON_LED_G_DRV#
2

<47,53> I2C_DAT SDA P1


3 LTRON_LED_B_DRV#
AD0_0 P2 RTRON_LED_R_DRV#
18 4 RTRON_LED_R_DRV# <53>
AD0_1 AD0 P3 RTRON_LED_G_DRV#
23 5 RTRON_LED_G_DRV# <53>
AD0_2 AD1 P4 RTRON_LED_B_DRV#
4.7K_0402_1%~D

24 6 RTRON_LED_B_DRV# <53>
AD2 P5
4.7K_0402_1%~D

7 ALIEN_LED_R_DRV#_1
P6
1

<53> TP_LED_R_DRV# TP_LED_R_DRV# 14 8 ALIEN_LED_G_DRV#_1


P12 P7
R28

R29

<53> TP_LED_G_DRV# TP_LED_G_DRV# 15 10 ALIEN_LED_B_DRV#_1


TP_LED_B_DRV# 16 P13 P8 LOGO_LED_R_DRV#
<53> TP_LED_B_DRV# 11
P14 P9 LOGO_LED_G_DRV#
17 12
OSC P10 LOGO_LED_B_DRV#
13
2

P11
9 25
GND GND
MAX7313DATG+T_TQFN-EP24_4X4~D

+3.3V_F347 +3.3V_F347
4.7K_0402_1%~D

4.7K_0402_1%~D

4.7K_0402_1%~D

0.1U_0402_16V4Z
1
1

C25
Indicator, Power
R30

R31

R32

+5VS
U4 2
22 21
2

INT#/O16 V+

0.1U_0402_16V4Z
7313_INT# I2C_CLK 19 1
I2C_DAT SCL P0
C 20 2 1 C
SDA P1

C26
3 +5VS
P2

0.1U_0402_16V4Z
AD2_0 18 4 LED_R_7313#_1 LED_R_7313#_1 <53> 20mil
AD2_1 AD0 P3 LED_G_7313#_1 JLOGO1
23 5 LED_G_7313#_1 <53>
AD2_2 AD1 P4 LED_B_7313#_1 2
24 6 LED_B_7313#_1 <53> 1 1
AD2 P5 1

C27
7 2
P6 2
1
4.7K_0402_1%~D

HDD_R_7313# 14 8 LID_SW 3 JTRONF


P12 P7 3
R33

HDD_G_7313# 15 10 LOGO_LED_R_DRV# 4 1
HDD_B_7313# P13 P8 PWR_R_7313# LOGO_LED_G_DRV# 4 2 1
16 11 PWR_R_7313# <53> 5 2
P14 P9 PWR_G_7313# LOGO_LED_B_DRV# 5 RTRON_LED_R_DRV# 2
17 12 PWR_G_7313# <53> 6 3
OSC P10 PWR_B_7313# 6 RTRON_LED_G_DRV# 3
13 PWR_B_7313# <53> 7 4
2

P11 ALIEN_LED_R_DRV#_1 7 RTRON_LED_B_DRV# 4


9 25 8 5
GND GND ALIEN_LED_G_DRV#_1 8 LTRON_LED_R_DRV# 5
9 6
MAX7313DATG+T_TQFN-EP24_4X4~D ALIEN_LED_B_DRV#_1 9 LTRON_LED_G_DRV# 6
10 7
10 LTRON_LED_B_DRV# 7
11 8
11 8
12 9
HDD_B 12 9
HDD_B <53> 13 10
G1 10
14 11
G2 GND1
1 12
D ACES_50224-0120N-001 GND2
CONN@ ACES_50224-01001-001
2 Q9 CONN@
G SSM3K7002F_SC59-3~D

+5VS
S
3
HDD_B_7313#
LOGO Board CONN
TRON LED Board (F) CONN
1 100K_0402_5%~D

HDD_R HDD_R <53>


R34

+5VALW
1
100K_0402_5%~D

D
2

1
R35

SATA_LED_ACT 2 Q10
G SSM3K7002F_SC59-3~D
B+_BIAS +5VS Q11 +5VS_TP_LED
+5VS
SSM3K7002F_SC59-3~D

1 S SI3456DDV-T1-GE3_TSOP6~D
2

D
D 3 6

S
300K_0402_5%~D

0.1U_0402_16V4Z
HDD_R_7313# 5 4

2
B B
Q12

0.1U_0402_16V4Z
2 LID_SW 2
<16> PCH_SATALED# LID_SW <53>

R36

1U_0603_10V4Z~D
G HDD_G HDD_G <53> 1 1 1

C29

C30
1 1

C32
S D

3
3
1 1
2 2
D 2 Q13
<19,43,47,53> LID_SW_IN# G 2
SSM3K7002F_SC59-3~D JTRONL
2 Q14 EN_TPLED 1
1
SSM3K7002FU_SC70-3~D
G SSM3K7002F_SC59-3~D S LTRON_LED_R_DRV# 2
3 2

1.5M_0402_5%~D

0.1U_0402_25V6K~D
1 LTRON_LED_G_DRV# 3
3
1

1
D

R37
S LTRON_LED_B_DRV# 4
3 4

C33
<43> EN_TPLED# 2 5
HDD_G_7313# G 5
6
SATA_LED_ACT Q15 2 6
S
3

2
GND
8
GND
1
Reference AD2 AD1 AD0 MAX7313 D E-T_4260-F06N-10L
CONN@
LID_SW 2 Q16

Tron Lights,TP
G SSM3K7002F_SC59-3~D
Touchpad LED circuit
U605 0 1 0 A-panel,B-Panel Logo
S
3
TRON LED Board (L) CONN

Power Button,
U608 0 1 1 Media and Status LED Color

Button,
U? 1 0 0 Indicator Brightness

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC (2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 45 of 61
5 4 3 2 1
A B C D E

www.laptopblue.vn

1 1

+3VS +5VS

Close to JHDD1
+3VS
Free Fall Sensor

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D

47P_0402_50V8J~D
1 1 1 1 1 2

CN4
0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

CN1

CN2

CN3

CN5

CN59
2 2 2 2 2 1
1 1

C34

C35
2 2
UN4
LNG3DM 10
RES
1 13
VDD_IO RES
14 15
VDD RES JHDD1
16
FFS_INT1 RES
<17> FFS_INT1 11
FFS_INT2 INT 1
<21,50> FFS_INT2 9 5 1
INT 2 GND CN6 SATA_PTX_DRX_P0_C GND
12 <16> SATA_PTX_DRX_P0 1 2 0.01U_0402_16V7K~D 2
GND CN7 SATA_PTX_DRX_N0_C A+
7 <16> SATA_PTX_DRX_N0 1 2 0.01U_0402_16V7K~D 3
PCH_SMBDATA SDO/SA0 A-
<6,12,13,14,15,19,50,51,53> PCH_SMBDATA 6 4
PCH_SMBCLK SDA / SDI / SDO CN8 SATA_PRX_DTX_N0_C GND
<6,12,13,14,15,19,50,51,53> PCH_SMBCLK 4 <16> SATA_PRX_DTX_N0 1 2 0.01U_0402_16V7K~D 5
SCL/SPC CN9 SATA_PRX_DTX_P0_C B-
2 <16> SATA_PRX_DTX_P0 1 2 0.01U_0402_16V7K~D 6
NC B+
8 3 7
CS NC GND
FFS_INT1 connect to PCH GPIO & EC LNG3DMTR_LGA16_3X3~D

discuss with BIOS to use which pin +3VS 8


VCC3.3
9
VCC3.3
10
VCC3.3
2 11 2
GND
<21> HDD_DET# 12
GND
13
GND
+5VS 14
VCC5
15
VCC5
16
VCC5
17
FFS_INT2_CONN GND
<50> FFS_INT2_CONN 18
DAS/DSS
19
GND
20 23
VCC12 G1
21 24
VCC12 G2
22
VCC12

FOX_LD2822F-SAQL6
CONN@
Close to JHDD2
+3VS +5VS
+3VS

1000P_0402_50V7K~D
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D

47P_0402_50V8J~D
1 1 1 1 1 2

CN12

CN13

CN14

CN60
CN10

CN11
0.01U_0402_16V7K

0.1U_0402_25V6K

2 2 2 2 2 1
1 1
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1

1
CN23

CN24

@ @ @
2 2
RN5

RN46

RN6

RN7
+3VS

UN1
2

2
RN1 1 2 0_0402_5% 7 6 JHDD2
EN VDD
16
CN15 1 SATA_PTX_DRX_P1_R VDD
<16> SATA_PTX_DRX_P1 2 0.01U_0402_16V7K~D 1
A_INp
1
GND
CN16 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N1_R 2 10 SATA_PTX_DRX_P1_C 2
<16> SATA_PTX_DRX_N1 A_INn NC HDD_REXT_SATA SATA_PTX_DRX_N1_C A+
20 3
3
CN18 1 SATA_PRX_DTX_P1_RC REXT A- 3
<16> SATA_PRX_DTX_P1 2 0.01U_0402_16V7K~D 5 4
CN17 1 SATA_PRX_DTX_N1_RC B_OUTp HDD_A_PRE0 SATA_PRX_DTX_N1_C GND
<16> SATA_PRX_DTX_N1 2 0.01U_0402_16V7K~D 4
B_OUTn A_PRE0
9 5
B-
8 HDD_B_PRE0 SATA_PRX_DTX_P1_C 6
RN2 @ HDD_B_PRE1 17 B_PRE0 B+
+3VS 1 2 0_0402_5% 7
RN3 @ HDD_A_PRE1 19 B_PRE1 SATA_PTX_DRX_P1_RC CN19 1 SATA_PTX_DRX_P1_C GND
1 2 0_0402_5% 15 2 0.01U_0402_16V7K~D
A_PRE1 A_OUTp SATA_PTX_DRX_N1_RC CN20 1 SATA_PTX_DRX_N1_C
A_OUTn
14 2 0.01U_0402_16V7K~D
RN4 1 @ 2 0_0402_5% 18
TEST SATA_PRX_DTX_P1_R CN21 1 SATA_PRX_DTX_P1_C
3 11 2 0.01U_0402_16V7K~D +3VS 8
GND B_INp SATA_PRX_DTX_N1_R CN22 1 SATA_PRX_DTX_N1_C VCC3.3
13 12 2 0.01U_0402_16V7K~D 9
GND B_INn VCC3.3
21 10
EPAD VCC3.3
11
PS8520BTQFN20GTR2_TQFN20_4X4 GND
12
GND
13
GND
+5VS 14
VCC5
15
VCC5
16
VCC5
17
HDD_B_PRE0 RN8 @ FFS_INT2_CONN GND
1 2 0_0402_5% 18
DAS/DSS
19
HDD_B_PRE1 RN9 @ GND
1 2 0_0402_5% 20 23
VCC12 G1
21 24
HDD_A_PRE1 RN10 1 @ VCC12 G2
2 0_0402_5% 22
VCC12
Pin 20: Pin 9: HDD_A_PRE0 RN11 1 2
PARADE PS8250B: PARADE PS8250B: 2K_0402_5% FOX_LD2822F-SAQL6
HDD_REXT_SATA RN12
1 2 CONN@
Reserve RN46, Mount RN12 Reserve RN11. 5.1K_0402_1%

PERICOM PI3EQX6741ST: PERICOM PI3EQX6741ST:


Mount RN46, Reserve RN12 Reserve RN11

ASMEDIA ASM1466: ASMEDIA ASM1466:


Mount RN46, Reserve RN12 Mount RN11 to pull down

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA HDD1 & HDD2/FFS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 46 of 61
A B C D E
A B C D E

www.laptopblue.vn ODD_DA#_R

+5VS_ODD SATA ODD Conn.

1
D
2 QN4
ODD power +5VS QN2 +5VS_ODD
<43> ODD_EJECT#
G 2N7002E-T1-E3_SOT23-3

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D
SI3456DDV-T1-GE3_TSOP6~D S

3
1 1 1 1 JODD1

CN35

CN36

CN37

CN38
6 1

S
+3VS 1

1U_0402_6.3V6K~D
B+_BIAS 5 4 2
2
1 2 3
2 2 2 2 3

CN39
1 1, Host generate Low pulse 40ms to eject ODD +5VS_ODD 4
4

2
1 1
5

G
RN26 2, After this pulse, signal remain high and no 6
5

3
300K_0402_5%~D 2 RN45 1 ODD_DA#_R 6
pulse is allowed within 7s <17> ODD_DA# 2 0_0402_5%~D 7
7
<21> ODD_DETECT# 8
8
9

1
ODD_EN SATA_PRX_DTX_P2_C 9
Placea caps. near ODD CONN. +5VS SATA_PRX_DTX_N2_C
10
10
11
11

2
1.5M_0402_5%~D

0.1U_0402_25V6K~D
1 12
12

1
D

CN40
SATA_PTX_DRX_N2_C 13
13

1
RN27
2 QN1 +3VS SATA_PTX_DRX_P2_C 14
<21> ODD_EN# 14
G SSM3K7002FU_SC70-3~D 15
2 @ RN28 15
S 16

1
100K_0402_5%~D FFS_INT2_CONN 16
<49> FFS_INT2_CONN 17 21
17 GND1

2
G
18 22

2
+5VS 18 GND2
19 23
FFS_INT2 FFS_INT2_CONN 19 GND3
<21,49> FFS_INT2 3 1 1 2 FFS_INT2_CONN <49> 20
20 GND4
24

D
DN1 SDM10U45-7_SOD523-2~D
E-T_0870K-F20C-22L
QN3 CONN@
SSM3K7002FU_SC70-3~D
+3VS

ODD Redriver

0.01U_0402_16V7K

0.1U_0402_25V6K
1 1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
Pin 20: Pin 9:

1
CN33

CN34
@ @ @ ODD_B_PRE0 RN21 1 @ 2 0_0402_5%
2 2 PARADE PS8250B: PARADE PS8250B:

RN17

RN18

RN19

RN20
+3VS ODD_B_PRE1 RN22 1 @ 2 0_0402_5% Reserve RN18, Mount RN25 Reserve RN24.

UN2 ODD_A_PRE1 RN23 1 @ 2 0_0402_5% PERICOM PI3EQX6741ST: PERICOM PI3EQX6741ST:

2
RN13 1 2 0_0402_5% 7 6
EN VDD ODD_A_PRE0 RN24 1
Mount RN18, Reserve RN25 Reserve RN24
16 2
CN27 SATA_PTX_DRX_P2_R VDD
<16> SATA_ODD_PTX_DRX_P2 1 2 0.01U_0402_16V7K~D 1 2K_0402_5%
A_INp
2
<16> SATA_ODD_PTX_DRX_N2
CN28 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N2_R 2
A_INn NC
10 ODD_REXT_SATA RN25
1 2 ASMEDIA ASM1466: ASMEDIA ASM1466: 2
20 ODD_REXT_SATA 5.1K_0402_1% Mount RN18, Reserve RN25 Mount RN24 to pull down
CN25 SATA_PRX_DTX_P2_R REXT
<16> SATA_ODD_PRX_DTX_P2 1 2 0.01U_0402_16V7K~D 5
CN26 SATA_PRX_DTX_N2_R B_OUTp ODD_A_PRE0
<16> SATA_ODD_PRX_DTX_N2 1 2 0.01U_0402_16V7K~D 4
B_OUTn A_PRE0
9
8 ODD_B_PRE0
RN14 1 @ ODD_B_PRE1 17 B_PRE0
+3VS 2 0_0402_5%
RN15 1 @ ODD_A_PRE1 19 B_PRE1 SATA_PTX_DRX_P2_RC CN29 1 SATA_PTX_DRX_P2_C
2 0_0402_5% A_PRE1 A_OUTp
15 2 0.01U_0402_16V7K~D
14 SATA_PTX_DRX_N2_RC CN30 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N2_C
RN16 1 @ A_OUTn
2 0_0402_5% 18
TEST SATA_PRX_DTX_P2_RC CN31 1 SATA_PRX_DTX_P2_C
3 11 2 0.01U_0402_16V7K~D
GND B_INp SATA_PRX_DTX_N2_RC CN32 1 SATA_PRX_DTX_N2_C
13 12 2 0.01U_0402_16V7K~D
GND B_INn
21
EPAD
PS8520BTQFN20GTR2_TQFN20_4X4

+3VS

+3VS

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D
1 1 1 1

CN51

CN52

CN53

CN54
m-SATA Re-Driver 2 2 2 2 +3VS
0.01U_0402_16V7K

0.1U_0402_25V6K

+3VS +1.5VS
1 1
3 3
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

JP2
1

1
CN49

CN50

@ @ @ 1 2
2 2 WAKE# 3.3V
RN34

RN35

RN36

RN37

Placea caps. near JP2 CONN. PAD~D T62 @ 3 4


+3VS PAD~D T63 @ NC GND
5 6
NC 1.5V
7 8
UN3 CLKREQ# NC
9 10
2

RN30 1 GND NC
2 0_0402_5% 7 6 +1.5VS 11 12
EN VDD REFCLK- NC
16 13 14
CN41 SATA_PTX_DRX_P3_R VDD REFCLK+ NC
<16> MSATA_PTX_DRX_P3 1 2 0.01U_0402_16V7K~D 1 15 16
CN42 SATA_PTX_DRX_N3_R A_INp GND NC
<16> MSATA_PTX_DRX_N3 1 2 0.01U_0402_16V7K~D 2 10 PAD~D T61 @ 17 18
A_INn NC NC GND

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D
20 mSATA_REXT_SATA PAD~D T59 @ 19 20
CN43 SATA_PRX_DTX_P3_R REXT NC NC
<16> MSATA_PRX_DTX_P3 1 2 0.01U_0402_16V7K~D 5 1 1 1 1 21 22
B_OUTp GND PERST#

CN55

CN56

CN57

CN58
<16> MSATA_PRX_DTX_N3 CN44 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N3_R 4 9 mSATA_A_PRE0 SATA_PRX_DTX_P3_C 23 24
B_OUTn A_PRE0 mSATA_B_PRE0 SATA_PRX_DTX_N3_C PERn0 +3.3Vaux
8 25 26
RN31 1 @ mSATA_B_PRE1 B_PRE0 PERp0 GND
+3VS 2 0_0402_5% 17
B_PRE1
27
GND +1.5V
28
RN32 1 @ mSATA_A_PRE1
2 0_0402_5% 19 15 SATA_PTX_DRX_P3_RC CN45 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P3_C 2 2 2 2 29 30 PCH_SMBCLK
A_PRE1 A_OUTp GND SMB_CLK PCH_SMBCLK <6,12,13,14,15,19,49,51,53>
14 SATA_PTX_DRX_N3_RC CN46 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N3_C SATA_PTX_DRX_N3_C 31 32 PCH_SMBDATA
A_OUTn PETn0 SMB_DATA PCH_SMBDATA <6,12,13,14,15,19,49,51,53>
RN33 1 @ 2 0_0402_5% 18 SATA_PTX_DRX_P3_C 33 34
TEST SATA_PRX_DTX_P3_RC CN47 1 SATA_PRX_DTX_P3_C PETp0 GND
3 11 2 0.01U_0402_16V7K~D 35 36
GND B_INp SATA_PRX_DTX_N3_RC CN48 1 SATA_PRX_DTX_N3_C GND USB_D-
13 12 2 0.01U_0402_16V7K~D 37 38
GND B_INn NC USB_D+
21 39 40
EPAD NC GND
Placea caps. near JP2 CONN. 41
NC LED_WWAN#
42
PS8520BTQFN20GTR2_TQFN20_4X4 43 44
PAD~D T65 @ NC LED_WLAN#
45 46
PAD~D T64 @ NC LED_WPAN#
47 48
RN43 1 EC_TX_DAT NC +1.5V
<43> E51TXD_P80DATA 2 0_0402_5%~D 49 50
RN44 1 EC_RX_CLK NC GND
<43> E51RXD_P80CLK 2 0_0402_5%~D 51
NC +3.3V
52

2
53 54
GND GND

100K_0402_5%~D
RN47
BELLW_80003-4041
mSATA_B_PRE0 RN38 1 @ 2 0_0402_5% CONN@

1
Pin 20: Pin 9: mSATA_B_PRE1 RN39 1 @ 2 0_0402_5%
PARADE PS8250B: PARADE PS8250B: mSATA_A_PRE1 RN40 1 @ 2 0_0402_5%
Reserve RN35, Mount RN42 Reserve RN41.
mSATA_A_PRE0 RN41 1 2
4 PERICOM PI3EQX6741ST: PERICOM PI3EQX6741ST: 2K_0402_5% 4
mSATA_REXT_SATA RN42
1 2
Mount RN35, Reserve RN42 Reserve RN41 5.1K_0402_1%

ASMEDIA ASM1466: ASMEDIA ASM1466:


Mount RN35, Reserve RN42 Mount RN41 to pull down

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA ODD/mSATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 47 of 61
A B C D E
A B C D E

www.laptopblue.vn

+1.5VS +3VS

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
47P_0402_50V8J~D

47P_0402_50V8J~D
1 1 1 1 2 1 1 1 2 1

C36

C37

C38

C63

C39

C40

C41

C64
WLAN 2 2 2 1 2 2 2 1

JMINI1
<17,43,44> PCIE_WAKE# PCIE_WAKE# @ RE12 1 2 0_0402_5%~D 1 2 +3VS
COEX2 R38 WAKE# 3.3V
1 2 0_0402_5%~D 3 4
COEX1 R39 NC GND
1 2 0_0402_5%~D 5
NC 1.5V
6 +1.5VS
<18> MINI1CLK_REQ# MINI1CLK_REQ# 7 8 RE31 1 2 0_0402_5%~D
CLKREQ# NC LPC_FRAME# <19,43>
9 10 RE26 1 2 0_0402_5%~D
GND NC LPC_AD3 <19,43>
CLK_PCIE_MINI1# 11 12 RE27 1 2 0_0402_5%~D
<18> CLK_PCIE_MINI1# REFCLK- NC LPC_AD2 <19,43>
CLK_PCIE_MINI1 13 14 RE28 1 2 0_0402_5%~D
<18> CLK_PCIE_MINI1 REFCLK+ NC LPC_AD1 <19,43>
15 16 RE29 1 2 0_0402_5%~D
GND NC LPC_AD0 <19,43>
RE32 1 2 0_0402_5%~D 17 18
<6,17,43,44,53> PLT_RST# NC GND
19 20 WL_OFF#
<18> CLK_DEBUG NC NC WL_OFF# <17>
21 22 PLT_RST#
GND PERST# PLT_RST# <6,17,43,44,53>
<16> PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_N1 23 24
PCIE_PRX_WLANTX_P1 PERn0 +3.3Vaux
<16> PCIE_PRX_WLANTX_P1 25 26
PERp0 GND
27 28
C59 0.1U_0402_10V7K~D GND +1.5V
29 30
PCIE_PTX_WLANRX_N1_C GND SMB_CLK WiGi_RADIO_DIS#_R RE22 1
<16> PCIE_PTX_WLANRX_N1 1 2 31
PETn0 SMB_DATA
32 2 0_0402_5%~D WiGi_RADIO_DIS# <21>
1 2 PCIE_PTX_WLANRX_P1_C 33 34
<16> PCIE_PTX_WLANRX_P1 PETp0 GND
35 36 USB20_N4
GND USB_D- USB20_P4 USB20_N4 <20>
C60 0.1U_0402_10V7K~D 37 38
NC USB_D+ USB20_P4 <20>
+3VS 39 40
NC GND
41 42
NC LED_WWAN#
43 44
NC LED_WLAN#
45 46
NC LED_WPAN#
47 48
NC +1.5V
49 50
BT_ON# BT_ON#_R NC GND @
<17> BT_ON# 1 2 51 52 D3
1K_0402_1%~D RE119 NC +3.3V
53 54 WiGi_RADIO_DIS#_R 2 1 WiGi_RADIO_DIS#
GND GND
2 2
BELLW_80003-4041 SDMK0340L-7-F
CONN@

Display Mini Card (DMC)


+1.5VS +1.5VS_DMC
+3VS +3VS_DMC L1
L2 2 1
2 1 BLM18AG601SN1D_0603~D

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
BLM18PG330SN1D_2P~D
+3VS_DMC

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D
1 1 1

C42

C43

C44
JDMC1 1 1
+1.5VS_DMC +3VS_DMC

C45

C46
PCIE_WAKE# @ RE30 1 2 0_0402_5%~D 1 2
COEX2 R40 1 2
1 2 0_0402_5%~D 3 4
COEX1 R41 3 4 2 2 2
1 2 0_0402_5%~D 5
5 6
6
MINI2CLK_REQ# 7 8 2 2
<18> MINI2CLK_REQ# 7 8
9 10 CPU_MXM_DMC_AUXN R42 1 2 100K_0402_5%~D
CLK_PCIE_MINI2# 9 10 CPU_MXM_DMC_AUXP R43 1
<18> CLK_PCIE_MINI2# 11 12 2 100K_0402_5%~D
CLK_PCIE_MINI2 11 12
<18> CLK_PCIE_MINI2 13 14
13 14
15 16
15 16

17 18
17 18 DMC_RADIO_OFF#
19 20 DMC_RADIO_OFF# <21>
19 20 PLT_RST#
21 22
PCIE_PRX_WANTX_N2 21 22
<16> PCIE_PRX_WANTX_N2 23 24
3
PCIE_PRX_WANTX_P2 23 24 3
<16> PCIE_PRX_WANTX_P2 25 26
25 26
27 28
27 28 MINI2_SMBCLK RE33@1
C61 0.1U_0402_10V7K~D 29
29 30
30 2 0_0402_5%~D PCH_SMBCLK PCH_SMBCLK <6,12,13,14,15,19,49,50,53>
<16> PCIE_PTX_WANRX_N2 1 2 PCIE_PTX_WANRX_N2_C 31 32 MINI2_SMBDATA RE34@1 2 0_0402_5%~D PCH_SMBDATA PCH_SMBDATA <6,12,13,14,15,19,49,50,53>
31 32
<16> PCIE_PTX_WANRX_P2 1 2 PCIE_PTX_WANRX_P2_C 33 34
33 34 USB20_N5
35 36 USB20_N5 <20>
C62 0.1U_0402_10V7K~D 35 36 USB20_P5
37 38 USB20_P5 <20>
37 38
+3VS_DMC 39 40
39 40
41 42
41 42
43 44
43 44
45 46
45 46
47 48
47 48 R44
49 50
49 50 1M_0402_5%~D
51 52
51 52
1 2

<18> DMC_PCH_DET# DMC_PCH_DET# 53 54 DP_DMC_HPD DP_DMC_HPD <39>


CPU_MXM_DMC_AUXN 53 54
<39> CPU_MXM_DMC_AUXN 55 56
CPU_MXM_DMC_AUXP 55 56
<39> CPU_MXM_DMC_AUXP 57 58
57 58 CPU_MXM_DMC_N3
59 60 CPU_MXM_DMC_N3 <39>
59 60 CPU_MXM_DMC_P3
61 62 CPU_MXM_DMC_P3 <39>
CPU_MXM_DMC_N2 61 62
<39> CPU_MXM_DMC_N2 63 64
CPU_MXM_DMC_P2 63 64
<39> CPU_MXM_DMC_P2 65 66
65 66 CPU_MXM_DMC_N1
67 68 CPU_MXM_DMC_N1 <39>
67 68 CPU_MXM_DMC_P1
69 70 CPU_MXM_DMC_P1 <39>
CPU_MXM_DMC_N0 69 70
<39> CPU_MXM_DMC_N0 71 72
CPU_MXM_DMC_P0 71 72
<39> CPU_MXM_DMC_P0 73 74
73 74
75 76
75 76
77
GND1
79 78
GND3 GND2
TYCO_2041286-1
CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card -WLAN/DMC/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 48 of 61
A B C D E
5 4 3 2 1

+5VALW

SW_USB20_P0
@ RI1

4
LI3
1 2 0_0402_5%~D

3 USB20_P0_CONN
www.laptopblue.vn
Power share
+5VALW CI18
1 1
CI16
4 3 UI1 4.7U_0805_10V4Z 0.1U_0402_16V7K 2.0A

2
PWRSHARE_OE# 8 1 PWRSHARE_EN +3VALW 2 2 +USB3_VCCA
<43> PWRSHARE_OE# CB CEN

100K_0402_5%
SW_USB20_N0 1 2 USB20_N0_CONN USB20_N0 7 2 SW_USB20_N0
1 2 <20> USB20_N0 USB20_P0 TDM DM SW_USB20_P0
6 3 UI2
<20> USB20_P0 TDP DP

RI81
DLW21SN900SQ2L_0805_4P~D 5 4 PWRSHARE_SEL# 1 8 80mil
+5VALW VDD SELCDP GND VOUT

1
9 2 7

1
Thermal Pad VIN VOUT

0.1U_0402_16V4Z~D
@ RI2 1 2 0_0402_5%~D 2 3 6 0_0402_1%
VIN VOUT

CI1

EPAD
SLG55584AVTR_TDFN8_2X2 RI82 PWRSHARE_EN_R# 4 5 1 2 USB_OC0# <20>
10K_0402_5% EN FLG
1 RI80 @ 1

2
D 1 D

SSM3K7002FU_SC70-3~D
CI13 CI15

9
1
@ RI3 D
1 2 0_0402_5%~D AP2301MPG-13_MSOP8

0.1U_0402_16V7K
PWRSHARE_EN 1 2 2 0.1U_0402_16V7K
LI1 2 2
RI86 0_0402_5%~D G

QI1
USB3RN1_R_C 2 1 USB3RN1_R +5VALW S

3
2 1 DI7

<43> PWRSHARE_EN_EC# 1 2
USB3RP1_R_C 3 4 USB3RP1_R
3 4 PWRSHARE_SEL# RI9 1 2 10K_0402_5%~D
SDMK0340L-7-F_SOD323-2~D
DLW21SN900HQ2L_0805_4P~D PWRSHARE_OE# RI8 @
1 2 10K_0402_5%~D
@ RI4 1 2 0_0402_5%~D PWRSHARE_SEL# RI10 1 @ 2 10K_0402_5%~D
PWRSHARE_EN RI7 1 @ 2 10K_0402_5%~D

@ RI5 1 2 0_0402_5%~D +3VS


LI2
CI7 USB CONN
0.01U_0402_16V7K~D
USB3TN1_R_C 2 1 USB3TN1_R 1 2 +USB3_VCCA +USB3_VCCA
2 1
1 2
USB3TP1_R_C 3 4 USB3TP1_R CI6 JUSB1
3 4

10U_0603_6.3V6M~D
.1U_0402_16V7K~D USB3TP1_R 9 1
UI3 SSTX+
1 1
DLW21SN900HQ2L_0805_4P~D VBUS

CI22
1 7 RI56 1 2 4.99K_0402_1% USB3TN1_R 8 CI20 +
@ RI6 VCC NC USB20_P0_CONN SSTX-
1 2 0_0402_5%~D 13 24 @ RI57 1 2 0_0402_5%~D 3
VCC NC D+ 220U_6.3V_M
7
USB3RN1 CI9 USB3RN1_L USB3RN1_R_C USB20_N0_CONN GND 2 2
<20> USB3RN1 1 2 0.1U_0402_10V6K~D 11 20 2 11
+3VS USB3RP1 CI8 USB3RP1_L TX2- RX2- USB3RP1_R_C USB3RP1_R D- GND
<20> USB3RP1 1 2 0.1U_0402_10V6K~D 12 19 6 12
TX2+ RX2+ SSRX+ GND
4 13
RI55 @ USB3_P1_PIN6 USB3_OS2_P0 USB3RN1_R GND GND
1 2 3.3K_0402_5% 15
OS2
5
SSRX- GND
14
RI54 1 @ 2 3.3K_0402_5% USB3_P1_PIN18 USB3_DE2_P0 16 5 USB3_ERD_P0 10
DE2 EN_RXD <43> USBCHG_DET# Plug_DET
USB3_EQ2_P0 17 14 USB3_CM_P0
RI53 @ USB3_P0_PIN6 EQ2 CM
1 2 3.3K_0402_5% TAIWI_USB006-107CRL-TWD
RI52 1 @ 2 3.3K_0402_5% USB3_P0_PIN18 USB3TN1 CI4 1 2 0.1U_0402_10V6K~D USB3TN1_L 8 23 USB3TN1_RC CI11 1 2 0.1U_0402_10V6K~D USB3TN1_R_C CONN@
<20> USB3TN1 USB3TP1 RX1- TX1-
<20> USB3TP1
CI5 1 2 0.1U_0402_10V6K~D USB3TP1_L 9 22 USB3TP1_RC CI10 1 2 0.1U_0402_10V6K~D USB3TP1_R_C
RI421 @ 4.7K_0402_5%~D USB3_CM_P0 RX1+ TX1+ USB20_P0_CONN
C 2 C
RI431 @ 2 4.7K_0402_5%~D USB3_CM_P1 USB3_OS1_P0 4
RI441 @ 4.7K_0402_5%~D USB3_ERD_P0 USB3_DE1_P0 OS1 USB3_P0_PIN6 USB20_N0_CONN
2 3 6
RI411 @ 4.7K_0402_5%~D USB3_ERD_P1 USB3_EQ1_P0 DE1 GND DI2
2 2
EQ1 GND
10
SN65LVPE502 18 USB3_P0_PIN18 USB3RN1_R 1 10 USB3RN1_R
GND

2
RI191 @ 2 4.7K_0402_5%~D USB3_OS2_P0 25 21
EN== PGND GND

PESD5V0U2BT_SOT23-3~D
RI201 @ 2 4.7K_0402_5%~D USB3_DE2_P0 USB3RP1_R 2 9 USB3RP1_R
RI211 @ 2 4.7K_0402_5%~D USB3_EQ2_P0 PS8713BTQFN24GTR2-A0_TQFN24_4X4
RI221 @ 4.7K_0402_5%~D USB3_OS1_P0
1:normal operation(default) USB3TN1_R USB3TN1_R
2 Vendor PS8710B PCB footprint and CIS symbol use TI 4 7
RI261 @ 2 4.7K_0402_5%~D USB3_DE1_P0 TI 0:sleep mode (SN65LVPE502CPRGER)
pin (default)

DI9
RI231 @ 2 4.7K_0402_5%~D USB3_EQ1_P0 USB3TP1_R 5 6 USB3TP1_R
RI241 @ 4.7K_0402_5%~D USB3_OS2_P1
CM== Compal P/N and value use Parade
2 pin15 AEQ1 OS2
RI251 @ 2 4.7K_0402_5%~D USB3_DE2_P1 0:normal operation(default) (PS8710B) 3
RI301 @ 2 4.7K_0402_5%~D USB3_EQ2_P1 pin16 ADE0 DE2 1:Compliance test mode

1
RI271 @ 2 4.7K_0402_5%~D USB3_OS1_P1 8
RI281 @ 2 4.7K_0402_5%~D USB3_DE1_P1 pin17 AEQ0 EQ2
RI291 @ 2 4.7K_0402_5%~D USB3_EQ1_P1 PS8710 IP4292CZ10-TBR_XSON10_2.5X1~D

USB3_OS2_P0
pin4 BEQ1 OS1 [A(B)_DE1, A(B)_DE0] ==
RI871 @ 2 4.7K_0402_5%~D
RI311 @ 2 4.7K_0402_5%~D USB3_DE2_P0 pin3 BDE0 DE1 LL: 3.5dB de-emphasis
For OPTION reserve
RI361 @ 2 4.7K_0402_5%~D USB3_EQ2_P0
RI401 @ 2 4.7K_0402_5%~D USB3_OS1_P0 pin2 BEQ0 EQ1 LH: No de-emphasis USB3RN1 RI64 1 @ 2 0_0402_5%~D USB3RN1_RL RI72 1 @ 2 0_0402_5%~D USB3RN1_R_C
RI351 @ 2 4.7K_0402_5%~D USB3_DE1_P0 USB3RP1 RI65 1 @ 2 0_0402_5%~D USB3RP1_RL RI73 1 @ 2 0_0402_5%~D USB3RP1_R_C
RI321 @ 4.7K_0402_5%~D USB3_EQ1_P0
HL: 7dB de-emphasis
2 pin5 PD EN_RXD
RI331 @ 2 4.7K_0402_5%~D USB3_OS2_P1 HH: 5dB with boost output swing USB3TN1 RI66 1 @ 2 0_0402_5%~D USB3TN1_RL RI74 1 @ 2 0_0402_5%~D USB3TN1_R_C
RI341 @ 2 4.7K_0402_5%~D USB3_DE2_P1 pin14 TEST CM USB3TP1 RI67 1 @ 2 0_0402_5%~D USB3TP1_RL RI75 1 @ 2 0_0402_5%~D USB3TP1_R_C
RI391 @ 2 4.7K_0402_5%~D USB3_EQ2_P1 [A(B)_EQ1, A(B)_EQ0] ==
RI371 @ 2 4.7K_0402_5%~D USB3_OS1_P1 pin18 ADE1 LL: reserved
RI381 @ 2 4.7K_0402_5%~D USB3_DE1_P1
RI841 @ 4.7K_0402_5%~D USB3_EQ1_P1 LH: program EQ for channel loss up to 7dB USB3RN2 RI60 @ 2 0_0402_5%~D USB3RN2_RL RI68 @ 2 0_0402_5%~D USB3RN2_R_C
2 pin6 BDE1 1 1
HL: program EQ for channel loss up to 14.5dB USB3RP2 RI61 1 @ 2 0_0402_5%~D USB3RP2_RL RI69 1 @ 2 0_0402_5%~D USB3RP2_R_C
RI461 @ 2 4.7K_0402_5%~D USB3_CM_P0 [Parade suggest]
RI471 @ 2 4.7K_0402_5%~D USB3_CM_P1 HH: program EQ for channel loss up to 11.5dB USB3TN2 RI63 1 @ 2 0_0402_5%~D USB3TN2_RL RI71 1 @ 2 0_0402_5%~D USB3TN2_R_C
RI481 @ 2 4.7K_0402_5%~D USB3_ERD_P0 PS8710 AEQ0,BEQ0 adjust 7db, TEST == USB3TP2 RI62 1 @ 2 0_0402_5%~D USB3TP2_RL RI70 1 @ 2 0_0402_5%~D USB3TP2_R_C
RI451 @ 2 4.7K_0402_5%~D USB3_ERD_P1 +3VS
REXT use 3.3 K well get btter test result. L: Normal operation (default)
RI49 1 @ 2 0_0402_5%~D USB3_P0_PIN6 H: Test mode enable CI26
RI50 1 @ 2 0_0402_5%~D USB3_P0_PIN18 0.01U_0402_16V7K~D
1 2 +USB3_VCCB
RI85 1 @ 2 0_0402_5%~D USB3_P1_PIN6 1 2
B +USB3_VCCB B
RI51 1 @ 2 0_0402_5%~D USB3_P1_PIN18
CI25 JUSB2
.1U_0402_16V7K~D USB3TP2_R 9
UI4 SSTX+
1
VBUS

10U_0603_6.3V6M~D
1 7 RI77 1 2 4.99K_0402_1% USB3TN2_R 8 1
VCC NC @ RI76 USB20_P1_CONN SSTX-
13
VCC NC
24 1 2 0_0402_5%~D 3
D+ 1

CI34
7 CI32 +
USB3RN2 CI27 GND
@ RI13 1 2 0_0402_5%~D <20> USB3RN2 1 2 0.1U_0402_10V6K~D USB3RN2_L 11 20 USB3RN2_R_C USB20_N1_CONN 2 10
USB3RP2 CI28 TX2- RX2- D- GND
<20> USB3RP2 1 2 0.1U_0402_10V6K~D USB3RP2_L 12 19 USB3RP2_R_C USB3RP2_R 6 11 220U_6.3V_M
LI6 TX2+ RX2+ SSRX+ GND 2 2
4 12
USB20_N1 USB20_N1_CONN USB3_OS2_P1 USB3RN2_R GND GND
<20> USB20_N1 4 3 15 5 13
4 3 USB3_DE2_P1 OS2 USB3_ERD_P1 SSRX- GND
16 5
USB3_EQ2_P1 DE2 EN_RXD USB3_CM_P1 TAITW_PUBAU5-09FLBS1NN4H0
17 14
USB20_P1 USB20_P1_CONN EQ2 CM CONN@
<20> USB20_P1 1 2
1 2 USB3TN2
<20> USB3TN2
CI23 1 2 0.1U_0402_10V6K~D USB3TN2_L 8
RX1- TX1-
23 USB3TN2_RC CI29 1 2 0.1U_0402_10V6K~D USB3TN2_R_C
DLW21SN900SQ2L_0805_4P~D USB3TP2 CI24 1 2 0.1U_0402_10V6K~D USB3TP2_L 9 22 USB3TP2_RC CI30 1 2 0.1U_0402_10V6K~D USB3TP2_R_C
<20> USB3TP2 RX1+ TX1+
@ RI14 1 2 0_0402_5%~D USB3_OS1_P1 4
USB3_DE1_P1 OS1 USB3_P1_PIN6
3 6
USB3_EQ1_P1 DE1 GND
2 10
EQ1 GND USB3_P1_PIN18
18
GND USB20_P1_CONN
25 21
PGND GND
@ RI17 1 2 0_0402_5%~D PS8713BTQFN24GTR2-A0_TQFN24_4X4 USB20_N1_CONN DI8
PCB footprint and CIS symbol use TI USB3RN2_R 1 10 USB3RN2_R
LI5
(SN65LVPE502CPRGER)

2
USB3TN2_R_C 2 1 USB3TN2_R USB3RP2_R 2 9 USB3RP2_R
2 1 +5VALW Compal P/N and value use Parade

PESD5V0U2BT_SOT23-3~D
(PS8710B) USB3TN2_R 4 7 USB3TN2_R
USB3TP2_R_C 3 4 USB3TP2_R
3 4 USB3TP2_R USB3TP2_R
5 6

DI10
DLW21SN900HQ2L_0805_4P~D 1 1
CI35 CI36 3
@ RI18 1 2 0_0402_5%~D
4.7U_0805_10V4Z 0.1U_0402_16V7K 2.0A 8

1
2 2 +USB3_VCCB
IP4292CZ10-TBR_XSON10_2.5X1~D
UI5
1
GND VOUT
8 80mil
A 2 VIN VOUT 7 A
@ RI15 1 2 0_0402_5%~D 3 6 0_0402_1%
VIN VOUT
EPAD

USB_PWR_EN# 4 5 1 2 USB_OC1# <20>


LI4 <43,53> USB_PWR_EN# EN FLG
USB3RN2_R_C 2 1 USB3RN2_R 1 RI83 @ 1
2 1 CI37 CI38
9

AP2301MPG-13_MSOP8
0.1U_0402_16V7K

USB3RP2_R_C 3 4 USB3RP2_R 0.1U_0402_16V7K


3 4 2 2

DLW21SN900HQ2L_0805_4P~D
@ RI16 1 2 0_0402_5%~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB 3.0/2.0 x2 (left side)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 49 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn 60 pin FFC connector To MB


+5VALW
BTB CONNECTOR TO USB3.0 Board +5VS_TP_LED 1
JP3
1
2 2
10U_0805_10V6K

0.1U_0402_16V4Z~D
3
TP_CLK TP_CLK 3
1 1 <43> TP_CLK 4
4

C48
TP_DATA 5
<43> TP_DATA 5
C47

D TP_DATA D
6
6
<6,12,13,14,15,19,49,50,51> PCH_SMBDATA 7
2 2 7
<6,12,13,14,15,19,49,50,51> PCH_SMBCLK 8
8

3
+5VS +5VALW +5VALW TP_LED_R_DRV# 9
<48> TP_LED_R_DRV# TP_LED_G_DRV# 9
<48> TP_LED_G_DRV# 10
TP_LED_B_DRV# 10
<48> TP_LED_B_DRV# 11
11
12
JIO1 12
13
13
1 2 14
1 2 PESD5V0U2BT_SOT23-3~D VPK_DET# 14
3 4 <43> VPK_DET# 15
3 4 D71 VPK_EN 15
5 6 <43> VPK_EN 16
5 6 16
7 8 Reserve for Key Pad 17

1
7 8 MXM1_FAN_PWM KP_DET# 17
9 10 18
USB20_N2 11
9 10
12 MXM1_FAN_FB MXM1_FAN_PWM <43> (Viking only) 19
18
<20> USB20_N2 USB20_P2 13
11 12
14 RTRON_LED_G_DRV# MXM1_FAN_FB <43> Place close to JP3 +5VS 20
19
<20> USB20_P2 13 14 RTRON_LED_R_DRV# RTRON_LED_G_DRV# <48> 20
15 15 16 16 RTRON_LED_R_DRV# <48> 21 21
USB3TP5 17 18 RTRON_LED_B_DRV# 22
<20> USB3TP5 17 18 RTRON_LED_B_DRV# <48> +3VS 22
USB3TN5 19 20 USB_PWR_EN# 23
<20> USB3TN5 19 20 USB_PWR_EN# <43,52> <19,40,43,54> EC_SMB_DA2 23
21 22 LAN_ACTIVITY# LAN_ACTIVITY# <44> 24
USB3RP5 21 22 LAN_LINK#_R <19,40,43,54> EC_SMB_CK2 24
<20> USB3RP5 23 23 24 24 LAN_LINK#_R <44> 25 25
USB3RN5 25 26 LAN_LED2#_R LAN_LED2#_R <44> 26
<20> USB3RN5 25 26 <20> USB20_P13 26
27 27 28 28 +LAN_IO <20> USB20_N13 27 27
USB20_N3 29 30 LAN_MDIN0 28
<20> USB20_N3 29 30 LAN_MDIN0 <44> 28
USB20_P3 31 32 LAN_MDIP0 LAN_MDIP0 <44> I2C_CLK 29
<20> USB20_P3 31 32 <47,48> I2C_CLK I2C_DAT 29
33 33 34 34 <47,48> I2C_DAT 30 30
USB3TP6 35 36 LAN_MDIN1 LAN_MDIN1 <44> 31
<20> USB3TP6 USB3TN6 35 36 LAN_MDIP1 <48> 7313_INT# 31
<20> USB3TN6 37 37 38 38 LAN_MDIP1 <44> +3.3V_F347 32 32
39 40 <43> KB_DET# KB_DET# 33
USB3RP6 39 40 LAN_MDIN2 KSI0 33
<20> USB3RP6 41 41 42 42 LAN_MDIN2 <44> 34 34
USB3RN6 43 44 LAN_MDIP2 KSI1 35
<20> USB3RN6 43 44 LAN_MDIP2 <44> 35
+3VS 45 46 KSI2 36
USB_OC2# 45 46 LAN_MDIN3 KSI3 36
<20> USB_OC2# 47 47 48 48 LAN_MDIN3 <44> 37 37
C USB_OC3# LAN_MDIP3 KSI4 C
<20> USB_OC3# 49 49 50 50 LAN_MDIP3 <44> 38 38
KSI5 39
KSI6 39
40 40
51 52 KSI7 41
GND1 GND2 KSO0 41
42 42
E&T_1001-F50E-03R KSO1 43
CONN@ KSO2 43
44 44
KSO3 45
+3VS +5VS KSO4 45
46
KSI[0..7] KSO5 46
<43> KSI[0..7] 47
KSO[0..17] KSO6 47
<43> KSO[0..17] 48
48

22U_0805_6.3VAM~D
KSO7 49
KSO8 49
1 50
50

C56
KSO9 51
51

10K_0402_5%~D
KSO10 52
52

2
10K_0402_5%~D

10K_0402_5%~D KSO11 53
53
2

2
2

R55
KSO12 54
54
R56

R57
KSO13 55
KSO14 55
56
KSO15 56
57

1
KSO16 57
58
1

KSO17 58
59 62
MXM1_FAN_PWM 59 G2
60 61
MXM1_FAN_FB MXM1_FAN_FB_D 60 G1
2 1
D66 CVILU_CF25602D0R0-05-NH
SDMK0340L-7-F_SOD323-2~D CONN@

B B

30pin Connector to CardReader


JIO2
1
PCIE_PTX_CARDRX_P4 1
<20> PCIE_PTX_CARDRX_P4 2
PCIE_PTX_CARDRX_N4 2
<20> PCIE_PTX_CARDRX_N4 3
3
4
PCIE_PRX_CARDTX_P4 4
<20> PCIE_PRX_CARDTX_P4 5
PCIE_PRX_CARDTX_N4 5
<20> PCIE_PRX_CARDTX_N4 6
6
7
CLK_PCIE_CD 7
<18> CLK_PCIE_CD 8
CLK_PCIE_CD# 8
<18> CLK_PCIE_CD# 9
9
10
PLT_RST# 10
<6,17,43,44,51> PLT_RST# 11
CDCLK_REQ# 11
<18> CDCLK_REQ# 12
12
+3VALW 13
13
+3VS 14
14
+5VS 15
ON/OFFBTN# 15
+5VALW 16
16
<48> LED_R_7313#_1 17
17
<48> LED_B_7313#_1 18
18
<48> LED_G_7313#_1 19
19
<43> CAPS_LED# 20
20
3

<43> WLES ON/OFF LED# 21


D72 21
<48> HDD_R 22 22
A PESD24VS2UT_SOT23-3~D A
<48> HDD_G 23 23
<48> HDD_B 24 24
<55> ON/OFFBTN# 25 25
LID_SW 26
<48> LID_SW
1

LID_SW_IN# 26
27
Place close to JIO2 <19,43,47,48> LID_SW_IN#
28
27
<48> PWR_G_7313# 28
<48> PWR_R_7313# 29 29
30
<48> PWR_B_7313#
31
30 Security Classification Compal Secret Data
G1
32 G2 Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

ACES_88196-3041
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IO BTB CONN
CONN@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 50 of 61
5 4 3 2 1
A B C D E

www.laptopblue.vn

1 1

+3VS

System FAN Controller

0.1U_0402_10V7K~D
1

C49
2

100P_0402_50V8J~D
SENSOR_DIODE_P1 R46 1 2 0_0402_5%~D REMOTE_P1
1 U5

1
@ C51
1 C 1 8 EC_SMB_CK2 EC_SMB_CK2 <19,40,43,53>
C50 VDD SCLK
2
B 470P_0402_50V7K~D 2 7 EC_SMB_DA2
E Q17 2 D+ SDATA EC_SMB_DA2 <19,40,43,53>

3
2 MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N1 R47 1 2 0_0402_5%~D REMOTE_N1 3 6
D- ALERT#

+3VS R48 1 2 4.7K_0402_5%~D 4 5


THERM# GND
Diode circuit s used for skin temp sensor
(placed between CPU and MXM). ADM1032ARMZ-REEL_MSOP8
Place C51 close to Q17 as possible. Address:100_1100

+3VS +5VS

22U_0805_6.3VAM~D
1

C52
10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D
2

2
2 2
2

R49

R50

R51
1

1
JFAN1
1
SYSTEM_FAN_PWM 1
<43> SYSTEM_FAN_PWM 2
SYSTEM_FAN_FB 2
2 1 3
<43> SYSTEM_FAN_FB D65 3
4
SDMK0340L-7-F_SOD323-2~D 4
5
G5
6
G6
ACES_50273-0040N-001
CONN@

+3VS

MXM1 FAN Controller

0.1U_0402_10V7K~D
1

C53
2

SENSOR_DIODE_P2 R52 1 2 0_0402_5%~D REMOTE_P2


1 U6
1
100P_0402_50V8J~D

1 C 1 8 EC_SMB_CK2
VDD SCLK
C55

3 C54 3
2
B 470P_0402_50V7K~D 2 7 EC_SMB_DA2
E Q19 2 D+ SDATA
3

2
@

MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N2 R53 1 2 0_0402_5%~D REMOTE_N2 3 6


D- ALERT#

+3VS R54 1 2 6.8K_0402_5%~D 4 5


THERM# GND

ADM1032ARMZ-2REEL_MSOP8
Address:100_1101

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thermal Sensor & FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 51 of 61
A B C D E
A B C D E

www.laptopblue.vn
ON/OFF switch
1
IR SENSOR connector TOP Side
SW1
SMT1-05-A_4P
+3VLP
1

1 3 ON/OFFBTN#

Power Button

2
2 4
+5VS
R58

6
5
0.1U_0402_16V4Z~D
100K_0402_5%~D
1

1
C57
D26
2 ON/OFF <43>
<53> ON/OFFBTN# ON/OFFBTN# 1
2

0.1U_0402_25V6K~D
3
JIR1 1

C58
DAN202UT106_SC70-3
1 1 Bottom Side
2 2
3 SW2
3 SMT1-05-A_4P 2
4 4
USB20_N7 5 1 3
<20> USB20_N7 5
USB20_P7 6
<20> USB20_P7 6
2 4
7 GND
8

6
5
2 GND 2

E-T_4260-F06N-10L
CONN@

Pop only for


SSI debug

@ H1 @ H2 @ H3 @ H4
A H_3P5 H_3P5 H_3P5 H_3P5
1

@ H5 @ H6 @ H7 @ H8
B H_3P3 H_3P3 H_3P3 H_3P3

3 3
1

@ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15 @ H16 @ H29


C H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
1

@ H17 @ H18
D H_3P3 H_3P3 @ H34
H_2P0N
FD1 FD2 FD3 FD4
1

ZZZ1 @ @ @ @

1
@ H19 @ H20 @ H21 @ H22
E H_3P8 H_3P8 H_3P8 H_3P8 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

Fiducial Mark
1

PCB-MB
4 4
@ H23 @ H24 @ H25 @ H26 @ H27 @ H30 @ H31 @ H32 @ H33
F H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
Security Classification Compal Secret Data
Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & Power Button & IR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9331P
Date: Friday, June 22, 2012 Sheet 52 of 61
A B C D E
A B C D E

DC to DC www.laptopblue.vn

+5VALW to +5VS +3VALW to +3V_PCH +3VALW to +3VMXM Transfer


+3VALW +3V_PCH
+5VALW +5VS QZ6 +3VALW +3VMXM
QZ1 SI4800BDY-T1-E3_SO8~D UZ2
1 SI4800BDY-T1-E3_SO8~D 1
SI4800BDY-T1-E3_SO8~D 8 1 40mil(1A)

10U_0805_10V4Z~D
8 1 7 2 8 1

10U_0805_10V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D
7 2 6 3 1 7 2

10U_0805_10V4Z~D

1U_0603_10V4Z~D

1U_0603_10V4Z~D

CZ20

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
1 1 6 3 1 1 5 1 1 6 3

CZ1

CZ2

CZ11

CZ12

CZ13
5 1 1 5 1 1

CZ5

CZ3

CZ14

CZ23
4
2

CZ21
4

4
2 2 2 2 2 2
2 2 2 2
RZ30
200K_0402_5%
1 2 +3VMXM_GATE
B+_BIAS

0.1U_0603_25V7K~D

@
1
0_0402_5%~D
QZ8A 1
RZ5

RZ31
CZ22
B+_BIAS 1 2 +5VS_GATE 1 2 +3V_PCH_GATE DMN66D0LDW-7_SOT363-6~D
B+_BIAS
RZ1 102K_0402_1% DGPU_PWR_EN# 2

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
102K_0402_1% 1 1 1

0_0402_5%~D
3

1
2

SSM3K7002F_SC59-3~D

CZ15
D

@
0_0402_5%~D

2
@
CZ4

RZ6
RZ2
DMN66D0LDW-7_SOT363-6~D
QZ2B

QZ5
PCH_PWR_EN# 2
SUSP 5 2 G 2

2
S
4

+1.05V to +1.05VS
+3VALW to +3VS +1.05V +1.05VS
+5VALW to +5VMXM
QZ20
+3VALW +3VS SI4164DY-T1-GE3_SO8~D +5VALW +5VMXM
QZ3 8 1 UZ3
SI4800BDY-T1-E3_SO8~D 7 2 SI4800BDY-T1-E3_SO8~D 100mil(2.5A)

10U_0805_10V4Z~D

10U_0805_10V4Z~D
8 1 6 3 8 1
10U_0805_10V4Z~D

10U_0805_10V4Z~D

1U_0603_10V4Z~D

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
7 2 5 1 1 1 7 2

CZ16
2 1 1 6 3 6 3 1 1 2
CZ6

CZ7

10U_0805_10V4Z~D

1U_0603_10V4Z~D

CZ17

CZ24
5 5

CZ25

CZ26
1 2 2 2

CZ8
1
4

4
2 2 2 2

CZ9
2
B+_BIAS 1 2 +1.05VS_GATE
2 RZ53 RZ32

100P_0402_50V8J~D
B+_BIAS 1 2 +3VS_GATE 330K_0402_5%~D 200K_0402_5%

1 1M_0402_5%~D
RZ3 1 2 +5VMXM_GATE
B+_BIAS
0.1U_0603_25V7K~D

RZ54
102K_0402_1% 1 1 1 1
1

6
SSM3K7002F_SC59-3~D

0_0402_5%~D

SSM3K7002F_SC59-3~D

0.1U_0603_25V7K~D
D D

@
1
@
CZ10

CZ32

0_0402_5%~D
QZ9A 1

RZ33
QZ4

RZ4

QZ7

CZ27
SUSP 2 SUSP 2 DMN66D0LDW-7_SOT363-6~D

2
G 2 G 2 DGPU_PWR_EN# 2
2

S S 2

2
3 3

Discharge Circuit
+1.35V +5VS +1.5VS +3VMXM +5VMXM +5VALW
+3VALW +5VALW

1
1

RZ46
2

1
100K_0402_5%~D

2
RZ37 RZ34 RZ40 RZ36 RZ45
470_0603_5% 470_0603_5% 470_0603_5% RZ35 470_0603_5% @ RZ44 100K_0402_5%~D

2
470_0603_5% 10K_0402_5%~D
2

+3VMXM_D

SUSP
+1.5VS_D

3+5VMXM_D1

2
PCH_PWR_EN#
+1.35V_D

+5VS_D

1
3 3
1 1

SSM3K7002F_SC59-3~D

SSM3K7002F_SC59-3~D
D D
SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

QZ15

QZ16
<35,43> PCH_PWR_EN 2 <10,43,59,61> SUSP# 2
1

D D G G

100K_0402_5%~D
SYSON# 2 SUSP 2

100K_0402_5%~D
1

1
DMN66D0LDW-7_SOT363-6~D
QZ2A

DMN66D0LDW-7_SOT363-6~D
QZ8B

DMN66D0LDW-7_SOT363-6~D
QZ9B

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
G G 1 S 1 S
3 3

@
RZ47
QZ12 S SUSP 2 QZ10 S DGPU_PWR_EN# 5 DGPU_PWR_EN# 5
3

RZ52

CZ28

CZ29
1

2 2

2
+5VALW +5VALW

2
RZ49
100K_0402_5%~D RZ48
+3V_PCH +3VS +1.05VS 100K_0402_5%~D

2
+1.35V_CPU_VDDQ +0.675VS SYSON#

1
1

220_0603_5%~D

22_0603_5%~D

1 DGPU_PWR_EN#
1

SSM3K7002F_SC59-3~D
RZ42 RZ43 D 1
470_0603_5% 470_0603_5%

SSM3K7002F_SC59-3~D
RZ41 D
470_0603_5%
RZ38

RZ39

QZ17
2
2

<43,59,60> SYSON

QZ18
G 2
2

<29,43> DGPU_PWR_EN
+3V_D

G
+1.05VS_D

100K_0402_5%~D
+3VS_D

0.1U_0603_25V7K~D

S
+1.35V_CPU_VDDQ_CHG

100K_0402_5%~D
1

1
3

0.1U_0603_25V7K~D
@

S
RZ50

1 3
+DDR_CHG

@
CZ30

RZ51
6

CZ31
SSM3K7002FU_SC70-3~D

2
DMN66D0LDW-7_SOT363-6~D
QZ11A

2
1

D 2
DMN66D0LDW-7_SOT363-6~D
QZ11B

2
PCH_PWR_EN# 2 SUSP 5 SUSP 2
4 G 4
QZ19 S
1

SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
1

D D
2 2
QZ14

<6,10> RUN_ON_CPU1.5VS3#
G G
QZ13 S S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9331P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 22, 2012 Sheet 53 of 61
A B C D E
A B C D

PL1
VIN +3VALW

C8B BPH 853025_2P

www.laptopblue.vn
ADPIN 1 2

1000P_0402_50V7K

1000P_0402_50V7K
PJPDC1 @

2.2K_0402_5%
100P_0402_50V8J

100P_0402_50V8J
1

1
1 1

2
PC1

PC2

PC3

PC4
2 2
3 3

PR3
4 4 PR4
5 5 33_0402_5%
6 6 Erp lot6 Circuit VIN

1
+DCIN_JACK 3 PSID-3 1
7 7 1

S
1 2 PS_ID <43> 1

PQ7
8 8 FDV301N_NL_SOT23-3~D
9 9

3.3K_1206_5%~D
10 10

G
2
100K_0402_1%
11 11 @

2
PL2
PR8

PR5

PR6
ACES 50493-0110N-001 BLM18BD102SN1D_0603~D @
PSID 2 1 PR7 PSID-2 2 1 +5VALW

2
<17,29,43,47,63> ACIN 1M_0402_1%

32

1
10K_0402_1%

1
C
PSID-1 2 PQ2

2N7002BKS 2N SOT363-6
PQ1B
B

15K_0402_1%
MMST3904-7-F_SOT323~D

1
1

2
5 E

2N7002BKS 2N SOT363-6
@

3
PR9
PR1

2
@ @

1
PQ1A
200K_0402_1% PD1
PR10 @ SM24_SOT23

1
2
BATT+ BATT++ 1M_0402_1%

1
1
@ PC5 @

1
0.1U_0402_25V6
BATT+

2
PL3
C8B BPH 853025_2P
1 2 BATT++
100P_0402_50V8J
1

1
1000P_0402_50V7K
100P_0402_50V8J

0.01U_0402_25V7K
1

PC8

PC9
PC6

PC7

JRTC1
2

@
2

PD5
2 2
2 - + 1 2
1

PD3 3
1 +RTCBATT
B+
3 1
B+_BIAS

100K_0402_1%

0.1U_0402_25V6
0.22U_0603_25V7K
PESD24VS2UT_SOT23-3

1
BAS40CW _SOT323-3

1
PR12

PC10

PC11
PD4
+3VLP
2

LOTES AAA-BAT-054-K01

2
PESD24VS2UT_SOT23-3

2
PBATT1 @
+5VALW PR13 PQ3
TP0610K-T1-E3_SOT23-3
100K_0402_1%
1 1 BATT_TEMP <43,63>
2 1 2 VSB_N_001
2

1VSB_N_003
3 3
4 PR14
4 CLK_SMB PR15 PR16 100K_0402_1%
5 5
6 DAT_SMB 100_0402_5% 10K_0402_1%
6 BATT_PRS PR17
7 1 2 1 2
+3VALW

1
7 SYS_PRES 0_0402_5% D
8 8
9 9 <58> POK 1 2VSB_N_002 2 PQ4
10 PR18 G 2N7002KW _SOT323-3
10 100_0402_5%

.1U_0402_16V7K
11 S

3
11

PC12
12 1 2
12
13 EC_SMB_CK1 <63>
13 PR20

2
2

MOLEX_87437-1342 100_0402_5%
PR19 1 2
0_0402_5% EC_SMB_DA1 <63>
<BOM Structure>
1

3 3

<43,63> ADP_I PH1 under CPU botten side :


CPU thermal protection at 93 +/- 3 degree C

+3VALW +3VLP

2
PR23

2
49.9K_0402_1%
PR24 PR25 @
12.1K_0402_1% 12.1K_0402_1%

1
<43> VCIN0_PH

<43> VCIN1_PH

1
2

PR26 PC13 @
PH1

2
499K_0402_1% .1U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
1
1

4 4

<43> ECAGND

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / BATT CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9331P
Date: Friday, June 22, 2012 Sheet 54 of 61
A B C D
A B C D E

www.laptopblue.vn
PR100
13.7K_0402_1%~D
1 2

1 2 @ PC122

100P_0402_50V8J
@ 100P_0402_50V8J 1 2
PC121 +3VLP
PR101
30.9K_0402_1%
1 1
2 1

1U_0603_10V5K
PR102 PR104

2
0_0603_5%~D
20K_0402_5%~D 20K_0402_5%~D

1
PR103

PC114
1 2 2 1

2
1

59K_0402_1%~D
2
120K_0402_1%~D
B++

PR106
PR105
B++
FB_3V FB_5V

1
1
PL103
1UH_NRS4018T1R0NDGJ_3.2A_30%

2200P_0402_50V7K
1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
PC108

PC109

PC104
PU100

CS2

VFB2

VREG3

VFB1

CS1
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

PC103
0.1U_0402_25V6

PAD 21
1

1
PC110

PC107

3V_EN
FDMC8884_POWER33-8-5

2
EN2
5
PC105

PC106

14 @
VO1

5
2

AON7518 1N DFN
<57> POK PGOOD
@ 19
VCLK
PQ101

PQ102
UG_3V
B+ 4
PC112 PR108
10 DRVH2 TPS51225_QFN20_3X3 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR107 PC111
1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 BST_5V
17 1 2 1 2
1
2
3

2 VBST1 2

3
2
1
SW2 8 PL102
SW2 SW1
18

VREG5
DRVL2

DRVL1
+3VALWP PL101 SW1 3.3UH +-20% PIMB104T-3R3MS 10A
+5VALWP

EN1
VIN
3.3UH_PCMB063T-3R3MS_6.5A_20%
1 2 2 1

11

12

13

5V_EN 20

15
FDMC8878_POWER33-8-5
1

1
150U_B2_6.3VM_R35M

4.7_1206_5%

4.7_1206_5%
LG_3V LG_5V
PR109

PR110
AON6508 1N DFN
1

220U_6.3V_M
PC101

+
1
PQ103

PQ104
1 SNUB_3V 2

PC102
4 4 +
2

1SNUB_5V
2

1U_0603_10V5K
0.1U_0603_25V7K

2
680P_0603_50V7K

680P_0603_50V7K
0_0603_5%~D
1
2
3

3
2
1
1

1
PC117

PC118

PR118
PC116

PC119
2

2
2

2
B++ VL

3 3
3V_EN
3VALWP 1 2

TDC 6.08A PR111 0_0402_5%

Peak Current 8.11A 5V_EN 1 2


OCP current 9.73A PR112 0_0402_5%
PD102 PR113
TYP MAX 2 2.2K_0402_5%
5VALWP
<43> EC_ON
H/S Rds(on) :22mohm , 30mohm 1 1 2 TDC 10.64A
3
L/S Rds(on) :12.1mohm ,17mohm <43> USBCHG_DET_D Peak Current 14.19A
BAS40CW_SOT323-3
OCP current 17.03A
PD100 SBR2U30P1-7_POWERDI123-2
1 2
TYP MAX
<43> VCOUT0_PH#
PJP100 PJP101 H/S Rds(on) 11.2mohm , 14mohm
@ PD101 @ PR115
+3VALWP
1 2 +3VALW +5VALWP 1 2 +5VALW L/S Rds(on) :3.7mohm , 5mohm
LL4148_LL34-2 1M_0402_1%
2 1 1 2
VIN PAD-OPEN 4x4m PAD-OPEN 4x4m
PJP102
402K_0402_1%

4.7U_0603_6.3V6K
1
@ PR116

1 2
1

PC120

PAD-OPEN 4x4m
2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-3VALWP/5VALWP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9331P
Date: Friday, June 22, 2012 Sheet 55 of 61
A B C D E
5 4 3 2 1

www.laptopblue.vn PJP201
+1.35VP
0.675Volt +/- 5%
VLDOIN_1.35V 2 1 TDC 0.7A
Peak Current 1A
B+ @ PJP200 PAD-OPEN1x1m
2 2 1 1
1.35V_B+ 1
PR200
2 BOOT_1.35V OCP Current 1.2A
2.2_0603_5%
JUMP_43X118

SIR472DP-T1-GE3_POWERPAK8-5~D
DH_1.35V

2200P_0402_50V7K
0.1U_0402_25V6
D D

4.7U_0805_25V6-K

4.7U_0805_25V6-K
+0.675VSP

10U_0805_6.3V6M

10U_0805_6.3V6M
1

1
PC206 SW _1.35V

PC202

PC203

PC204

PC205
0.22U_0603_10V7K

1
2

1
DL_1.35V

PC207

PC208
16

17

18

19

20
5
PU200

PQ201

VLDOIN
PHASE

UGATE

BOOT

VTT

2
PAD 21

15 LGATE VTTGND 1
4

14 PGND VTTSNS 2
PL201 PR201
0.68UH_PCMC063T-R68MN_15.5A_20% 6.04K_0402_1%

1
2
3
1 2 1 2 CS_1.35V 13 3
+1.35VP CS RT8207MZQW _W QFN20_3X3 GND

5
4.7_1206_5%

PQ203
PR203 VDDP_1.35V 12 4 VTTREF_1.35V
VDDP VTTREF

SIR818DP-T1_POWERPAK-SO8-5~D
5.1_0603_5%

PR202
1
+ PC201 +5VALW 1 2 VDD_1.35V 11 5
+1.35VP PC209
1 SNUB_1.35V 2
VDD VDDQ

PGOOD
330U_2.5V_M 4 0.033U_0402_16V7~D

TON
2 PC210

FB
S5

S3
1U_0603_10V6K

2
PC211 220P_0402_50V8J~D
680P_0603_50V7K

1
2
3

10

6
C 1 2 C

VDDP_1.35V
+5VALW PR204
PC212

8.06K_0402_1%
2

2
1.35V_FB 2 1
PC213
1U_0603_10V6K PR205

1
1M_0402_1%

2
PR206 1.35V_B+ 1 2

1
0_0402_5% PR207
1 2 S5_1.35V 10K_0402_1% PC214
<43,56,60> SYSON @ @ .1U_0402_16V7K

2
1

PC215 PR208

1
0_0402_5%
1U_0402_6.3VX5R 1 2 S3_1.35V
2

<10,43,56,61> SUSP#

0.1U_0402_10V7K
PC216
1
1.35VP
TDC 13.75A

2
+1.35VP
Peak Current 19.64A
OCP current 23.57A @
TYP MAX
B H/S Rds(on) :12.2mohm , 15mohm B

L/S Rds(on) :2.7mohm , 3.3mohm @


PJP202
@ PJP203
+0.675VS 2 1 +0.675VSP 1 2
+1.35V +1.35VP
PAD-OPEN 4x4m
PAD-OPEN1x1m
@ PJP204
1 2

PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.35VP/0.675VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9331P
Date: Friday, June 22, 2012 Sheet 56 of 61
5 4 3 2 1
5 4 3 2 1

www.laptopblue.vn +1.05VP_B+
@ PJP300
2 2 1 1 B+
JUMP_43X118

+3VS

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
0.1U_0402_25V6
1

1
PC303
PC302

PC304

PC305
2
D D

2
5
PR300
100K_0402_5%

1
4

PC306
PU300 .1U_0603_25V7K PQ301
PR301
1 10 BST_+1.05VP 1 2 2 1 FDMC8884_POW ER33-8-5

3
2
1
PGOOD VBST
PR302 2.2_0603_5%
1 2 TRIP_+1.05VP 2 TRIP DRVH 9 UG_+1.05VP PL301
69.8K_0402_1% 1UH_PCMC063T-1R0MN_11A_20%
PR303 EN_+1.05VP 3 8 SW _+1.05VP 1 2
0_0402_5% EN SW
+1.05VP
<43,56,59> SYSON 1 2 FB_+1.05VP 4 7 +1.05VP_5V
VFB V5IN
+5VALW
RF_+1.05VP 5 6 LG_+1.05VP PC308 1
TST DRVL
1

1
@ 1 2
PC307 11 + PC301
0.22U_0402_16V7K TP 1U_0603_10V6K PR304 330U_2.5V_M
2

TPS51212DSCR_SON10_3X3 4.7_1206_5%
2

2
PR305 4 SNB_1.05VP
470K_0402_1%

1
PQ303 PC309
2

FDMC7692S_POW ER33-8-5
1000P_0402_50V7K

3
2
1

2
C C

PR306

4.99K_0402_1%
2 1
2

PR307
10K_0402_1%
1

@ PJP301
B B
1 2
+1.05V +1.05VP
PAD-OPEN 4x4m
+1.05VP
TDC 4.56A
Peak Current 6.51A
OCP current 7.81A
TYP MAX
H/S Rds(on) :22mohm , 30mohm
L/S Rds(on) :10.8mohm ,13.6mohm

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.05VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9331P
Date: Friday, June 22, 2012 Sheet 57 of 61
5 4 3 2 1
A B C D

www.laptopblue.vn

1 1

PR400
2 1
+1.5VSP
+3VS
TDC 0.66A
10K_0402_5%
Peak Current 0.88A
OCP current 1.06A

PU400 PL401

4
PJP400 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3VALW 2 1 1.5VSP_VIN 10 2 1.5VSP_LX 1 2

PG
PVIN LX +1.5VSP

22P_0402_50V8J
@ PAD-OPEN 1x2m~D 9 3
PVIN LX

1
1

1
4.7_0603_5%
2 2

PC402
PC400 PC401 8 SVIN

PR401
22U_0805_6.3VAM 0.1U_0402_25V6 PR402
6 1.5VSP_FB 30.1K_0402_1%

2
FB

47P_0402_50V8J
22U_0805_6.3VAM

22U_0805_6.3VAM
5

2
EN

PC405
NC

NC
TP

PC403

PC404
0_0402_5% @

11

2
SNUB_1.5VSP
<10,43,56,59> SUSP# 1 2EN_1.5VSP

1
1

.1U_0402_16V7K
PR403

PC406
SYN470DBC_DFN10_3X3 PR405

1
@ PR404 20K_0402_1%
47K_0402_5%

2
2

680P_0402_50V7K
PC407
@

2
@

3 3

PJP401
2 1
+1.5VS +1.5VSP
@ PAD-OPEN 1x2m~D

4
DELL CONFIDENTIAL/PROPRIETARY 4

Compal Electronics, Inc.


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR-1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9331P
Date: Friday, June 22, 2012 Sheet 58 of 61
A B C D
5 4 3 2 1

SIR472DP-T1-GE3_POWERPAK8-5~D
www.laptopblue.vn
+5VS CPU_B+

SIR472DP-T1-GE3_POWERPAK8-5~D
2

2200P_0402_50V7K~D
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K~D
PC501

5
1U_0603_10V6K
0.22U_0603_16V7K PQ501 PQ502

1
1
2

1
0_0402_5%~D

PC502

PC503

PC505

PC506

PC504

PC507
1
PR501

2
+VCCIO_OUT PR500 110_0402_1%~D PR502

2
2 1 2.2_0603_5% 4 4

1
@ PR503 75_0402_5%

2
2 1
D PU501 D

3
2
1

3
2
1
PR504 54.9_0402_1% 6 1 UGATE3
VCC UGATE
2 1
7 2 BOOT3 PL501
FCCM BOOT 0.22UH +-20% PCMB104T-R22MS 35A
PR505 0_0402_5% PWM3 3
PWM PHASE
8 PHASE3 4 1 +VCC_CORE

680P_0603_50V7K
<10> VIDSOUT 1 2 PR507

5
PR506 0_0402_5% 49.9K_0402_1%~D LGATE3 PQ503 PQ504 P3_SW V3N

SIR818DP-T1-GE3_POWERPAK8-5

SIR818DP-T1-GE3_POWERPAK8-5
4 5 3 2
GND LGATE

PC508
<10> VIDALERT_N 1 2 1 2 9
PR508 0_0402_5% TP PR510
<10> VIDSCLK 1 2 PR509 ISL6208BCRZ-T_QFN8_2X2 10K_0603_1%

2
34K_0402_1% 2 1
1 2 4 4 SNB_CPU_P3

4.7_1206_5%

3.65K_0603_1%
ISEN3

10_0402_1%
PR512

PR513

PR514

PR515
PR511 0_0402_5% 24.9K_0402_1% @ PR516
<43> IMVP_VR_ON 1 2 1 2 1_0402_5%

3
2
1

3
2
1
V1N 1 2
+5VALW

1
BOOT2 @ PR518
UGATE2 1_0402_5%

ISUMP
PR519 1.91K_0402_1% PHASE2 V2N 1 2

ISUMN
2 1 SDA PR520
+3VS ALERT# 0_0402_5%~D
<6,17,43> IMVP_PWRGD PC509
1U_0603_10V6K

32
31
30
29
28
27
26
25

VCORE_VDDP 1
PC500
1 2 VCC_core (Base on PDDG rev 0.8)

SDA
ALERT#

SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
1 2 TDC 33A
0.01U_0402_50V7K Peak Current 95A
PR522 SCLK 1 24 LGATE2 @
PR521 0_0402_5%~D VR_ON 2
SCLK
VR_ON
LGATE2
VDDP 23
PR523 DC Load line -1.5mV/A
100K_0402_1% 1 2 VCC_PGOOD 3 22 PWM3 2 1
2 1 IMON 4
PGOOD PWM3
21 LGATE1 0_0402_5%~D Icc_Dyn_VID1 60A
C IMON LGATE1 C

1
PR524
2 VR_HOT#1 NTC
5 VR_HOT# PHASE1 20 PHASE1
UGATE1
OCP current 114A
6 NTC UGATE1 19
0_0402_5%~D COMP 7 COMP BOOT1 18 BOOT1 DCR 0.82m ohm
<43> VR_HOT# PR525 FB 8 17
FB VIN PR526

FB2/VSEN

SIR472DP-T1-GE3_POWERPAK8-5~D

SIR472DP-T1-GE3_POWERPAK8-5~D
1 2 2 1
PH500 0_0402_5%~D
B+

ISUMN
ISUMP
ISEN3
ISEN2
ISEN1
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 33 1 2CPU_B+ PL504

VDD
RTN
+1.05VS @ PR527 PAD FBMA-L11-453215-800LMA90T_1812

0.22U_0603_25V7K
1 2 PR528 CPU_B+ 1 2

2200P_0402_50V7K~D
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K~D
27.4K_0402_1% 9 PU500
10
11
12
13
14
15
16

5
47P_0402_50V8J~D

0_0402_5% 2 1 @ PR529 ISL95812HRZ-T_QFN32_4x4


PC510

1 2 PQ505 PQ506
1

1
PC511

PC512

PC513

PC514

PC515

PC516
2
0_0402_5%
2

2
UGATE2 4 4
2
0_0402_5%

@ PR530
+5VALW
PR531

PC517 1_0402_1%~D
2 1 FB2/VSEN 1 2
PL502

3
2
1

3
2
1
4700P_0402_50V7K~D

39P_0402_50V8J @ 0.22UH +-20% PCMB104T-R22MS 35A


1

1
@ @ PC520 PHASE2 4 1
+VCC_CORE

680P_0603_50V7K
PC519 PR532 PR533 390P_0402_50V7K PC518
COMP 2 1 2 1 FB 2 1 2 1 1U_0603_10V6K PR536 3 2

2
1

1
PC521

PC524
PR534 PQ507 PQ508 3.65K_0603_1% P2_SW

SIR818DP-T1-GE3_POWERPAK8-5

SIR818DP-T1-GE3_POWERPAK8-5
V2N
1800P_0402_50V8F~D 130K_0402_1% 10_0402_1% BOOT2 2 1 1 2 1 2
453_0402_1%

2.2_0603_5% PR538
2

2
1

@ PC523 PR537 PC522 SNB_CPU_P2 10K_0603_1%


0_0402_5%

PR535

2 1 2 1 0.22U_0603_16V7K 1 2
2

1
4.7_1206_5%
PR540

LGATE2 4 4
2

1
4700P_0402_50V7K~D 909_0402_1%

ISUMP
PR541
22P_0402_50V8J~D 2.94K_0402_1% ISEN2
2

2
154K_0402_1%

PR539

@ PR546 PR544
2
2

1.5K_0402_1%
PR542

PR543 1_0402_5% 10_0402_1%


2

PR545

2K_0402_1% V1N 2 1
1

3
2
1

3
2
1

2
B @ PC525 B
2 1

2
39P_0402_50V8J @ PR547
1

2 1

1_0402_5%
1

ISUMN
PC526

V3N 2 1
PC527
1

330P_0402_50V7K~D
1

SIR472DP-T1-GE3_POWERPAK8-5~D

SIR472DP-T1-GE3_POWERPAK8-5~D
PC528
0.15U_0402_10V6K~D CPU_B+

2200P_0402_50V7K~D
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K~D
1 2 1 1 1

100U_25V_M

100U_25V_M

100U_25V_M
PC530
+

PC531
+

PC532
ISEN3 PQ509 PQ510 +

1
PC533

PC534

PC535

PC536

PC537
PC529
0.1U_0603_25V7K~D
ISEN2 PR548 2 2 2
1 2

2
0_0402_5% UGATE1 4 4
1 2
ISEN1 PC538
0.033U_0603_25V7M~D
PC539 1 2 PL503

3
2
1

3
2
1
0.22U_0402_6.3V6K 0.22UH +-20% PCMB104T-R22MS 35A
<10> VCCSENSE
2 1 PHASE1 4 1
+VCC_CORE

680P_0603_50V7K
PR549
PC540 11K_0402_1%

SIR818DP-T1-GE3_POWERPAK8-5
3 2

PC543
0.22U_0402_6.3V6K @ PC541 PR550 PQ511 PQ512 P1_SW

SIR818DP-T1-GE3_POWERPAK8-5
1 2 V1N
2 1 ISUMN 1 2 BOOT1 2 1 1 2
0.082U_0402_16V7K

PR551 2.2_0603_5% PR552 PR553

2
PC545

PC544 330P_0402_50V7K PH501 PC542 SNB_CPU_P1 3.65K_0603_1% 10K_0603_1%


1

0.22U_0402_6.3V6K 10KB_0402_5%_ERTJ0ER103J 2.61K_0402_1% 0.22U_0603_16V7K 1 2 1 2

1
4.7_1206_5%
2 1 1 2 1 2 LGATE1 4 4

PR554
ISEN1
2

1
ISUMP
PC546 @
1 2 @ PR555 PR556
.1U_0402_16V7K

ISUMP V2N 2 1 10_0402_1%


3
2
1

3
2
1

2
1

A A
0.01U_0402_50V7K 1_0402_5%
PC547

ISUMN 2
ISUMN @ PR557
2

V3N 2 1
<10> VSSSENSE
10K_0402_1%

Local sense put on HW site DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9331P
Date: Friday, June 22, 2012 Sheet 59 of 61
5 4 3 2 1
A B C D

VIN VIN P2
Iada=0~4.62A(90W) PQ705 SI7149DP SI7149DP PQ706 P3
PQ702 SI7149DP SI7149DP PQ703 P3
P2
www.laptopblue.vn
1 1
1 1 ADP_I = 19.9*Iadapter*Rsense 2 2
CC = 3.52A (Normal)
2 2 5 3 3 5
5 3 3 5
CV = 13.3V
PR703

4
0.005 +-1% 2512

4
Back_G1 B+ Back_G1 Back_G2

1
Back_G2 1 4 SI7149DP PQ704

200K_0402_1%
3.3_1210_5%

0.1U_0603_25V7K
3

PR702
PQ707 2 3 CSIN 1
2 PR701 1

PC702
PDTA144EU PNP_SOT323

5600P_0402_25V7K~D
2
1

1 1
CSIP 3 5

2
200K_0402_1%

2
CHG_B+
PR704

PL701
1UH_NRS4018T1R0NDGJ_3.2A_30%

4
1 2 PR705
2

Dis_G 200K_0402_1%
3.3_1210_5%

PC703

2200P_0402_25V7K~D
0.1U_0603_25V7K
1 2
1 VIN
1

PQ709

4.7U_0805_25V6-K

4.7U_0805_25V6-K
DDTC115EUA-7-F_SOT323
PR706

PC704

PC705
1

2
V1

10_0402_5%

10_0402_5%
2 VIN 100K_0402_1%
1

1
PR708

PR709

PC706

PC707
PR710
PR711
2 2

PR707 47K_0402_1%

0.1U_0402_25V6K~D

2
150K_0402_1% 1 2 V1

2N7002BKS 2N SOT363-6
PC701

@
2.2U_0805_25V6K

0.1U_0402_25V6K~D
3

1
3
1

2
PQ716B
6

2N7002BKS 2N SOT363-6
2N7002BKS 2N SOT363-6

2
PR712
PQ710A

1
PC708

PC711
<43,57> BATT_TEMP 5 10_1206_1%

2
PQ710B

PC713

0.1U_0402_10V7K
1 2

DDTC115EUA-7-F_SOT323

2N7002BKS 2N SOT363-6
1
1
2

PC710
0.047U_0603_25V7M PC709

1
1

3
1U_0603_10V6K

PQ711
5 1 2

PQ717B
PC712
1

2
@ 1U_0603_25V6K PR713
4

2
VDDP_LDO

4.7_0603_5% 5
VIN 2 1
ISL8731_ICREF PC715 PR714

210K_0402_1%

4
PC714 PR716 VDDP_LDO 1 2

2N7002BKS 2N SOT363-6
2
1000P_0402_50V7K 0_0603_5% 0.1U_0603_25V7K

28

27

SIR472DP-T1-GE3_POWERPAK8-5~D
1

6
PR715
PU700 2BST_CHGA 10K_0402_5%
100K_0402_1%

1 2 1 1 2
PR717

PQ717A
ICREF

CSSP

CSSN
2
DCIN 22 26 PQ701 2

DCIN ICOUT PC716 <43> ACOFF 2

1
1 PR719
2 ACSETIN 2
2

ACIN

5
PR720 49.9K_0402_1% 25 BST 1 2
BOOT

1
47K_0402_5%
<17,29,43,47,57> ACIN ACIN 13 ACOK
ACIN 1 2 +5VALW 1U_0603_10V6K
1
158K_0402_1%

11 VDDSMB
PR722
0.1U_0402_10V7K
DDTC115EUA-7-F_SOT323

PR721

0_0402_5% 10 4
<57> EC_SMB_CK1 SCL
1

1
PC717

2 1
9 21 VDDP_LDO
2

PR724 SDA VDDP


2

PR723 0_0402_5% 14 PR725

3
2
1
<57> EC_SMB_DA1 NC
PQ713

1 2 2 2 1 24 DH_CHG PL702 0.01_1206_1%


UGATE
8 VICM
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D BATT+
10K_0402_5% 23 LX_CHG 1 2 CHG
1 4
PHASE

4.7_1206_5%
6 FBO
2 3
2N7002BKS 2N SOT363-6

1
ACOFF ISL8731_EAJ 5 PQ714

FDMC7692S_POWER33-8-5
EAI
6

PR728
PQ718A

DL_CHG
4.7K_0402_5%

4 EAO LGATE 20

10U_0805_25V5K~D

10U_0805_25V5K~D

10U_0805_25V5K~D

10U_0805_25V5K~D
2

0_0402_5%
10_0402_5%
7> BATT_TEMP 2 @

1
PR730

PC720

PC721

PC722

PC723
PR729 SNUB_CHG
100_0402_1% ISL8731_REF 3 19 4
1

VREF PGND

PR731

PR732
680P_0402_50V7K
18
0.01U_0402_25V7K

2
CSOP

PC719
@
33K_0402_1%~D
1

1
PC735

7 17

2
CE CSON
PR738

3
2
1
@ 15 VFB 1 PR734 2 BATT+ @
2

VFB
33K_0402_1%~D

<43,57> ADP_I 12 GND 100_0402_5%


0.1U_0402_10V7K

16
2

@ NC PC726
3

29 TP
<6,43> H_PROCHOT# ISL8731_REF 1 2
1

1
PC728

ISL8731_ICREF @
PR735

ISL88731CHRTZ-T_QFN28_5X5~D 0.22U_0603_25V7K
1

PC731
2

@ PC729 @
33K_0402_1%~D

1 2
2

1U_0603_25V6K
0.01U_0402_25V7K

0.01U_0402_25V7K
2

1 2

PR739

PC732 0.1U_0402_25V6K~D
33K_0402_1%~D
1

1
PC733

@ PC734

.1U_0402_16V7K @
1

PR736
2

2
2
1

D
<43,57> BATT_TEMP 2 PQ715 @ @
G SSM3K7002FU_SC70-3
S
3

PR740
0.004_2512_1% PL703
For DT Mode SMB3025500YA_2P
B+_MXM 1 4 1 2 B+
VIN 2 3
V1 1 1
100U 25V M

100U 25V M

+
PC736

+
2N7002BKS 2N SOT363-6 3.3K_1206_5%~D

PC737

@
2N7002BKS 2N SOT363-6
1

2 2
PR737

PQ716A

4 4
<43,57> BATT_TEMP 2 <29> VIN-
2

<29> VIN+
1
3

PQ718B

<43> ACOFF 5
Security Classification Compal Secret Data Compal Electronics, Inc.
4

Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9331P
Date: Friday, June 22, 2012 Sheet 60 of 61
A B C D
5 4 3 2 1

Based on PDDG rev 0.8 Table 5-1.


www.laptopblue.vn
+VCC_CORE +VCC_CORE

1 1 1 1 1
D 1 1 1 1 1 D
+ PC905 + PC906 + PC907 + PC908 + PC915
PC900 PC901 PC902 PC903 PC904
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D
2 2 2 2 2 2 2 2 2 2

1 1 1 1 1 1
PC909 PC910 PC911 PC912 PC913 PC914
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM
2 2 2 2 2 2

+VCC_CORE
1 1 1 1 1
PC917 PC918 PC919 PC920 PC921
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

C 1 1 1 1 1 C

PC922 PC923 PC924 PC925 PC926


22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1 1
PC935 PC936 PC937 PC938 PC939
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1
PC940 PC941 PC942 PC943
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9331P
Date: Friday, June 22, 2012 Sheet 61 of 61
5 4 3 2 1
www.laptopblue.vn

www.s-manuals.com

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