CHAPTER 8

FET Amplifiers
Small Signal Model
▪ The gate-to-source voltage controls the drain-to-source (channel)
current of a JFET.
▪ The change in drain current that will result from a change in gate-
to-source voltage.

The relationship of a change in Id to the corresponding change in Vgs

is called Transconductance gm.
▪ gm is a slope at Q-point.
▪ gm increase as we progress from Vp to
IDSS. In other words, as Vgs approaches
0V, the magnitude of gm increases.
▪ The derivative of a function at a point is equal to the slope of the
tangent line drawn at that point.
▪ Deriving the gm.

▪ where |VP| denotes magnitude only,

to ensure a positive value for gm
Plotting gm Versus Vgs

▪ the maximum value of gm occurs where VGS

is 0 V and the minimum value at VGS = VP.
The more negative the value of VGS the less
the value of gm .
JFET Input Impedance Zi
JFET Output Impedance Zo
▪ The output impedance of JFETs is similar in magnitude to that of
conventional BJTs
JFET Output Impedance Zo
▪ The more horizontal the curve, the
greater is the output impedance.
▪ If it is perfectly horizontal, the ideal
situation is on hand with the output
impedance being infinite (an open
circuit)—an often applied
approximation
▪ The current source has its arrow
pointing from drain to source to
establish a 180° phase shift between
output and input voltages as will
occur in actual operation.

▪ Input impedance is represented by

the open circuit at the input terminals

▪ Output impedance by the resistor d r

from drain to source
- both capacitors have the short-circuit equivalent
because the reactance is sufficiently small
compared to other impedance levels of the
network, and the dc batteries VGG and VDD are
set to 0 V by a short-circuit equivalent.
- infinite input impedance at the input
terminals of the JFET

- If the resistance rd is sufficiently large (at least

10:1) compared to RD , the approximation
rd||RD ≅ RD can often be applied and
- The fixed-bias configuration has the distinct disadvantage of requiring two dc
voltage sources. The self-bias configuration requires only one dc supply to
establish the desired operating point.

2 types
• Bypassed RS
• Unbypassed RS
Bypassed RS
- Reduced the network to lower level of complexity.
Bypassed RS
- Since the resulting
configuration is the
same as appearing in
Fig. 8.12 , the
resulting equations for
Zi , Zo , and Av will be
the same.
Unbypassed RS
- there is no obvious way to reduce the
network to lower its level of complexity.

- In determining the levels of Zi , Zo , and

Av , one must be very careful with
notation and defined polarities and
direction.

- Due to the open-circuit condition

between the gate and the output
network, the input remains the
following:
Unbypassed RS
The output impedance is defined by

CASE 1.
When rd is not present in the network, then the
Zo;
Unbypassed RS
CASE 2.
When rd is included in the network, then the Zo;

Expressing for Io in terms of ID.

Apply KCL @ a
Unbypassed RS

Substitute;
Unbypassed RS
For the value of Av

Apply KVL @ a

voltage across rd using Kirchhoff’s

voltage law - application of Kirchhoff’s current law
results in
Unbypassed RS
Substitute;
The values are the same as obtained for the fixed-bias and self-
bias (with bypassed R S ) configurations. The only difference is that
they are sensitive to the parallel combination of R1 and R2.
 Substituting the JFET common-gate configuration
to AC equivalent circuit for analysis

- the controlled source gmVgs be

connected from drain to source with
rd in parallel.
- the resistor connected between input
terminals is no longer RG , but the
resistor RS connected from source to
ground.
Input impedance Zi
- KVL @ a

- KCL @ a
Input impedance Zi

If rd ≥ 10RD
Output impedance Zo

Substituting Vi = 0V in Fig. 8.25 will “short-out” the effects of

RS and set Vgs to 0 V. The result is gmVgs = 0, and rd will be in
parallel with RD

If rd ≥ 10RD
Output impedance Zo

Substituting Vi = 0V in Fig. 8.25 will “short-out” the effects of

RS and set Vgs to 0 V. The result is gmVgs = 0, and rd will be in
parallel with RD

If rd ≥ 10RD
 For Av

Note that,

KCL @ b

Voltage and current across rd

For Av

If rd ≥ 10RD
 JFET equivalent of the BJT emitter-follower
configuration is the source-follower configuration.

AC equivalent of the JFET source-

follower configuration.
 Since gmVgs, rd, and RS are connected to
the same terminal and ground;

Input impedance will be

Output impedance Zo
Applying KCL @ node S
Output impedance Zo
• Shockley’s equation is also applicable
to depletion-type MOSFETs

• The only difference offered by D-

MOSFETs is that VGSQ can be positive
for n -channel devices and negative for p
-channel units.
• enhancement-type MOSFET (E-
MOSFET) can be either an n -channel
(nMOS) or p -channel (pMOS) device

• the relationship between output

current and controlling voltage is
defined by
 Constant k can be determined from a given typical operating point on a
specification sheet. The characteristics of an E-MOSFET are such that the
biasing arrangements are somewhat limited.
Next reporter will continue the remaining topic for FET small signal
analysis