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Kiran P PE B180894EE EXP2
Kiran P PE B180894EE EXP2
1. Transfer characteristics
Circuit diagram
Graph
14
Graph
3. Collector to emitter voltage vs gate to emitter voltage
Circuit diagram
14
Graph
Graphs
V(n001) denotes the gate-emitter voltage while V(n004) denotes the collector-
emitter voltage.
a. Trise
Time taken for VCE to go from 10% to 90% of its maximum value.
Trise = 382.56ns
b. Tfall
Time taken for VCE to go from 90% to 10% of its maximum value.
Tfall = 625.13ns
c. Ton
Time interval between 10% of VGE(max) and 10% of VCE(max).
Ton = 2.52µs
d. Toff
Time interval between 90% of VGE(max) and 90% of VCE(max).
Ton = 3.55µs
Circuit diagram – with parasitic inductances
Graphs
Where V(n001) denotes the gate-emitter voltage and V(n005) denotes the
collector-emitter voltage.
a. Trise
Time taken for VCE to go from 10% to 90% of its maximum value.
Trise = 3µs
b. Tfall
Time taken for VCE to go from 90% to 10% of its maximum value.
Tfall = 3.26µs
c. Ton
Time interval between 10% of VGE(max) and 10% of VCE(max).
Ton = 6.07µs
d. Toff
Time interval between 90% of VGE(max) and 90% of VCE(max).
Ton = 7.72µs
RESULTS
1. The transfer characteristics of the given IGBT has been plotted and the
threshold voltage was determined from the graph to be 5.543V.
2. The output characteristics of the same IGBT has been plotted.
3. Collector to emitter voltage versus gate to emitter has been plotted and
the on state voltage corresponding to 14 V is 1.75V
4. Switching characteristics has been plotted.
Without parasitic With parasitic
Parameter
inductances inductances
Trise 382.56ns 3µs
Tfall 625.13ns 3.26µs
Ton 2.52µs 6.07µs
Toff 3.55µs 7.72µs