FPGA Based Implementation of 16-Bit ALU

Mini Project 2 B Report

Submitted in partial fulfillment of the requirement of University of
Mumbai For the Degree of
(Electronics & Telecommunication Engineering)

By

1) “Akash Gupta” “ID No: TU2S2021020”

2) “Sandeep Ray” “ID No: TU2S2021021”
3) “Aditya Jadhav” “ID No: TU2S2021018”
4) “Pravin Pawar” “ID No: TU2S2021023”

Under the Guidance

of Prof. Saurabh Tejpal

Department of Electronics and Telecommunications Engineering

TERNA ENGINEERING COLLEGE

Plot no.12, Sector-22, Opp. Nerul Railway

station, Phase-11, Nerul (w), Navi Mumbai
400706 UNIVERSITY OF MUMBAI
 TERNA ENGINEERING COLLEGE, NERUL,

NAVI MUMBAI
Department of Electronics & Telecommunication
Engineering
Academic Year 2020-21

CERTIFICATE
This is to certify that the mini project 2 A entitles “ FPGA based Implementation of 16-Bit
ALU ” is a bonafide work of

1) “Akash Gupta” “ID No: TU2S2021020”

2) “Sandeep Ray” “ID No: TU2S2021021”
3) “Aditya Jadhav” “ID No: TU2S2021018”
4) “Pravin Pawar” “ID No: TU2S2021023”

submitted to the University of Mumbai in partial fulfillment of the requirement for the
award of the Bachelor of Engineering (Electronics & Telecommunication Engineering).

Guide Head of Department Principal

Project Report Approval

This Mini Project 1 A Report – entitled “FPGA based Implementation of 16-Bit ALU” by
following students is approved for the degree of B.E. in "Electronics and
Telecommunications Engineering".

Submitted by:

1)“Akash Gupta” “ID No: TU2S2021020”

2)“Sandeep Ray” “ID No: TU2S2021021”
3)“Aditya Jadhav” “ID No: TU2S2021018”
4)“Pravin Pawar” “ID No: TU2S2021023”

Examiners Name & Signature:

1.---------------------------------------------------------

2.----------------------------------------------------------

Date:

Place:
 Declaration

We declare that this written submission represents our ideas in our own words and where
others' ideas or words have been included, we have adequately cited and referenced the
original sources. We also declare that we have adhered to all principles of academic honesty
and integrity and have not misrepresented or fabricated or falsified any idea/data/fact/source
in our submission. We understand that any violation of the above will be cause for
disciplinary action by the Institute and can also evoke penal action from the sources which
have thus not been properly cited or from whom proper permission has not been taken when
needed.

“Akash Gupta” “ID No: TU2S2021020”

---------------------------

“Sandeep Ray” “ID No: TU2S2021021”

---------------------------
“Aditya Jadhav” “ID No: TU2S2021018”
---------------------------
“Parvin Pawar” “ID No: TU2S2021023”

Date:
Place:
 Acknowledgement

We would like to express our sincere gratitude towards our guide Pro. Saurabh Tejpal, Mini
Project Coordinator Prof. Vijaypal Yadav for their help, guidance and encouragement, they
provided during the project development. This work would have not been possible without
their valuable time, patience and motivation. We thank them for making our stint thoroughly
pleasant and enriching. It was great learning and an honor being their student.

We are deeply thankful to Dr. Jyothi Digge (H.O.D Electronics and Telecommunications
Department) and entire team in the Electronics and Telecommunications Department. They
supported us with scientific guidance, advice and encouragement, they were always helpful
and enthusiastic and this inspired us in our work.

We take the privilege to express our sincere thanks to Dr. L. K. Ragha our Principal for
providing the encouragement and much support throughout our work.

“Akash Gupta” “ID No: TU2S2021020” ---------------------------

“Sandeep Ray” “ID No: TU2S2021021”
---------------------------
“Adtiya Jadhav” “ID No: TU2S2021018”
---------------------------
“Pravin Pawar” “ID No: TU2S2021023”

Date:
Place:
 Index

TABLE OF CONTENTS

Sr. No. Title Page No.

Abstract 2

List of Figures 3

Chapter 1 Introduction 7
1.1 Arithmetical Operations 8
1.2 Logic operations 9

Chapter 2 Problem Statement 11

Chapter 3 Literature Survey 13

Chapter 4 Design and Implementation

4.1 Pre-Processing 14
4.2 Design Flow Overview 14
4.3 Design Entry
14
4.4 Design Simulation
14
4.5 Design Synthesis
14
4.6 Functional and Timing Simulation
4.7 Design Implementation 14

4.8 Block Diagram 15

4.9 Flow Chart 16

Chapter 5 Results 17
Chapter 6 Application and Advantages 18
Chapter 7 Conclusion and future Scope 19

Reference 20
 Abstract

In this paper VHDL implementation of 16 Bit ALU is proposed to be implemented. With help of 5 select lines,
it has the ability to give the output for 32 different functions. Right from the basics of logical operations such as
AND , OR , XOR to Arithmetics like Addition and Subtraction; to higher operations such as binary to gray and
concept of Floating Point operations. Floating point operations of addition, subtraction and multiplication will
be performed along with use of new Floating point Format
Keywords—VHDL, ALU, 16 Bit, Floating Point, new format

7
 List of Figures

Sr.no Name of Figure Pg.no

Fig 1.1 FPGA Board 5
Fig 1.2 Symbol of 16 bit ALU 7
Fig 4.8 Block Diagram of 16 bit ALU 15
Fig 4.9 Flow Chart 16

8
 Vivado 2021.2

Xilinx's Vivado Design Package is a software suite for synthesis and analysis of hardware
description language designs that replaces Xilinx ISE with extra functionality for system on a
chip development and high-level synthesis. Vivado is a complete rebuild and rethinking of the
whole design flow. Vivado Simulator is a mixed-language simulator that can handle VHDL and
Verilog simulation models. If you use different simulators and only have a licence for one
language, adjust the simulator language to match your licence.

FPGA

FPGAs are often used as implementation platforms for real-time image processing applications
because their structure is able to exploit spatial and temporal parallelism. The approach used is a
windowing operator technique to traverse the pixels of an image, and apply the filters. FPGA
image processing performs compute-intensive video and image processing using dedicated
hardware that delivers low latency and high throughput computation. These techniques often
involve pre-processing an incoming video stream for further processing in software or a deep
learning network to them.

9
 Fig1.1 FPGA BOARD

NEXYS 4DDR FPGA BOARD

The Nexys 4 DDR board is a complete, ready-to-use digital circuit development platform based
on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx®. With its large,
high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external
memories, and collection of USB, Ethernet, and other ports, the Nexys4 DDR can host designs
ranging from introductory combinational circuits to powerful embedded processors. Several
built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone,
a speaker amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range
of designs without needing any other component

10
 What is included?

 The Nexys4 DDR board featuring the XC7A100T-1CSG324 FPGA

 Micro-USB cable

 Can be used to power the board

Suggested use of this board

 Student projects using any of the built-in features of the board

 Creating embedded system

 Design circuits which require more than 8 LEDs

 Modeling processor whose output can utilize eight 7-segments displays

 System design utilizing multiple (more than eight) bits input/output

Artix-7 FPGA Features

 99K logic cells (15,850 logic slices, each with four 6-input LUTs and 8 flip-flops)

 4,860 Kbits of fast block RAM

 Six clock management tiles, each with phase-locked loop (PLL)

 Internal clock speeds exceeding 450MHz

11
 Chapter 1: Introduction

The Design and implementation of FPGA based Arithmetic Logic Unit is of core significance in digital
technologies as it is an integral part of central processing unit.
ALU is capable of calculating the results of a wide variety of basic arithmetical and logical
computations. The ALU takes, as input, the data to be operated on (called operands) and a code, from
the control unit, indicating which operation to perform. The output is the result of the computation.
Designed ALU will perform the following operations:
 Arithmetic operations
 Bitwise logic operations

All the modules described in the design are coded using VHDL which is a very useful tool with its
degree of concurrency to cope with the parallelism of digital hardware. The top level module connects
all the stages into a higher level at Register Transfer Logic (RTL). RTL describes the requirements of
data and control units in terms of digital logic to execute the desired operations. Each instruction from
the architecture's instruction set is defined in detail in the RTL. Once identifying the individual
approaches for input, output and other modules, the VHDL descriptions are run through a VHDL
simulator and then is downloaded the design on FPGA board for verification. As FPGA has an
application that it can incorporates much logic on a single FPGA. So as floating point ALU has many
operations to be performed in the computer we are using an FPGA IC to implement it. The operations
performed by the FPU are addition, subtraction, multiplication, division and logical operations as AND,
OR, NOT etc. FPU mainly work on Real as well as integers value. FPGA is an integrated circuit
designed to be configured by the customers or designer after manufacturing-hence “Field
Programmable”. The FPGA configuration is generally specified using a hardware description language,
similar to that used for an application specific integrated circuit (ASIC). FPGA contain programmable
logic components called “Logic Blocks”, and a hierarchy of reconfigurable interconnects that allows
the block to be wired together. Logic blocks can be configured to perform complex combinational
function or merely simple logic gates like AND and OR. In most FPGA’s, the logic blocks also
include memory elements which may be simple flipflops or more complete blocks of memory.

Fig.1.2 Symbol of 16 bit ALU

12
1.1 ARITHMETICAL OPERATIONS

1.1.1 ADDITION

Addition is the basic operation of arithmetic. In its simplest form, addition combines two numbers, the
addends or terms, into a single number, the sum of the numbers. Adding more than two numbers can be
viewed as repeated addition; this procedure is known as summation and includes ways to add infinitely
many numbers in an infinite series; repeated addition of the number one is the most basic form of
counting.

1.1.2 SUBTRACTION

Subtraction is one of the four basic arithmetic operations; it is the inverse of addition, meaning that if
we start with any number and add any number and then subtract the same number we added, we return
to the number we started with. Subtraction is denoted by a minus sign in infix notation.

1.1.3 MULTIPLICATION

Multiplication is the second basic operation of arithmetic. Multiplication also combines two numbers
into a single number, the product. The two original numbers are called the multiplier and the
multiplicand, sometimes both simply called factors.

1.1.4 DIVISION

Division is essentially the opposite of multiplication. Division finds the quotient of two numbers, the
dividend divided by the divisor. Any dividend divided by zero is undefined. For positive numbers, if
the dividend is larger than the divisor, the quotient is greater than one, otherwise it is less than one (a
similar rule applies for negative numbers). The quotient multiplied by the divisor always yields the
dividend.

1.1.5 REMAINDER

The binary operator is said to yield the remainder of its operands from an implied division; the left-
hand operand is the dividend and the right-hand operand is the divisor.

1.1.6 MODULUS

In computing, the modulo operation, sometimes also called "remainder" or "rest", gives the remainder
from a division. It finds the remainder of division of one number by another. Given two numbers, a (the
dividend) and n (the divisor), a modulo n abbreviated as a mod n) is the remainder, on division of a by
n. For example, if you divide 7 by 3, 3 goes in 7 two times. But there is a remainder of 1, and that is the
result of the modulo
operation.
1.1.7 UNARY ADDITION/SUBTRACTION

Unary addition and subtraction operators are unary operators that add or subtract one from their
operand, respectively. They are commonly implemented in imperative programming languages. The t
operator creases the value of its operand by 1. The operand must have an arithmetic data type, and must
refer to a modifiable data object. Similarly, the decrement operator decreases the value of its modifiable

13
arithmetic operand by 1.

1.1.8 EXPONENTIAL

In mathematics, the exponential function is the function ex, where e is the number (approximately
2.718281828) such that the function ex is its own derivative.[1][2] The exponential function is used to
model phenomena when a constant change in the independent variable gives the same proportional
change (i.e.. percent increase or decrease) in the dependent variable. The function is often written as
exp(x), especially when it would be impractical to write the input expression as an exponent.

1.2 LOGICAL OPERATIONS

1.2.1 AND

A bitwise AND takes two binary representations of equal length and performs the logical AND
operation on each pair of corresponding bits. In each pair, the result is 1 if the first bit is 1 AND the
second bit is 1. Otherwise, the result is 0.

1.2.2 OR

A bitwise OR takes two bit patterns of equal length, and produces another one of the same length by
matching up corresponding bits (the first of each; the second of each; and so on) and performing the
logical inclusive OR operation on each pair of corresponding bits. In each pair, the result is 1 if the first
bit is 1 OR the second bit is IOR both bits are 1, and otherwise the result is 0. For example:

1.2.3 NOT

The bitwise NOT, or complement, is a unary operation that performs logical negation on each bit,
forming the ones' complement of the given binary value. Digits which were 0 become 1. and vice versa.

1.2.4 NAND

A bitwise NAND takes two binary representations of equal length and performs the logical NAND
operation on each pair of corresponding bits. In each pair, the result is 0 if the first bit is 1 AND the
second bit is 1. Otherwise, the result is 1.

1.2.5 NOR

A bitwise NOR takes two bit patterns of equal length, and produces another one of the same length by
matching up corresponding bits (the first of each; the second of each. and so on) and performing the
logical inclusive OR operation on each pair of corresponding bits. In each pair, the result is 1 if the both
bits are zero otherwise the result is Q. For example:

1.2.6 XOR

A bitwise exclusive or takes two bir patterns of equal length and performs the logical XOR operation
on each pair of corresponding bits. The result in each position is lif the two bits are different, and 0 if
14
they are the same.

1.2.7 VHDL

VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed
by a synthesis program, only if it is part of the logic design. A simulation program is used to test the
logic design using simulation models to represent the logic circuits that interface to the design. This
collection of simulation models is commonly called a testbench.

15
 Chapter 2: Problem statement

2.1 Problem Statement: ALU design

2.1.1 Part I:

In this section of Homework 3, you will be designing a 16-bit Arithmetic Logic Unit (ALU) with
following specifications using VHDL.

1. ALU has two 16-bit inputs operands

2. ALU performs operations such as addition, subtraction, AND & XOR on the two input operands
depending on control lines.
3. The operands can be both positive and negative.

4. ALU provides an overflow error when the result of any operation exceeds range of output word.
5. Your design must have the same input and output port names as those in Figure 1

1.2 Part II:

Simulate the above created ALU in Model Sim. To know more about simulating your design with
Model Sim, please refer to the “Model Sim Tutorial ”, posted on course website. This tool can be found
on the computers in Lab 320 and Lab 310. You can also access this tool remotely using linux servers.
Additional information on Model Sim can be found at
http://www.eng.auburn.edu/department/ee/mgc/quickvhdl/modelsim.html

What to submit?

1. A report which contains a List output of ALU simulations (Do not include your code). Highlight
the time instances which verify the functionality of ALU in List output.

2. Comment your code appropriately and email it to TA. Mention your name at the top of your file
as a comment.

Once the ALU design is ready and has been thoroughly tested in Model Sim, we are ready to synthesize
and test the design in FPGA. The complete setup of the design required to test the ALU is as shown in
Figure 1. You have to design only ALU. Other components in the figure have already been designed
and will be provided to you as a wrapper (hw3.zip) on course website. You have to add the above
designed ALU in the project folder.
However, it is advised that you go through VHDL description of all other components as well and

16
understand the port mapping in top level design. This understanding is crucial for successfully
completing the class project on ‘CPU design’ which will be assigned shortly.

1. To create a new project and synthesize the design in Altera FPGA, go through “Altera Quartus II
and DE2 manual ”. The Quartus II software has been updated recently.
So you might find the screen shots from tutorial a little different from what you are observing on
the screen but the contents are the same. After you have created the project, BEFORE YOU
COMPILE, go through “Run time content editable memory tutorial ”. Since the memories have
already been created and provided to you in hw3.zip folder, you only need to complete step 8
from this tutorial.

2. Also, you need to do following pin assignments by referring to Altera Quartus II and DE2 manual

• clk ⇒ KEY0
• Addr0[4-0] ⇒ [SW4 - SW0]
• Addr1[4-0] ⇒ [SW9 - SW5]
• func[1-0] ⇒ [SW17 - SW16]
• disp0 ⇒ HEX0
• disp1 ⇒ HEX1
• disp2 ⇒ HEX2
• disp3 ⇒ HEX3
• ovrfl ⇒ LEDR17

3. Memory initialization files (RAM INIT.MIF ) for both the memories have been provided in the
zip folder. If the memories are not being initialized to the values specified in initialization files
then mention the complete path name of the file on line number 93 in mem0.vhd and mem1.vhd
files. Notice that Altera Quartus II uses forward slashes in the path as against backward slashes
used by Windows.

4. How to test the design?

 Once you have successfully synthesized and downloaded the design in FPGA, the memory now
contains data specified in the initialization files. This can be verified by following steps 10, 11,
12 from Run time content editable memory tutorial.
 Now select the addresses for both the memories and choose a function for ALU. Press clock
once. You should see the result of the operation on the displays.
 Verify this result. Apply different functions and operands (various memory words) and check
whether ALU functions correctly.

5.Altera DE2 boards can be found in Lab 320. Please go through the above manual carefully before
using the boards. After you have successfully tested your design on FPGA, you need to demonstrate it
to your TA.

17
 Chapter 3: Literature Survey

Published in IJERT Vol. 2 Issue 7, July 2013 by Supraj Gaonkar and Anitha M. In this paper, the
behavioral design and functional characteristics of 16-bit is proposed, which utilizes minimum
functional units without compromising in performance. The design is based on Harvard architecture.
All modules in the design are coded in Verilog. The individual modules are designed and tested at each
level of implementation and finally integrated in a top-level module. The tools used are Xilinx ISE 10.1
and Model Sim 10.2.

Presented in the 2018 Fourth International Conference on Computing Communication Control and
Automation (ICCUBEA) by Shraddha M. Bhagat and Sheetal U. Bhandari This paper is available on
IEEE Xplore and the design of a 16-bit is explained using Verilog HDL. It comprises of various blocks
such as ALU, Controller, register files and data memory unit. It is based on the simple Von Neumann
architecture which has a single shared memory for instructions and data. It consists of 15 instructions.
The processor is analyzed using Xilinx ISE tool.

18
 Chapter 4: Design and Implementation

4.1 Pre-Processing:-

The sequences of pre-processing steps are as follows

4.2 Design Flow Overview:-

Xilinx tools can be installed on your own PC so that you can draw schematics or write the code, perform
simulations without coming to the lab. You may download a free, compatible version from the Xilinx web page
called Vivado 2021.2

The design steps are explained here.

4.3 Design Entry:-

The first step is to enter your design. This can be done by creating "Source" files. Source files can be created in
different formats such as a schematic, or a Hardware Description Language (HDL) such as VHDL, Verilog. A
project design will consist of a top-level source file and various lower level source files. Any of these files can
be either a: schematic or a HDL file.

4.4 Design Simulation:-

Verification of the functionality can be done using Behavioral Simulation. Create a test bench waveform
containing input stimulus you can use to verify the functionality your module.

4.5 Design Synthesis:-

The synthesis step creates EDIF or NGC netlist files from the various source files. The netlist files can serve as
an input to the implementation module. Popular synthesis tools include: Synplify, Precision, PGA Compiler II,
and XSTgn.

19
4.6 Functional and Timing simulation:-
Design verification can be done at various stages. The simulator is used to verify the functionality of a design
(functional simulation), the behavior and the timing (timing simulation) of your circuit. Timing simulation is run
after implementing your circuit in the FPGA since it needs to know the actual placement and routing to find out
the exact speed and timing of the circuit

4.7 Design Implementation:-

After generating the netlist file (synthesis step), the implementation will convert the logic design into a physical
file that can be downloaded on the target device. This step involves three sub-steps: Translating the netlist,
Mapping and Place & Route. There are several outputs of implementation: Reports, Timing simulation netlists,
Floor plan files, FPGA Editor files.

4.8 Block Diagram

Chapter .4.1.7 Block Diagram of 16 bit AL

20
4.9 Flow chart

21
 Chapter 5: Result

5.1 Out Result

22
 Chapter 6: Application and Advantages

 Reduces dynamic power dissipation of ALU by approx. 66.7%.

 Reduce carry propagation delay.

 Increased performance for high no. of bits.

 Used in portable devices such as cell phone, laptop, computers.

 Used as a multiplier and accumulator (MAC) in DSP

23
 Chapter 7:Conclusion and Future Scope

6.1 Conclusion

Thus, we have designed and simulated a 16-bit using Verilog HDL and verified its working by
simulation. The processor can be extended to a 32 or even a 64-bit processor in the future by simple
changes in the code and the data path can be altered to include various new blocks which is not possible
on a traditional processor unit.

6.2 Future scope

In this paper, clock gating technique is applied to a 16-bit

ALU and implemented on a Spartan6 FPGA to reduce the
clock and dynamic power. The ALU block is divided into two
functional blocks. The power for reduction is obtained, as only
one functional block process the input at a time. The clock
power is reduced by nearly100%, 77.78%, 44.59% and an
average of around 36% for frequency of 1MHz, 10MHz and
100MHz and upto 1000MHz respectively. For higher
frequencies the power reduction varies irrelevantly as FPGA
operates in the frequency of KHz to few MHz. The logic and
signal power is reduced for lower frequencies but increases
for the frequencies due to additional hardware and signals in
the design. The dynamic power is reduced for lower
frequencies while for higher frequencies it increases
tremendously as the junction temperature increases beyond the
operating limit of the FPGA. The area utilized for clock gating
is more but can be compensated for the gain in the power
reduction. The power reduction motivates using this technique
in high speed devices and those applications such as network
processors or system-on-chip where there are large no of
processing elements or more than one processors or functional
units.
The future scope could be to implement this on a high
scalable technology for other FPGA of Virtex series and also
for ASIC devices
In this paper, clock gating technique is applied to a 16-bit
ALU and implemented on a Spartan6 FPGA to reduce the
clock and dynamic power. The ALU block is divided into two
functional blocks. The power for reduction is obtained, as only
one functional block process the input at a time. The clock
power is reduced by nearly100%, 77.78%, 44.59% and an
average of around 36% for frequency of 1MHz, 10MHz and
100MHz and upto 1000MHz respectively. For higher
frequencies the power reduction varies irrelevantly as FPGA
operates in the frequency of KHz to few MHz. The logic and
24
signal power is reduced for lower frequencies but increases
for the frequencies due to additional hardware and signals in
the design. The dynamic power is reduced for lower
frequencies while for higher frequencies it increases
tremendously as the junction temperature increases beyond the
operating limit of the FPGA. The area utilized for clock gating
is more but can be compensated for the gain in the power
reduction. The power reduction motivates using this technique
in high speed devices and those applications such as network
processors or system-on-chip where there are large no of
processing elements or more than one processors or functional
units.
The future scope could be to implement this on a high
scalable technology for other FPGA of Virtex series and also
for ASIC devices
In this paper, clock gating technique is applied to a 16-bit
ALU and implemented on a Spartan6 FPGA to reduce the
clock and dynamic power. The ALU block is divided into two
functional blocks. The power for reduction is obtained, as only
one functional block process the input at a time. The clock
power is reduced by nearly100%, 77.78%, 44.59% and an
average of around 36% for frequency of 1MHz, 10MHz and
100MHz and upto 1000MHz respectively. For higher
frequencies the power reduction varies irrelevantly as FPGA
operates in the frequency of KHz to few MHz. The logic and
signal power is reduced for lower frequencies but increases
for the frequencies due to additional hardware and signals in
the design. The dynamic power is reduced for lower
frequencies while for higher frequencies it increases
tremendously as the junction temperature increases beyond the
operating limit of the FPGA. The area utilized for clock gating
is more but can be compensated for the gain in the power
reduction. The power reduction motivates using this technique
in high speed devices and those applications such as network
processors or system-on-chip where there are large no of
processing elements or more than one processors or functional
units.
The future scope could be to implement this on a high
scalable technology for other FPGA of Virtex series and also
for ASIC devices.
Today's high speed devices namely Network-on-Chip,
System-on-Chip or the devices of communication need to
operates at very low voltages, consume less power but with
increased performance. From the survey it is learnt that the
processing elements of Network processors for example
consume power the most. Hence, the reduction of power in
these PE is of concern, leading to energy efficient NP. As one
of the solution to this problem, in [1] a low power technique
reducing the switching activities for the varying traffic volume

25
is proposed. Low power design techniques have been adopted
This 16-bit reversible Alu is designed and implemented in Verilog using MODEL SIM ALTERA 6.6d.
The main aim of the design in this paper is improve the ALU features by increasing it to 15-operations
and increase width to 16-bit. For further research this ALU can be extended to 32-bit and 64-bit and
more features can also be added.

This design is verified using Verilog which has constrains of input to output one-way functionality, if
we can design the reversible logic circuit using tools which support 2-way functionality the reversible
logic result can be simulated and analysed in much better.

REFERENCE

[1] Jikku Jeemon, “Low power pipelined 8-bit RISC processor design and implementation on FPGA”,
ICCICCT 2015.

[2] Supraj Gaonkar and Anitha M, “Design of 16-bit RISC Processor”, IJERT Vol. 2 Issue 7, July
2013.

[3] D. J. Smith, “HDL Chip Design”, International Edition, Doone Publications, 2000.
26
[4] J.F. Wakerly, “Digital Design: Principles and Practices”, Third Edition, Prentice-Hall, 2000.

[5] A. S. Tanenbaum, “Structured Computer Organization”, Fourth Edition, Prentice-Hall, 2000.

[6] Yatin Trivedi and others, “Verilog HDL”, IC, 2000.

[7] Mauriss M Mano, “Digital Design”, Third Edition, Perason Edition, 2000.

[8] Shraddha M. Bhagat and Sheetal U. Bhandari, “Design and Analysis of 16-bit RISC Processor”,
Fourth International Conference on Computing Communication Control and Automation (ICCUBEA),
2018

27
28