Digital Circuits and Systems Lab

Laboratory report submitted for the partial fulfillment

of the requirements for the degree of

Bachelor of Technology
in
Electronics and Communication Engineering

by

Anuj Gupta - 20UEC153

Course Coordinator
Dr. Mohit Joshi

Department of Electronics and Communication Engineering

The LNM Institute of Information Technology, Jaipur

september 2021
Copyright © The LNMIIT 2021
All Rights Reserved
 Contents

Chapter Page

1 Experiment - 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Aim: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.1 2x1 MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.2 4x1 MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.3 8x1 MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Coding Techniques used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4.1 2x1 multiplexer using dataflow modeling. . . . . . . . . . . . . . . . . . . . . 2
1.4.2 2x1 multiplexer using behavioral modeling. . . . . . . . . . . . . . . . . . . . 5
1.4.3 4x1 multiplexer using data flow modeling. . . . . . . . . . . . . . . . . . . . . 8
1.4.4 4x1 multiplexer using structural modeling(using only 2x1 MUX). . . . . . . . 11
1.4.5 8x1 MUX using structural modeling and using 4x1 and 2x1 MUX. . . . . . . . 14
1.4.6 Comparison the power and cell usage in all 4 different implementation. . . . . 17

iii
 Chapter 1

Experiment - 3

[9:28 PM, 9/15/2021] Anuj Gupta : koi na bhej [9:31 PM, 9/15/2021] Ayush Jain Lnmiit:

1.1 Aim:

Implementation of 2x1, 4x1 and 8x1 multiplexers using dataflow, behavioral and structural modeling
in VHDL.

1.2 Theory

Multiplexers also denoted as MUX are the combinational circuits that take many inputs and produces
single output. The number of input lines depends on the select lines. If a MUX has n select lines than
number of input lines will be 2n .Hence there are 2n input combinations possible.

1.2.1 2x1 MUX

There is only one select line(S) and no. of input lines thus is 21 = 2(I0,I1). Below is the truth table
for 2x1 MUX . Thus logical expression for output is , Y = S’.I0 + S.I1

S Output(Y)
0 I0
1 I1

1.2.2 4x1 MUX

There are 2 select line(S0,S1) and no. of input lines thus is 22 = 4(I0,I1,I2,I3). Below is the truth table
for 4x1 MUX . Thus logical expression for output is , Y = (S0’.S1’.I0)+(S0.S1’.I1)+(S0’.S1.I2)+(S0.S1.I3)

1
 S1 S0 Output(Y)
0 0 I0
0 1 I1
1 0 I2
1 1 I3

1.2.3 8x1 MUX

There are 3 select line(S0,S1,S2) and no. of input lines thus is 23 = 8(I0 to I7). Below is the truth table
for 8x1 MUX .Thus logical expression for output is , Y = (S0’.S1’.S2’.I0)+(S0.S1’.S2’.I1)+(S0’.S1.S2’.I2)+
(S0.S1.S2’.I3)+ (S0’.S1’.S2.I4)+(S0.S1’.S2.I5)+ (S0’.S1.S2.I6)+(S0.S1.S2.I7) .

S2 S1 S0 Output(Y)
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

1.3 Coding Techniques used

Structural Modeling: We implement circuits using the user defined circuits as components in our
main circuit. In coding, component instantiation statement is a concurrent statement. Int his model
architecture consists of two parts one is declarative part which comes before ’begin’ keyword and the
statement part which comes after ’begin’ keyword.
Data flow Modeling: Data flow style describes a system in terms of how the data flows through the
system.A data flow description directly implies a gate-level implementation.
Behavioral Modeling : A behavioural description describes a system’s behaviour or function in
an algorithmic fashion. Behavioral style consists of one or more process statements. Each process
statement is a single concurrent statement that itself contains one or more sequential statements.

1.4 Simulation and Results

1.4.1 2x1 multiplexer using dataflow modeling.

2
 Figure 1.1 Schematic of 2x1 multiplexer using dataflow modeling.

Figure 1.2 Project Summary of 2x1 multiplexer using dataflow modeling.

3
Figure 1.3 VHDL Code of 2x1 multiplexer using dataflow modeling.

Figure 1.4 Simulation of 2x1 multiplexer using dataflow modeling.

4
1.4.2 2x1 multiplexer using behavioral modeling.

Figure 1.5 Schematic of 2x1 multiplexer using behavioral modeling.

5
Figure 1.6 Project Summary of 2x1 multiplexer using behavioral modeling.

Figure 1.7 VHDL Code of 2x1 multiplexer using behavioral modeling.

6
Figure 1.8 Simulation of 2x1 multiplexer using behavioral modeling.

7
1.4.3 4x1 multiplexer using data flow modeling.

Figure 1.9 Schematic of 4x1 multiplexer using data flow modeling.

8
Figure 1.10 Project Summary of 4x1 multiplexer using data flow modeling.

Figure 1.11 VHDL Code of 4x1 multiplexer using data flow modeling.

9
Figure 1.12 Simulation of 4x1 multiplexer using data flow modeling.

10
1.4.4 4x1 multiplexer using structural modeling(using only 2x1 MUX).

Figure 1.13 Schematic of 4x1 multiplexer using structural modeling.

11
Figure 1.14 Project Summary of 4x1 multiplexer using structural modeling.

Figure 1.15 VHDL Code of 4x1 multiplexer using structural modeling.

12
Figure 1.16 Simulation of 4x1 multiplexer using structural modeling.

13
1.4.5 8x1 MUX using structural modeling and using 4x1 and 2x1 MUX.

Figure 1.17 Schematic of 8x1 multiplexer using structural modeling.

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Figure 1.18 Project Summary of 8x1 multiplexer using structural modeling.

Figure 1.19 VHDL Code of 8x1 multiplexer using structural modeling.

15
 Figure 1.20 Simulation of 8x1 multiplexer using structural modeling.

Figure 1.21 Synthesis report of 8x1 multiplexer using structural modeling.

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1.4.6 Comparison the power and cell usage in all 4 different implementation.

Name of the Entity No. of LUT used Total On chip Power

2x1(DF) 1 0.409W
2x1(Behav) 1 0.409W
4x1(DF) 1 0.509W
4x1(Struct.) 1 0.509W
8x1(Struct.) 1 0.510W

17