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Test Type Module Test Test Code Verilog SET 4_2019-

20
Verilog module
Subject Duration 2hrs Total Marks 100 Marks

INSTRUCTIONS: (Please read before answering)

1. Do not write on the question paper. Write / Answer only in the answer sheet provided
2. No additional time will be provided to complete the test
3. Your answer sheet will not be evaluated if the instructions are not followed.
I. Answer in one word (10 x 1 = 10)

1. The FPGA refers to ____________

a) First programmable Gate Array b) Field Programmable Gate Array

c) First Program Gate Array d) Field Program Gate Array

2. In a multiplexer the output depends on its ________________

a) Data inputs b) Select inputs c) Select outputs b) Enable Pin

3.Most demultiplexers facilitate which type of conversion?_________________

a) Decimal-to-hexadecimal b) Single input, multiple outputs

c) AC to DC d) Odd parity to even parity

4.The sequential circuit is also called ___________

a) Flip-flop b) Latch c) Strobe d) Adder

5. How many possible outputs would a decoder have with a 6-bit binary input?_________

a) 32 b) 64 c) 128 d) 16

6.Total number of inputs in a half adder is __________

a) 2 b) 3 c) 4 d) 1

7. A decimal counter has ______ states.

a) 5 b) 10 c) 15 d) 20

8. Any signed negative binary number is recognized by its ________

a) MSB b) LSBc) Byte d) Nibble

9. Represent signed number -3 in bit/hex format. Consider bitwidth as 32

_______________________

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10. In a combinational circuit, the output at any time depends only on the _______ at that time.

a) Voltage b) Intermediate values c) Input values d) Clock pulses

II. Answer the following (5 x 8 = 40)

11. Determine the type of machine and design the circuit for the following state machine.

12. Write any VHDL/Verilog HDL code for an Asynchronous Reset D Flip Flop.

13. Design and write a verilog for dual port RAM.

14. Draw the combinational logic circuit with three inputs x,y, z and three output a, b and c.
when binary input is 0, 1, 2 or 3 the binary output is one greater than the input. When the binary
input is 4, 5, 6 or 7 the binary output is one less than the input.

15. Design 5 to 32 decoder. Use 2 to 4 and 3 to 8 decoder if required.

16. What is the difference between a Flop and a latch.

17. From the below diagram tell the equivalent logic

Circuit Gate Circuit Gate Circuit Gate

Circuit Gate Circuit Gate Circuit Gate

18. Draw IO Pin diagram for a Dual Port RAM and a FIFO.

19. Design the following using decoders

a) Half adder
b) F(w, x, y, z) = ∑(1, 4, 5, 6, 12, 14, 15)

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III. Explain the following ( 10x 5 = 50)

20. Design a sequence detector which detects 101 and 010 using mealy and moore state machine
and write verilog code.

21. Design and write a verilog program for a counter which counts 16 states using synchronous
counter.

22. Design and write a verilog program for 4x4 multiplier.

23. Design ALU with minimum 10 functions using register and write verilog program.

24. Draw the MOOREFSM for following sequence detection “101011” for both overlap and
non-overlap sequence and write the HDL code.

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