ADC术语表 TI

Glossary of Terms
Application Report
Application
SBAA147A – August 2006 Report
– Revised 应用报告
January 2008
ZHCA068-August
SBAA147A 2006-Revised
– August 2006 – Revised January 2008
A Glossary of Analog-to-Digital Specifications and

A Glossary of Analog-to-Digital Performance Specifications
Characteristics and
术语词汇表：模数转换的规格和性能特点 Performance Characteristics
Bonnie Baker ................................................................................................ Data Acquisition Products
Bonnie Baker ................................................................................................ Data Acquisition
数据采集系统Products
ABSTRACT
This glossary is a collection of the definitions 摘要 of Texas Instruments' Delta-Sigma (ǻȈ),
ABSTRACT
successive approximation
This这份术语表汇总定义了 register
glossary is a collection 公司 (SAR), and pipeline
of the definitions of Texas analog-to-digital (A/D) Converter
Instruments' Delta-Sigma (ǻȈ),
specifications TI
and performance Delta-Sigma (ΔΣAlthough
)技术、逐次逼近寄存器 (SAR)和流水
successive approximation register characteristics. there is a
(SAR), and pipeline analog-to-digital considerable
(A/D) Converter
amount
线模数 of detail
(A/D) 转换器
specifications andin this document,
并详细说明了它们的规格和性能特点
，performance the product data
characteristics. sheet for a isparticular
。虽然这是一份相当详尽的文
Although there product
a considerable
specification
amount
档， of is
detail
但如果想得到最全面的参考资料 thein best
this and final
document, ，reference.
the To
product download
data
请参阅这一特定产品的资料手册 sheet or
forview
a a specific
particular
。如要下载并浏览 data
product
converter product data sheet, see the Texas Instruments web site at www.ti.com/.
specification is the best and final reference. To download or view a specific data
某一特定转换器的数据手册，请访问TI公司的网站www.ti.com/.
converter product data sheet, see the Texas Instruments web site at www.ti.com/.
Glossary
术语表 of Terms
Glossary
采集时间of Terms
Acquisition
: Time:
Acquisition
参看图
Refer 1，Time:
to Figure when comparing (SAR)
对比逐次逼近寄存器 SAR, 、流水线和
Pipeline, Delta-Sigma
and (ΔΣ
Delta-Sigma )转换器三者的采集时间
converter acquisition time.。
Refer to Figure when comparing SAR, Pipeline, and Delta-Sigma converter acquisition time.
Signal�Noise
Signal�Noise
Multiple�samples,
averaged
Single Multiple�samples,
sample�per averaged
2 Single 2
conversion
sample�per
1 2 conversion 1 2
1 1
Data Data Data

1 2 3 4 1 2 3 4 1 2 3 4
Out Out Out
Data Data Data
1 2 3 4 1 2 3 4 1 2 3 4
OutSampling�SAR�ADC Out Pipeline�ADC Out Oversampling
Delta-Sigma�ADC
Sampling�SAR�ADC Pipeline�ADC Oversampling
Figure
参看图 1.1，对比逐次逼近寄存器
SAR vs Pipeline vs(SAR) ǻȈ A/D Converters
、流水线和 Sampling Algorithms Comparison
Delta-Sigma (ΔΣDelta-Sigma�ADC
)转换器三者的采集时间。
Figure 1. SAR vs Pipeline vs ǻȈ A/D Converters Sampling Algorithms Comparison
•• Acquisition time, Delta-Sigma
采集时间，Delta-Sigma 模数转换器 A/D Converters–
• The
Acquisition time, Delta-Sigma
Delta-Sigma (ǻȈ) converter averages A/D Converters–
multiple samples for each conversion result. The averaging
Delta-Sigma
performed by (the
ΔΣ)数模转换器对每一转换结果进行多次平均取样。转换器的采样过程通常采用有限冲击
converter usually occurs in the form of a Finite Impulse Response (FIR) oraveraging
Infinite
The Delta-Sigma (ǻȈ) converter averages multiple samples for each conversion result. The
响应 (FIR)
Impulse Response
或者无限冲击响应 (IIR) (IIR)
digital filter.
数字滤波的方式 Consequently,
。因此，the acquisition
它的采样时间和 SAR
time is longer than
或者流水线转换器相比要长
performed by the converter usually occurs in the form of a Finite Impulse Response (FIR) or Infinite it is with a SAR，
or pipeline
Impulse converter,
Response
因为后两者每次转换只对信号进行一次采样 which
(IIR) onlyfilter.
digital samples 。the
图1signal
Consequently,
展示了 once
the for each
acquisition
SAR， conversion.
time is
流水线和ΔΣ模数转换器三者的取样方法差 Figure
longer than it illustrates
is with one
a SAR
of
or the differences
pipeline between
converter, which the sampling
only samples mechanism
the signal of a SAR,
once for a Pipeline
each and aFigure
conversion. ǻȈ converter.
If theone
illustrates
异中的一种
user 。如果用户输入一个阶跃输入信号或者在多路复用器中切换一个输出通道，转换器需要花一定时
of thepresents
differencesa step-input
betweento thethe delta-sigma
sampling converter
mechanism of input
a SAR, or aswitches
Pipelineaand multiplexer output channel,
a ǻȈ converter. If the

I C is a Itrademark
2
of Koninklijke
C是荷兰皇家菲利浦电子有限公司的商标 Philips Electronics
。 N.V.
user presents a step-input to the delta-sigma converter input or switches a multiplexer output channel,
SPI is a trademark of Motorola, Inc.
IC is aSPI 是摩托罗拉公司的商标
trademark 。
of Koninklijke Philips Electronics N.V.
All other其它商标版权归各自的公司所有
trademarks are the property of。 their respective owners.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
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Glossary of Terms
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Glossary of Terms
间，因为数字滤波器要刷新信号 www.ti.com
。如果要对信号进行“快照”或需要查看某一特定时间电的信号，则最好使
Glossary
用SARof模数转换器
Terms
the 。 will require time for the digital filter to refresh with the new signal. If a snap-shot of the
converter
signal or a defined acquisition point in time is required, it is more appropriate to use a SAR A/D
the converter will require time for the digital filter to refresh with the new signal. If a snap-shot of the
converter.
• 采集时间，流水线模数转换器
signal or a defined acquisition point in time is required, it is more appropriate to use a SAR A/D
• Acquisition
converter. time, Pipeline
在使用流水线模数转换器时 A/D Converters–
，先用外输入时钟的上升沿（有的是下降沿，在产品资料表单中会有说明）
• With a pipeline
Acquisition A/DPipeline
time, converter,
A/DtheConverters–
user initiates the conversion process with the rising edge (or falling
进行初始化。紧随着输入信号首端的跳变，转换器开始对信号进行差分运算。参看图1和图2.
edge, as specified in the product data sheet) of the external input clock. The capture of the differential
With a pipeline A/D converter, the user initiates the conversion process with the rising edge (or falling
input signal follows the opening of the input internal switches. See Figure and Figure .
edge, as specified in the product data sheet) of the external input clock. The capture of the differential
input signal follows the opening of the input internal switches.
Sample�ErrorSee Figure and Figure .
(offset,�nonlinearity)
Input�signal
Sample�Error
(offset,�nonlinearity)
Input�signal
Aperture�time
Acquisition�time
Aperture�time
or�sample�time
Acquisition�time
Hold Sample
or�sample�time Hold
Hold Sample Hold

Figure 2. Acquisition Time (Sample Time) and Aperture Time
图2.采集时间（采样时间）和孔径时间
•
Acquisition time,Figure
SAR2. Acquisition Time (Sample Time) and Aperture Time
A/D Converters–
• The acquisition
Acquisition time
time, for the
SAR A/DSAR converter is the time required for the sampling mechanism to capture
Converters–
the inputSAR
• 采集时间， voltage.
模数转换器 This time begins after the sample command is given where the hold capacitor
The acquisition time for the SAR converter is the time required for the sampling mechanism to capture
SARcharges. Some converters have the capability of sampling
转换器的采集时间是由采样运算捕获输入电压来决定的
the input voltage. This time begins after the sample command
the input signal in response，to同时保持电
。当采样命令发出后开始计时 a sampling
is given where the hold capacitor
pin on the converter. Other SAR CMOS converters sample with the clock after CS (chip select) drops
charges.
容也开始充电 Some converters have the capability of sampling the input。
有的转换器会对采样管脚端做出响应并对输入信号进行采样 signal
而其它的 in response
SAR CMOS to a转换器的
sampling
(with a。serial peripheral interface, or SPI™). Figure shows an example of a clock-initiated sample
pin on the converter. Other SAR CMOS converters sample with the clock after CS (chip select) drops
using the ADS.
采样启动由时钟输入与 CS（ Also see ）
片选信号 Figure
下降沿决定 and Figure .
，CS由串行外部接口产生，即SPI™。图3举了一个时钟
(with a serial peripheral interface, or SPI™). Figure shows an example of a clock-initiated sample
using the ADS.
信号启动采样过程的例子 A ADS7816。
Also see Figure
，使用的芯片是图1和图
and Figure . 2中使用的是同样的芯片
A
Sample
Period Conversion�Period
Sample
CS Period Conversion�Period
Clock�#15�is
B
CS optional;
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Clock�#15�is
D0�is�clocked�out
B
CLK optional;
on�falling�edge�of
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0�is�clocked�out
Clock�#14
CLK on�falling�edge�of
Clock�#14
DOUT D D D D D D D D D D D D
11 10 9 8 7 6 5 4 3 2 1 0
DOUT D D D D D D D D D D D D
11 10 9 All�data�transitions�occur
8 7 6 5 4 3 2 1 0
Null�Bit on�the�falling�edge�of�SLK
All�data�transitions�occur
Null�Bit on�the�falling�edge�of�SLK
A Chip select (CS) falls.
B
A The
Chipfalling
selectedge
(CS) of the clock图
falls. closes the sample switch.
3. 一个由时钟启动采样过程的SAR模数转换器
B Figure
The falling edge of the 3. Clock-Initiated
clock closes the sample switch.Sample for a SAR A/D Converter
A 片选信号下降沿. Figure 3. Clock-Initiated Sample for a SAR A/D Converter
Analog Input, Analog Bandwidth: The input frequency where the reconstructed output of the A/D
B 时钟信号的下降沿结束了采样阶段.
converter is dB below the value of the input signal.
Analog Input, Analog Bandwidth: The input frequency where the reconstructed output of the A/D
converterInput,
Analog is dB below the value
Capacitance, of the input signal.
Common-mode: The common-mode capacitance of an A/D converter is the
capacitance between each analog signal input(s) and ground.
模拟输入，模拟带宽：模数转换器的输出比输入信号的频率低了 3dB。
Analog Input, Capacitance, Common-mode: The common-mode capacitance of an A/D converter is the
capacitance
Analog
模拟输入，电容值，共模：共模模式下between
Input, each analog
Capacitance, signal
Differential:
， input(s) and ground.
The capacitance between the positive input (AIN+) 。
模数转换器的电容值为每个信号输入管脚与地之间的容值 and negative
input (AIN–) of an A/D converter with a differential input.
Analog Input, Capacitance, Differential: The capacitance between
模拟输入，电容值，差分输入：一个带有差分输入的模数转换器中，正级输入 the (A
positive input (AIN+IN–
IN+)和负极输入(A
) and
)之间negative
input (AIN–) of an A/D converter with a differential input.
的电容值
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A Glossary of Analog-to-Digital Specifications and Performance Characteristics SBAAA – August 00 – Revised January 00
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Glossary of Terms
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Analog Input, Differential Input: With the analog differential input, both input pins of theGlossary of Terms
A/D converter
can swing the full range, and typically change in a balanced fashion—that is, as one input goes up, the
模拟输入，差分输入：当输入模拟的差分信号时，模数转换器的两输入端的数值可以全范围浮动，通常在一
other goes down in a corresponding way. The differential input offers the advantage of subtracting the two
inputs and provides common-mode
个相互平衡的状态上改变，当一个输入端电压升高rejection. These types of inputs are commonly
，另一输入端就相应的降低 found in single-supply
。差分输入有个好处就是利用
converters, such as delta-sigma
了两输入端信号的差值，提供了共模抑制 or pipeline
。 converters. The differential
这类型的输入模式在单电源的转换器中很常见 input offers the advantages of
，如delta-sigma 或
common-mode rejection, with a smaller input voltage swing required on each pin while preserving a high
流水线转换器差分输入有个好处就是提供了共模抑制
dynamic range. ，只需要每一管脚很小的输入电压变化，同时保留了很
高的动态范围。
Analog Input, Impedance, Common-mode: The impedance between each analog signal input of the
A/D converter and ground.
模拟输入，阻抗，共模：模数转换器的各个模拟信号输入管脚与地之间的阻抗。
Analog Input, Impedance, Differential: The impedance between
模拟输入，阻抗，差分模式：一个带有差分输入的模数转换器中 the positive
，正级输入 input
(AIN+ (AIN+) and
)和负极输入 negative
(AIN– )之间的阻
input
抗。 (A IN– ) of an A/D converter with a differential input.
Analog Input, Voltage Range, Absolute: The absolute analog voltage range of an A/D converter is the
模拟输入，电压范围，绝对值：模数转换器的绝对电压范围是输入电压的最大值和最小值（相对于地和模拟
maximum and minimum voltage limit of the input stage (compared to ground and/or the analog supply
voltage). ）。
电源电压 This这个数值描述了输入信号的绝对输入电压范围
term describes the absolute input voltage range，通常 limits of the input stage. Usually, the
，这由正电源和负电源所提供的电压值来
positive and negative power supplies impose
决定，除非输入端还存在一个电阻网络。如果有这么一个电阻网络，那么输入的绝对值就可以超过正电源和 these limits on the device, unless there is a resistance
network on the input. If there is a resistive input network, the absolute inputs can exceed the positive and
负电源提供的电压值
negative power supplies.。
模拟输入，电压范围，双极输入模式（差分模式）：一个配置了双极输入模式的模数转换器
Analog Input, Voltage Range, Bipolar Input Mode (Differential Inputs): An A/D converter ，它的输入范围
configured in
a Bipolar Input Mode，has
由两个输入引脚确定 an input range that uses two input pins
同时可以任意输入正的和负的模拟信号。 and
在这种配置下 allows negative
， and positive
任意一个输入管脚都不会低 analog
inputs on both pins with
于或超出绝对输入电压范围。（参考-输入电压范围差分输入。） respect to each other. In this configuration, neither input pin goes below or above
the absolute input voltage range. (See –Input Voltage Range Differential Inputs. )
模拟输入，电压范围，满量程(FS or FSR)：转换器把输入的信号数字化为满量程的输入电压。其内部和外
Analog Input, Voltage Range, Full-Scale (FS or FSR): The converter digitizes the input signal up to the
full-scale input voltage. The internal or external applied。
部所使用的参考电压决定了这个满量程电压的数值范围 voltage reference value determines the full-scale
确切的满量程输入电压范围会因器件不同而有所差
异input voltage range. The actual FS input voltage range
，更多的细节可以参考特定的模数转换器的资料单。 will vary from device to device. Refer to the
specific A/D converter data sheet for details.
•• For 对于一个 n字节的转换器
an n-bit converter, ，FS FS is等于 : to:
equal
n
FS = FS
( )=×(2(ideal
n ) × (code width)
理论码宽 )
• For 对于delta-sigma
delta-sigma的转换器 converters,，FSR FSR is often used to express units in
通常用百分比的形式来描述数值的大小 terms
。例如 of percentages.
，可以把 INL的大小描述 For
instance, you may find INL defined at
为FSR的±0.001%。这个例子中，A/D转换器的输入范围可以是±2.5V，它的FSR为5V。±0.00% of FSR. In this instance, the input range of the A/D
converter could be ±.V, with a FSR = V.
同样可以参考：模拟输入，差分输入。要了解具体型号A / D转换器的更多细节请参考资料单。
Also see: Analog Inputs, Differential Inputs. Refer to a specific A/D converter data sheet for details.
模拟输入，电压范围，拟微分模式：一个拟微分输入有两个输入管脚，AIN+和AIN–，如图4所示。当其中一
Analog Input, Voltage Range, Pseudo-differential: A pseudo-differential input has two input pins, AIN+
and AIN–, as Figure，另一个输入管脚则为输入信号提供参考电压
个为拟微分输入时 illustrates. With a pseudo-differential input,。the second input
第二个管脚 pin provides the）只能接
（负电压信号输入端
reference for the signal. This second input
受一个很小范围内的电压，大约只有几百毫伏(mv)，当输入信号有一个很小的共模偏置或有小信号误差的时 pin (the negative input) can only accept a small range of
voltages, perhaps a few hundred millivolts (mV). This configuration can be very helpful in situations where
候这种拟微分模式的设置就非常有用了
the，signal has a slight common-mode offset 。它能除去这类的偏置和误差，因为转换器只对正端管脚输入和负
or small-signal error. The pseudo-differential input reduces
this offset or small-signal error because
端管脚输入信号之间的差起作用。 the converter sees only the difference between the positive input
pin and the negative input pin.
AIN+
ADC DAC
AIN�
±200mV�Maximum
Figure 4. Pseudo-Differential
图4. A/D转换器的拟微分模式Mode for A/D Converters
Analog Input, Voltage Range, Single-ended (unipolar and bipolar): A single-ended input A/D converter
模拟输入，电压范围，单端信号（单级和双极）：一个单端信号输入的模数转换器只有一个输入端，并且输
is configured for one input voltage that is referenced to ground. Some single-supply devices have a
single-ended input range 。
入电压是以地为参考信号 that allows only positive analog input signals. Other single-supply
有的单电源供电的器件对单端信号的输入范围有限制 (and
，只允许正电压的模拟输
dual-supply) parts handle a signal that moves
入。而有的单电源供电（或双电源供电）的器件可允许正电压信号或负电压信号输入，并且有两个输入端 both above ground and below ground, and have a bipolar 。
input. Also see Analog Input, Voltage Range, Pseudo-differential.
参看模拟输入，电压范围，拟微分模式。
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Glossary
Glossary ofofTerms
Terms
Glossary of
Glossary of Terms
Terms
Analog
Analog Input,
Input, Voltage
Voltage Range,
Range, Differential
模拟输入，电压范围，差分输入：差分输入电压的范围等于同相端模拟输入 Differential Inputs:
Inputs: The
The differential
differential input
input voltage range
range is
is equal
(AIN+)与反相端模拟输入
voltage equal to
to the
(AIN–)之
the
noninverting
noninverting analog
analog
差。有了这两个输入管脚，输入电压的范围为 input
input (A
(AIN+
IN+
IN+
)
) minus
minus the
the inverting
inverting
： analog
analog input
input (A
(AIN–
IN–
IN–
).
). With
With these
these two
two input
input pins,
pins, the
the
IN+ IN–
input
input voltage
voltage range
range is:
is:
Full-Scale�= (((A
Full-Scale�= (AIN+(MAX)
IN+(MAX) �A
IN+(MAX) �
IN+(MAX) AIN
IN
IN (MIN))) �
(MIN)
�(MIN)
IN��
�(MIN) � (A
(AIN+(MIN)
IN+(MIN) �A
IN+(MIN) �
IN+(MIN) AIN
IN
IN �(MAX)))))
(MAX)
�(MAX)
IN��(MAX)
A
A positive digital
digital output
当模拟输入差分信号
positive output is(Aproduced
is when
when the
IN+ – AIN–)是正电压时
produced the analog input
input differential
，输出的数字信号也是正的
analog differential voltage (A IN+ –
。负电压差分模拟输入
voltage (AIN+
IN+
IN+ –A IN–)) is
AIN–
IN–
IN– is positive.
，输出负
positive. A
A
negative analog
negative analog 。 input
input differential
differential voltage
voltage produces
produces negative digital output. Most
negative digital output. Most SAR SAR and delta-sigma
and delta-sigma A/D A/D
电压的数字信号
converters
大多数的 SAR 和 delta-sigma 模数转换器都工作在相似的模式下，并且不需要共模电压。
converters operate
operate in in aa similar
similar fashion
fashion toto analog
analog instrumentation
instrumentation amplifiers
amplifiers and
and dodo not
not require
require a a
而大多数CMOSvoltage.
common-mode 流水线的模数转换器则需要在输入端有一个共模电压偏置 (VCM)，典型值为电源电压的一半
common-mode voltage. Most Most CMOS
CMOS pipeline
pipeline A/D
A/D converters
converters require
require aa common-mode
common-mode voltage
voltage biasbias (V
(VCM )
CM)
CM
CM
to the
to the
(+V inputs,
inputs,
S/2)。
which is typically set to mid-supply (+V
which is typically set to mid-supply (+VSSS/).，
一个外部电源可以有两种方式驱动转换器的输入 S/). An
An external source
external source can
可以是单端电压驱动 can drive
，drive the differential
the differential
也可以是差分方式输入。
converter
converter inputs
inputs in
in one
one of
of two
two ways:
ways: either
either single-ended
single-ended or
or differential.
differential. See
See Figure
Figure .
.
看图 5。
Single-Ended
Single-Ended Input
Input Differential
Differential Input
Input
+�f
+�f
+�f +�f
+�f
+�fsss/2/2
/2
+�fssss +�f s/2
Input
Input
Input V
V
VCM CM
V Input V CM
CM IN
IN
V
VCM
CM IN
IN
IN f /2 IN
IN
V CMCM IN � fffsss/2
��
�
s
/2
/2
f ADC
ADC
ADC ADC
ADC
ADC
� fffssss
�� ADC +�f
+�f /2 ADC
+�fssss/2
+�f /2
�
IN /2
IN
IN
IN V
V
V CM IN
IN
IN
VCM CM
CM IN
�� ff /2
/2
� ffsss/2
/2
� s
V
V
VCM
CM
V CM
CM
Figure
Figure 5.
5. Single-Ended
Single-Ended and
and Differential
Differential Inputs
图5. 模数转换器的单端电压驱动和差分方式输入 Inputs to
to an
an A/D
r Converter
A/D Converter
模数转换器(ADC, A-D转换器, A/D转换器):一个A/D转换器能够把连续的信号转换成时间和幅值都是离散的数
Analog-to-Digital
Analog-to-Digital Converter
Converter (ADC,
(ADC, A-D A-D Converter,
Converter, A/D A/D Converter):
Converter): An An A/D
A/D converter
converter is is a
a device
device that
that
字信号。 a continuous signal into a discrete-time, discrete-amplitude digitized signal.
changes
changes a continuous signal into a discrete-time, discrete-amplitude digitized signal.
Aperture:
孔径 :
Aperture:
•• Delay–
延迟–
Delay–
The
The delay
delay in
in time
time between
between the
时间的延迟是从外输入取样命令的上升沿或下降沿 the rising
rising or
or falling
falling edge
edge (typically
（一般是the
(typically 50%
the 0%
0%
的位置 point)
point)
）开始 of
of ，the external
external sample
the到实际对信号进行 sample
command
command
采样的这一段时间 and the
and the 。 actual
actual
看图2.time at which the signal is captured. See
time at which the signal is captured. See Figure . Figure .
•• Jitter–
Jitter–
• Aperture
抖动–
Aperture jitter
jitter is
is the
the standard
standard deviation
deviation ofof aperture
aperture delay
delay from
from sample
sample to
to sample
sample over
over time.
time. Aperture
Aperture
jitter
jitter is sometimes
sometimes mistaken
mistaken as
孔径抖动是孔径延迟在采样中随时间而产生的标准偏差
is as input
input noise.
noise. The
The aperture
aperture jitter, along
along with
with clock
。有时候孔径抖动被误认为是输入噪声
jitter, clock jitter
jitter of
of the
the sampling
。孔
sampling
system,
system, impacts
impacts the
径抖动加上时钟脉冲抖动 the overall
overall signal-to-noise
signal-to-noise ratio
，会对整个转换过程的信噪比 ratio (SNR)
(SNR) of
of
(SNR) the
the
产生影响conversion.
conversion.
。 The
The contribution
contribution
抖动对信噪比的影响公式为 of
of jitter
jitter
： to
to
the SNR is equal
the SNR is equal to: to:
11
SNR�=�20log10(��)
SNR�=�20log10(��)
(2
(2��f�t
f�tjjj)))
(2 � f�t j
其中:
Where:
Where:
• •• tjttj是时钟和孔径的抖动 ; jitter;
• tjjj isis the
is the clock
the clock and
clock and aperture
and aperture
aperture jitter;
jitter;
• ••• f是转换器的频率
fff is the
is the
is clock
the clock frequency
frequency of
clock frequency of the
of the converter
the converter
converter
The
孔径和时钟抖动等于 :
The aperture and clock jitter is equal to:
aperture and clock jitter is equal to:
tttjjj = 22
22 22
2
2
=
= (t
(taaaa +�t
+�tcccc ))
j
Where:
Where:
其中 :
• taa is is the
the root-mean-square
root-mean-square of
of the
the aperture
aperture jitter;
• •• tatta是孔径抖动的方均根值 jitter;
a is the root-mean-square; of the aperture jitter;
•• ttcccc is the root-mean-square of the clock jitter
is the root-mean-square of the clock jitter
• tc是时钟抖动的方均根值
There
There is
is no
no correlation
correlation between
between the
the clock-jitter
clock-jitter and aperture-jitter
aperture-jitter terms;
and因此这两项可以合并写为一项 terms; therefore,
therefore, these
these terms
terms can
can be
be
由于时钟抖动与孔径抖动没有联系而相互独立
combined on a root-sum-square basis (rss). ，，写成平方和的开方
combined on a root-sum-square basis (rss).
•• Uncertainty–Also
Uncertainty–Also known
(rss)。 as aperture
known as aperture jitter.
jitter.
Asynchronous
• 不确定性–Sampling:
Asynchronous 也叫做孔径抖动
Sampling: Sampling
.
Sampling of
of the
the A/D
A/D converter
converter that
that is
is not
not locked
locked to
to the
the frequencies
frequencies or
or the
the time
time
of
of other frequencies
other异步采样
frequencies or
or samples
samples in
in the
the application
application circuit.
circuit.
: A/D 转换器采样过程没有被锁定在某一频率或时间上，或者是应用电路的采样
Average
Average Noise
Noise Floor:
噪声平均值 In
In aa Fast
Fast Fourier
: 在数据转换的快速傅立叶变换中
Floor: Fourier Transform
Transform (FFT)
(FFT)
，由所有的 representation
FFT二进制数据点
representation of
of converter
converter data,
data, the
，包括输入信号和信号的the average
average
noise
noise floor
floor is
is a
a calculated
calculated average
average of
of all
all of
of the
the bins
bins within
within the
the FFT
FFT plot,
plot, excluding
excluding the
the input
input signal
signal and
and
谐波，最后求平均而计算出噪声平均值。
signal harmonics.
signal harmonics.
A术语词汇表of ：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January
January 2008

A Glossary
Glossary of Analog-to-Digital
Analog-to-Digital Specifications
Specifications and
and Performance
Performance Characteristics
Characteristics SBAAA
SBAAA––August
August 00
00––Revised
Revised January 00
00
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www.ti.com
www.ti.com
www.ti.com Glossary of Terms
Glossary
Glossaryof ofTerms
Terms
Binary Twos Complement Code (BTC): With the BTC code, the digital zero (0000, for a -bit system)
Binary
二进制补码 Twos
corresponds toComplement
(BTC):Bipolar
在二进制补码中 Zero Code
(BPZ),，(BTC):
and
数字零 theWith thecount
digital
(0000, BTC code,
对于一个 the digital
increments
4比特的系统 to its)zero (0000,positive
maximum
和双极归零码 forBPZ
a -bit
相联系 system)
code of当模拟
。 0
corresponds to Bipolar Zero
as the analog voltage approaches and (BPZ), and the
reachesdigital
its count increments
positive full-scale to its
value. maximum
The code positive
then code
continues of at
0
the
电压达到满量程的正数最大值时候
as the analog voltage approaches 数值增大到它的最大正数有效值
， reaches its positive full-scale value. 0111，然后达到它的负数最大有效值
negative full-scale value at a digitaland
code of 000, then approaches BPZ until The code then
a digital valuecontinues
of (for at the
a
negative
1000， full-scale
并朝
-bit system) BPZ 逼近value
，直到数值
is reached at one
at a digital
LSB code
1111（value ofbelow
对于一个 000,4BPZ then(see
比特的系统 approaches
），).
Table 这比BPZ BPZ
With until aBTC
digital
小了一个最低有效位
the valuescheme,
coding of
LSB（ (for
the 见表a
-bit system)
most significant
1）。按这张BTCbit is reached
(MSB)
字码表 at
，canone LSB value
also be （MSB）
最高有效位 below
considered BPZ (see Table
a sign indicator. 。
可以看成是符号位 ).
WhenWith
当MSB the
the是逻辑 BTC coding scheme,
MSB is'0'a则表示数值是正的 the
logic '0' a positive；
most
value significant
is indicated;bitwhen
(MSB)the can alsoisbe
MSB a considered
logic '' a a sign indicator.
negative value is When theThe
indicated. MSB is a logic
analog '0' a full-scale
positive positive
当 MSB
value 是逻辑
isone '1'则表示数值是负的
indicated; when the MSB is。a模拟信号的正最大值减去 LSBindicated.
就等于(0111)，模拟信号的负最大值就是
minus LSB digital representation islogic
equal'' to
a negative
(0), andvalue
theisanalog The analog
negative full-scalepositive full-scale
representation
minus
(1000). one LSBTable
更多内容请参考表
is (000). See digital representation
for1 more details. is equal to (0), and the analog negative full-scale representation
is (000). See Table for more details.
Table 1. 表BTC1. BTC 字码表(1)(2)
Coding Scheme (1) (2)
Table 1. BTC Coding Scheme (1) (2)
MNEMONIC DIGITAL CODE VTR– VCODE VTR+
–FS 000 — –.000 –.
–FS 000 — –.000 –.
00 –. –. –.0
00
00 –.0
–. –.0
–. –.
–.0
0
00 –.
–.0 –.
–.0 –.
0 –. –. –.
/ –FS 00 –. –.00 –.
/ –FS 00 –. –.00 –.
0 –. –. –.
0
0 –. –.0
–. –0.
–.
0 –. –.0 –0.
BPZ – VLSB –0. –0. –0.
BPZ – VLSB –0. –0. –0.
BPZ 0000 –0. 0.000 +0.
BPZ 0000 –0. 0.000 +0.
BPZ + VLSB 000 +0. +0. +0.
BPZ + VLSB 000 +0. +0. +0.
000 +0. +.0 +.
00
000 +.
+0. +.
+.0 +.
00 +. +. +.
/ +FS 000 +. +.00 +.
/ +FS 000 +. +.00 +.
00 +. +. +.
00
00 +. +.0
+. +.0
+.
00 +. +.0 +.0
+FS 0 +.0 +. —
+FS 0 +.0 +. —
(1)
() 也称为二元补码。此处为4比特系统, FSR = ±5V.
(2) Also 下转换电压码元
known as Two's Complement. For this -bit system, FSR = ±V.
() VTR–
Also= ; Complement.
VTR+ = 上转换电压码元 ; VCODEsystem,
= (码元FSR
)10×V=LSB, VTR+ = VCODE +(1/2)VLSB; VTR– = VCODE – (1/2)VLSB.
±V.
VTR– known
= loweras Two's
code transition voltage;For this=-bit
VTR+ upper code transition voltage; VCODE = (digital code)0 × VLSB, VTR+ = VCODE +
()
V TR– =LSB
(/)V lower code
; VTR– = Vtransition LSB. VTR+ = upper code transition voltage; VCODE = (digital code)0 × VLSB, VTR+ = VCODE +
voltage;
CODE – (/)V
(/)VLSB; VTR– = VCODE – (/)VLSB.
Bipolar Offset Binary Code (BOB): BOB coding begins with digital zero (0000, for a -bit system) at the
Bipolar
negativeOffset
双极偏移二元码 Binary
full-scale. Code (BOB):the
By incrementing
(BOB):BOB 码由数字零 BOB coding
digital
(0000, begins
count,
对于一个 the with digital)开始
corresponding
4比特的系统 zeroanalog
，(0000, for a approaches
value
对应的是负号的最大值 -bit system) at
the
。随着数the
negative full-scale.
positive full-scale By incrementing the digital
in V, least significant bit (LSB) count, the corresponding analog value approaches the
值的增加
positive ，对应的模拟电压朝正最大有效值增大
full-scale in V, ，steps,
每一个最低有效位passing through (LSB)bipolar
增量为1zero 伏，on the way. This 。
中间经过双极零码
zero crossing occurs at aleast significant
digital code of bit (LSB)
000 (seesteps,
Tablepassing
). The through bipolar
digital count zero
continues on the
to way. This
increase
zero crossing occurs
此时对应的数字值是
proportionally at a digital
to the 1000（
analog code
input2）.
见表 of
the000
数值随着模拟输入按比例增大
until (seefull-scale
positive Table ).isThe digital atcount
a fullcontinues
，当模拟输入达到正最大有效值时数字增
reached to increase
digital count (, for a
proportionally
-bit 1111（
大到 system) 对于一个to seen
as the analog
4比特的系统 input
in Table until 见表
. ），
With the
BOB positive
2。按照full-scale
coding, MSBis
the 编码
BOB ， canreached at a（MSB）
be considered
最高有效位 full digital
a sign count (,
indicator,
可以看成是符号位 for a
whereas
。当
-bit system)
a logic '0' as
indicatesseen
a in Table
negative . With
analog BOB
value, coding,
and a the
logic MSB
'' can
indicatesbe considered
an analog a sign
value indicator,
greater thanwhereas
or equal
MSB 是逻辑
a logic '0'则表示模拟电压是负的
'0' indicates a negative analog，value, 当MSB 是逻辑
and '1'则表明模拟电压大于或等于
a logic '' indicates an analog value BPZ greater than or equal
to Bipolar Zero (BPZ).
to Bipolar Zero (BPZ).
(1) (2)
Table 2. 表BOB
2. BOBCoding
字码表Scheme(1)(2)
Table 2. BOB Coding Scheme (1) (2)
–FS 0000 — –.000 –.
–FS 0000 — –.000 –.
000 –. –. –.0
000
000 –.0
–. –.0
–. –.
–.0
00
000 –.
–.0 –.
–.0 –.
00 –. –. –.
/ –FS 000 –. –.00 –.
/ –FS 000 –. –.00 –.
00 –. –. –.
00
00 –. –.0
–. –0.
–.
00 –. –.0 –0.
BPZ – VLSB 0 –0. –0. –0.
BPZ – VLSB 0 –0. –0. –0.
BPZ 000 –0. 0.000 +0.
BPZ 000 –0. 0.000 +0.
BPZ + VLSB 00 +0. +0. +0.
BPZ + VLSB 00 +0. +0. +0.
00 +0. +.0 +.
0
00 +.
+0. +.
+.0 +.
0 +. +. +.
/ +FS 00 +. +.00 +.
/ +FS 00 +. +.00 +.
0 +. +. +.
0
0 +. +.0
+. +.0
+.
0 +. +.0 +.0
+FS +.0 +. —
() +FS +.0 +. —
FSR = ±V.
()
FSR
VTR– = ±V. code transition voltage; VTR+ = upper code transition voltage; VCODE = (digital code)0 × VLSB, VTR+ = VCODE +
(1)
() FSR = ±lower
5V.
(2) V TR– =LSB
(/)V lower code
; VTR– = Vtransition voltage;
CODE – (/)V LSB. VTR+ = upper code transition voltage; VCODE = (digital code)0 × VLSB, VTR+ = VCODE +
VTR– =
(/)V下转换电压码元 ; VTR+ = 上转换电压码元 ; VCODE = (码元)10 × VLSB, VTR+ = VCODE + (1/2)VLSB; VTR– = VCODE – (1/2)VLSB.
LSB; VTR– = VCODE – (/)VLSB.
SBAAA – August
ZHCA068-August
Submit 00 – Revised
2006-Revised
Documentation Feedback January
January 200800 A Glossary of Analog-to-Digital Specifications
术语词汇表 and Performance Characteristics
：模数转换的规格和性能特点
www.ti.com
www.ti.com
Glossary of Terms
Glossary of Terms
Calibration: www.ti.com
Glossary of Terms
Calibration:
• Background Calibration–
• Background Calibration–
Background calibrations are pre-programmed and occur at a scheduled frequency during converter
校正:
Background
operation without calibrations
further are pre-programmed
instructions. During aand occur at acalibration,
background scheduledthe frequency
converter during converter
is disconnected
• 背景校正法 operation without
from the input further
signal and instructions. During
an internal offset a background
and/or calibration,
gain calibration theThe
occurs. converter
resultsisfordisconnected
each
from the input
calibration
背景校正法是预先编好程序 are signal
storedand ，an
in the internalregisters
internal offset and/or
在转换时不需要进一步的指令就能对预订的频率进行校正 of thegain calibration
converter and occurs.
applied The results
to every 。for each after the
conversion
在背景校
calibration are stored in the
occurs. The converter internal registers of the
algorithm subsequently converter and applied to every conversion
adds or subtracts the offset calibration after the
value
正法中，转换器与输入信号相互断开，而在内部进行偏置校正。每一类的校正都被存储在转换器内置的
calibration occurs. Theresult.
with every conversion converter
The algorithm
converter subsequently
algorithm alsoadds or subtracts
divides the offset calibration
the gain calibration value with value
every
寄存器中 with every conversion result. The converter
，并可以在随后的的每次转换中使用
conversion. algorithm also divides the gain calibration value with every
。转换器的运算法则会在后来的每次转换结果中增加或减
去偏置校正量 conversion.
• Self-Calibration–
，同时算法也会在每次转换中划分增益校正。
• Self-Calibration–
• 自校正 On command, a self-calibration occurs as the converter is disconnected from the input signal. Once
On
this command,
calibration aoccurs,
self-calibration occurs
the converter as the converter
performs an internalisoffsetdisconnected fromcalibration
and/or gain the input algorithm.
signal. Once The
接受指令后
this
converter 转换器与外部输入信号断开后即开始自校正
calibration
，algorithmoccurs, the converter
subsequently adds performs an internal
or subtracts 一旦自校正开始
offset
。offset
the and/or gain
calibration ，转换器执行一个内部
valuecalibration
with every algorithm.
conversionThe
converter
result. Thealgorithm
偏置或者是增益校正算法 converter subsequently
algorithm also adds or subtracts
divides
，其运算法则会在后来的每次转换结果中增加或减去校正偏置量 the gain the offset calibration
calibration value withvalue
everywith every conversion
conversion.
。
• result.
System The converter algorithm also divides the gain calibration value with every conversion.
Calibration–
• 系统校正 • System Calibration–
On command, a system calibration occurs with the input signal connected. In this mode, the converter
接受指令后
On command, 系统开始自校正
，offset a and
system ，同时与外部输入信号相连接
calibration occurs with the input 。在这个模式下
signal connected. ，转换器可以按照两条
In thiscommands.
mode, the converter
calibrates gain, including the external input signal(s), on two separate The offset
calibrates
calibrationoffset
独立的指令进行偏置校正和增益校正 and gain,
is performed including
with the external
the包括外部输入信号
， assumed input
zero applied signal(s),
to the input
。当转换器的外部输入为零的情况下 on two separate
of the converter. commands.
The
，执行的 The offset
converter
calibration
algorithm is performed
subsequently with
adds
是偏置校正。它的运算法则会在后来的每次转换结果中增加或减去偏置校正量。在转换器的输入为满量 the
or assumed
subtracts zero
the applied
offset to the
calibration input
value of the
with converter.
every The
following converter
conversion
algorithm
result. Thesubsequently
user can then adds or subtracts
perform the gainthe offset calibration
calibration value with
with an assumed every following
full-scale conversion
signal applied to the
程值的状态下 result.
input. ，执行的是增益校正
The
The user can then
converter ，同时算法也会在每次转换中划分增益校正
perform
algorithm alsothe gain calibration
divides with an assumed
the gain calibration value with full-scale signal applied
every following to the
conversion.
时钟: input. The converter algorithm also divides the gain calibration value with every following conversion.
Clock:
• 占空比 Clock:
• Duty Cycle–
•时钟信号的占空比是时钟信号在高电平
Duty
The dutyCycle–
cycle of a clock signal is the ratio of the time
（时钟脉冲宽度 the clock signal remains at a 。
）的时间与时钟周期的时间之比 logic
占空比通 high (clock
The
pulse duty cycle
width) to of
the
常用一个百分数来表示，一个完美的方波或微分正弦波的占空比是50%。a clock
period signal
of the is the
clock ratio
signal.of the
Duty time
cycletheis clock signal
typically remains
expressed asat a
a logic high (clock
percentage value.
pulse
The dutywidth)
cycle to the
of aperiod
perfectofsquare
the clockwavesignal.
or a Duty cycle is
differential sinetypically
wave is expressed
0%. as a percentage value.
• 抖动• The duty cycle of a perfect square wave or a differential sine wave is 0%.
Jitter–
•A/DJitter–
转换器的时钟对采样边沿
The standard deviation of（可以是上升沿或下降沿
clocking the A/D converter ，取决于特定的
sampling edge A/D 转换器
(can be ）进行计时
a rising edge，会产 or falling
生标准偏差 The
edge, standard deviation of clocking
depending on the specific A/D converter)
。这种时钟的不稳定性会导致转换误差 the A/D converter sampling edge
variation from pulse-to-pulse
，同时带来转换器噪声的增大 (can be a rising edge or falling of
in time. This instability
。转换器的综合抖动包
edge, depending
the clock signal may on the
causespecific A/D converter)
converter variation
errors as well as anfrom pulse-to-pulse
increase in converter in time.
noise.This instability of
括孔径抖动和时钟抖动
the 公式为
，may ：
Theclock signalincludes
total jitter cause
bothconverter
aperture and errors as well
clock jitter,asandan isincrease
equal to:in converter noise.
The2 total2 jitter includes both aperture and clock jitter, and is equal to:
tj = (ta2 +�tc2)
tj = (ta +�tc )
其中: Where:
• taWhere:
是孔径抖动的均方根 ;
• ta is the root-mean-square of the aperture jitter;
•
• t
ta is
is the
the root-mean-square
root-mean-square of the
of the clock
aperture
jitterjitter;
• tc 是时钟抖动的均方根
c
• tc is the root-mean-square of the clock jitter
There is no correlation between the clock-jitter
孔径抖动和时钟抖动之间没有相互的关联 and aperture-jitter terms; therefore,
，因此这两项可以合并写为一项，写成平方和的开方these terms can be
There
combined is nooncorrelation
a root-sum-squarebetween the basisclock-jitter
(rss). In mostand aperture-jitter terms;
cases, the clock therefore,
jitter is severalthese
timesterms can
higher be
than
(rss)。通常情况下
combined on时钟抖动的影响比
，
the A/D converter a root-sum-square
aperture jitter, A/D 转换器孔径抖动影响的数倍
basis
making (rss).
the In most
clock cases,
jitter ，因此
the
the dominant
时钟抖动决定了系统的抖
clock，jitter
jitter is several
noise sourcetimes higher
in the than
system.
动噪声源 the A/D converter
。同时时钟抖动会对转换器的中频和高频段的信噪比
Clock jitter can impact aperture jitter,ofmaking
the SNR the clock
the converter at jitter the产生影响
SNR
medium dominant 。jitter
and higher noise source
而孔径抖动与采样系统的
frequencies. Theinaperture
the system.
jitter,
Clock jitter
along with ，
时钟抖动结合起来 can
clock impact the SNR of the
jitter of the sampling system,
对转换器整个频段的信噪比 converter
SNR都会产生影响 at medium and
impacts the overall higher frequencies.
SNR of the conversion.
。抖动对转换器信噪比 The
SNR产生的影 aperture
The jitter,
along with clock
contribution of jittertoofthe
jitter theSNR
sampling
of the system,
conversion impacts
is the to:
equal overall SNR of the conversion. The
响可以写为：
contribution of1 jitter to the SNR of the conversion is equal to:
SNR�=�20log10(��)
(2�1f�tj)
SNR�=�20log10(��)
(2�f�tj)
Where:
其中 Where:
• tj is the clock and aperture jitter;
•• tfj is
is the
the clock
clock frequency
and aperture jitter;
of the converter
• tj是时钟抖动和孔径抖动 ;
• f is the clock frequency of the converter
• Slew
• f 是转换器的时钟频率 Rate–
• Slew
The time Rate– derivative (δV/δt) of the clock signal (digital input or digital output) as it passes through the
• 转换速率 The time
logic, voltage derivative (δV/δt) of the clock signal (digital input or digital output) as it passes through the
threshold.
logic, voltage
在时钟信号 threshold.
（可以是数字信号输入或输出）超过逻辑阈值电压时，时钟信号的时间导数。
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Code Width: The code width is the voltage differential between two adjacent transition points of an
Glossary
Glossary ofA/D
of Terms
Terms
Code
converter Width:
digital Thecode.
output codeThe
width is the
code voltage
width differential
is ideally equal tobetween two adjacent
LSB. See Figure .transition points of an A/D
Code Width:
converterThe codeoutput
digital width is the voltage
code. The differential
code width is between
ideally two to
equal adjacent
LSB. transition
See Figurepoints of an A/D
. LSB。
码元宽度是 A/D转换器数字输出的相邻转换点电压宽度
converter digital output code. The code width is ideally 理论上码元宽度等于一个最低有效位
。equal to LSB. See Figure . 见图6.
111 Ideal�transfer�function
for�a�3-bit�A/D
Transition�point =�where
111 Ideal�transfer�function
110
111 for�a�3-bit�A/D
Ideal�transfer�function
output�code�changes
output�code�changes
110 for�a�3-bit�A/D from�one�code
101
110 output�code�changes
from�one�code
Digital
Transition to�an�adjacent�code
101
Points Transition from�one�code
to�an�adjacent�code
Output Digital
100
101
Code
Digital Output
TransitionPoints to�an�adjacent�code
100
Points
Output Code
011
100
Code 011 code�width
010
011 Ideal�code�width =
code�width
010 code�width 1LSB Ideal�code�width =
001
010 Ideal�code�width
1LSB =
001 1LSB
000
001
000
000 0 1/4�FS 1/2�FS 3/4�FS FS
0 Analog�Input�Voltage
1/4�FS 1/2�FS 3/4�FS FS
0 1/4�FS 1/2�FS 3/4�FS
Analog�Input�Voltage FS
NOTE: The unipolar ideal transfer function has zero Offset Error, zero Gain Error, zero DNL error, and zero INL error.
Analog�Input�Voltage
NOTE:
In this graph, FSThe unipolar
means ideal transfer function has zero Offset Error, zero Gain Error, zero DNL error, and zero INL error.
Full-Scale.
NOTE: The unipolar
In this
注意：具有零偏移误差 graph,ideal
FS transferFull-Scale.
means
，零增益误差 function
，零DNL has zero Offset
误差和零 INL误差 Error,
。 zero Gain Error, zero DNL error, and zero INL error.
Figure 6. Unipolar Ideal Transfer Function
In this graph, FS means Full-Scale.
Figure图6. Unipolar Ideal Transfer Function
6. 单极理想传输函数
Figure 6. Unipolar Ideal Transfer Function
Code Transition Point (Uncertainty): The Code Transition Point is the point at which the digital output
Code
switches fromTransition
one code Point
码元转换点（不确定性）：当模拟输入变化时 to the (Uncertainty):
next as a result， The aCode Transition
analogPoint
of转换器的数字信号输出也随着变化
changing inputisvoltage.
the point， at which
The the digital
uncertainty
从一个代码跳变到另一 or output
Code Transition
switches
variation in the Point
from one
transition (Uncertainty):
code
point to
is the
a resultThe
next as
of Code
a Transition
result
internal of a Point
changing
converter isanalog
noise, theFigure
as point at
input
which
voltage.theThe
illustrates. digital output or
uncertainty
个代码
switches，其中的跳变点就是码元转换点
from one code to the next 。而转换器的内部噪声导致了码元转换点的不确定性，或者叫抖动，
variation in the transition pointasisaaresult
resultofofainternal
changing analog noise,
converter input voltage.
as Figure The uncertainty
illustrates. or
variation
如图 7 所示 in
。 the transition point is a result of internal converter noise, as Figure illustrates.
111 Code
under�testCode
111
110
111 Code under�test
under�test
100%
110
101
110 0% 100%
Output
50% 100% Center�of�code�width

101 0%
Digital Output
100
101 0% 50% Center�of�code�width
Output
50% Center�of�code�width
100
DigitalDigital
011
100
011 Low�side�transition
010
001
010
001 Transition�point;�uncertainty�noise
000
000 0 1/2�FS FS
0 Analog Input 1/2�FS FS
0 1/2�FS
Analog Input FS
Figure 7. A/D Converter Transition Noise
Analog Input
Figure 7. A/D
图 7. A/D Converter Transition Noise
转换器的转换点噪声
Figure 7. A/D Converter Transition Noise
Coherent sampling: Coherent sampling exists when the sampling frequency times the integer number of
cycles Coherent
of the waveform
相干采样：当满足以下条件时产生相干采样 sampling:
in theCoherent sampling
data record equalsexists when theof
the frequency sampling
，即采样频率乘以数据记录中波形的整数个周期等于波形的频率 frequency
the waveform times
times the integer
the number of number of
Coherent
samples cyclesin sampling:
theof the
data Coherent
waveform
record, in
wheresampling
the data
the exists
record
waveform when
equals
is the
periodic.sampling
the frequency
In otherfrequency
of the
words, times the
waveform
coherent integer
times
sampling number
the ofof
number
exists
乘以数据记录中的采样数
cycles of the waveform in 其中的波形是周期性的
，the data record equals 。换句话说
the frequency，只有当满足下式的情况下才会有相干采样
of the waveform times the number of 。
when thesamples followingin the data record,
relationship where the waveform is periodic. In other words, coherent sampling exists
is met:
samples when in thethedata record,
following where the iswaveform
relationship met: is periodic. In other words, coherent sampling exists
fS � K��=�f N
when thefS � following
K��=�ft � N relationship is met:
t �
fWhere:
S � K��=�ft � N
其中
• Where:
f = the sampling frequency
Where: S • f = the sampling frequency
••• fSK = number
fS==采样频率
S
theKsampling
of cycles of a waveform in the data record (integer)
frequency
• f = •
the = number
waveform of cycles of a waveform in the data record (integer)
frequency
•• KK==数据记录中的波形的周期数
t
number of cycles of a waveform (整数 ) data record (integer)
in the
• N = number• ft = the
of samples infrequency
waveform the data record
• f = the waveform frequency
• ft t= • N = number of samples in the data record
波形的频率
•• NN== 数据记录中的采样数
number of samples in the data record
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Glossary of Terms www.ti.com

Glossary of Terms
Complementary Offset Binary (COB): COB coding begins with digital zero (0000, for a -bit system) at
偏移二进制补码
the (COB):
positive full-scale. 二进制补码从数值零
By (0000,count,
incrementing the digital 对于一个 4比特的系统)开始
the corresponding ，对应的是正数的最大值
analog value approaches the 。随
negative full-scale in –LSB steps, passing through
着数值的增加，对应的模拟电压朝负最大有效值增大，每次变化一个最低有效位(LSB)，中间经过双极零码。 BPZ on the way. This zero crossing occurs at a digital
code of 0 (see Table ). As the digital count continues to increase, the analog signal goes more
此时对应的数字值是0111（见表3）。随着数值的增加，模拟输入量朝负最大值变化，当模拟输入达到负最大
negative until the negative full-scale is reached at a full digital count (), as shown in Table .
有效值时数字增大到1111，见表3。和COB编码类似，按照COB编码，最高有效位（MSB）可以看成是符号
With COB coding, like BOB coding, the MSB can also be considered a sign indicator where a logic ''
位。当MSB
indicates 是逻辑'1'analog
a negative 则表示模拟电压是负的，当
value, and a logic '0'MSB 是逻辑
indicates an'1'analog value greater than orBPZ。
则表明模拟电压大于或等于 equal见表 3
to BPZ.
See Table .
(1)(2)
编码表Scheme (1) (2)
Table 3. 表 3. COB
COB Coding
–FS — –.000 –.
0 –. –. –.0
0 –.0 –.0 –.
00 –. –. –.
/ –FS 0 –. –.00 –.
00 –. –. –.
00 –. –.0 –0.
BPZ – VLSB 000 –0. –0. –0.
BPZ 0 –0. 0.000 +0.
BPZ + VLSB 00 +0. +0. +0.
00 +0. +.0 +.
000 +. +. +.
/ +FS 00 +. +.00 +.
000 +. +. +.
000 +. +.0 +.0
+FS 0000 +.0 +. —
(1)
() FSR = ±5V.
FSR = ±V.
(2)
() VV
TR– = 下转换电压码元 ; VTR+ = 上转换电压码元
= lower code transition voltage; V = ;upper
VCODE =code
(码元 )10 ×VLSBvoltage;
transition , VTR+ = V
VCODE +(1/2)VLSB; V
= (digital TR– = VCODE
code) x V – (1/2)V
, V LSB=. V +
TR– TR+ CODE 0 LSB TR+ CODE
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Glossary of Terms
Glossary of Terms
标准二进制补码(CSB): 标准二进制补码表正好与单级标准二进制码相反（换句话说就是补码）。CSB编码和
Complementary Straight Binary Code (CSB): The Complementary Straight Binary coding scheme is the
USB编码一样
exact ，也是受单级系统的限制
digital opposite 。当用CSBof
(that is, one’s complement) 对一个数字系统进行编码时，二进制数字从数值零
Unipolar Straight Binary. CSB coding, as with USB(0000,
code, is also restricted to unipolar systems.
对于一个4比特的系统)开始，对应的是正数的最大值。随着数字的增加，对应的模拟电压开始减小，每次变 When using CSB coding with a digital system, the digital count
begins at all zeros (0000, for a -bit system) at the positive full-scale value. As the digital code increments,
化一个VLSB，即一个最低有效位(LSB)所对应的电压。一直减小到0V，所对应的数字是1111.CSB编码和相对应
the analog voltage decreases one VLSB at a time, until 0V is reached at a digital code of . The
relationship between CSB coding 4.（
的模拟电压之间的关系可以参看表 and 在表
its corresponding analog voltages ）。
4中，BPZ和双极归零码相类似 can be seen in Table . (In
Table , BPZ is analogous to Bipolar Zero.)
(1) (2)
Table 4. 表
CSB Coding
4. CSB 编码表Scheme
(1)(2)

Zero — 0.000 0.
+VLSB 0 0. 0. 0.
0 0. .0 .
00 . . .
/ FSR 0 . .00 .
00 . . .
00 . .0 .0
000 .0 . .
/ FSR 0 . .000 .
00 . . .
00 . .0 .
000 . . .
/ FSR 00 . .00 .
000 . . .
000 . .0 .0
+FS 0000 .0 . —
(1)
() FSR = 10V.
FSR = 0V.
(2)
() VTR– ==下转换电压码元
V ; VTR+ =voltage;
lower code transition 上转换电压码元 ; VCODEcode
VTR+ = upper = (码元 )10 × Vvoltage;
transition LSB, VTR+ = VCODE =+(1/2)V
VCODE ; VTR– = V
(digitalLSBcode) CODE – (1/2)VLSB.
TR– 0 x VLSB, VTR+ = VCODE +

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Glossary of Terms
共模, DC:
Common-mode, DC:
• 误差–
• Error–
当转换器的两个差分输入量改变相同的数值时，其输出量的变化就是共模误差。这种情况适用于带有差
Common-mode error is the change in output code when the two differential inputs are changed by an
equal amount.
分输入的转换器，比如 ThisAspecification applies where LSB
IN+ 和AIN–。共模误差一般用 a converter
来表示。has a differential input, AIN+ and AIN–. This
term is usually specified in LSBs.
• 输入范围–
• Range–
由于转换器的外接器件所受的限制
The common-mode, analog voltage 这就决定了
，range at theA/D 转换器的差分输入范围
differential ，也就是共模
input of the A/D ，外接的模拟输
converter while the
入范围 converter
。 still converts
这种情况出现在转换器的输入差分电压 accurate code in accordance
（AIN+ AIN–）
和 with the specific
相对小的时候 device
。 limits. This specification
applies when the input voltages applied to the converters has a relatively small differential input, AIN+
• and信号A– .
IN–
• Signal–
输入的共模信号等于(AIN+ + AIN–) / 2，这个数值也叫做共模电压。这种情况出现在转换器的有输入差分电
The input common-mode signal is equal to (AIN+ + AIN–) / . Another name for this specification is
压（A IN+和AIN–）的时候。
Common-mode Voltage. This specification applies when the input voltages applied to a converter have
• a电压 differential
– input, AIN+ and AIN–.
• Voltage–
共模电压等于两个模拟输入电压之和，再除以二。
The common-mode voltage is equal to the sum of the two analog input voltages divided by two.
共模抑制比(CMRR):共模抑制比是用来衡量抑制共模信号（直流或交流）跨越差分输入阶段的能力。这个比
Common-mode Rejection Ratio (CMRR): The Common-mode Rejection Ratio is the degree of rejection
率等于输出的数字信号比上所输入的共模信号的变化量。
of a common-mode signal (dc or ac) across the differential input stage. This specification is the ratio of the
resulting
补码 (CTC):digital
在补码编码中output signal to a changing input common-mode signal.
，数字零是一个比模拟双极零信号稍小的模拟电压量，实际上是小了一个最低有效
Complementary
位 (1LSB)。随着数字的增加 Twos Complement
，对应的模拟电压开始减小(CTC): With CTC ，coding, digital zero is at an analog voltage that
直到除最高有效位以外所有的位数都变为高 is
，变成
slightly less (LSB) than analog bipolar zero.
0111(对于一个4比特的系统)。这时候，该数字值对应的是模拟信号的负最大值。下一步要继续增大数字值， As the digital count increments, the analog voltage becomes
more negative until all of the bits are high except for the MSB (0, for a -bit system). At this point, the
只能把最高有效位 MSB变为逻辑
digital code corresponds '1'，而其它比特位则为逻辑
to the analog negative full-scale. The '0'(1000); 这个数字值代表了模拟信号的正数最
next step in incrementing the digital code
would
大值。be to have the MSB set
当数字值继续增大时 to a logic '', and the rest of the
，所对应的模拟电压值开始下降，一直到 bits asBPZ.
logic
表'0's (000); this code then
5画出了模拟量和数字量之间的
represents the analog positive full-scale value. As the digital codes continue to increment, the
关系。按照 CTC 编码，最高有效位（MSB）可以看成是符号位。 MSB
当是逻辑 '0'则表示模拟电压是负的，
corresponding analog voltage decreases until BPZ is obtained. Table illustrates this analog/digital
逻辑 '1'则表明模拟电压是正的
relationship. With Complementary 。 Two’s Complement coding, the MSB is also a sign indicator with its
states of '0' and '' representing negative and positive voltages, respectively.
(1)(2) (1) (2)
Table 5.表
CTC Coding
5. CTC 编码表Scheme
–FS 0 — –.000 –.
00 –. –. –.0
00 –.0 –.0 –.
000 –. –. –.
/ –FS 00 –. –.00 –.
000 –. –. –.
000 –. –.0 –0.
BPZ – VLSB 0000 –0. –0. –0.
BPZ –0. 0.000 +0.
BPZ + VLSB 0 +0. +0. +0.
0 +0. +.0 +.
00 +. +. +.
/ +FS 0 +. +.00 +.
00 +. +. +.
00 +. +.0 +.0
+FS 000 +.0 +. —
(1) FSR
()
FSR=± 5V.
= ±V.
(2) VTR–
() =
VTR–下转换电压码元 ; VTR+ = 上转换电压码元
= lower code transition voltage; VTR+ =; VCODE =code
upper (码元transition
)10 × VLSBvoltage;
, VTR+ = V
VCODE +(1/2)VLSB; Vcode)
CODE = (digital TR– = VCODE – (1/2)VLSB.= VCODE +
0 x VLSB, VTR+
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Glossary of Terms
Conversion Cycle: A conversion cycle is a discrete A/D converter operation, and refers to the process of
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changing the input signal to a digital result. When performed by a SAR converter, for example, theof Terms
Glossary
conversion occurs after the sample is acquired. For delta-sigma converters, a conversion cycle refers to
the tDATA time period (that is, the period between each data output). With delta-sigma converters, each
digital output is actually based on the modulator，
转换周期：一个转换周期是离散的模数转换过程 results from several tDATA time periods. 。举个例子，如过
包括把模拟输入转换为数字输出的过程
Conversion
使用的是SARMaximum 逐次逼近转换器 Rate:， The maximum sampling rate of a device
转换过程是在采样结束之后才开始。对于 while performing
delta-sigma 转换器 within specified
，转换周期涉及
operating limits. All parametric testing is performed
到tDATA（即输出每个数据之间所需要的时间）。因此，几个调制器的tDATA时间决定了delta-sigma at this sampling rate unless otherwise noted. (Also
转换器see
Sample Rate.)
的数字输出。
Conversion Minimum Rate: The minimum conversion rate is the minimum sampling rate at which the
A/D converter meets its stated specifications.
最大转换速率：在指定的工作模式内器件最大的采样速率。所有的参数都在这个最大转换速率下进行测试，
如果不是则会特殊说明（请参考采样率）
Conversion Rate: The frequency of the digital output words at the output of the converter. (See also
Sample Rate.)
最小转换速率：最小转换速率是在指定的工作条件下，A/D转换器最小的采样速率。
Conversion Speed: See Sample Rate.
转换速率:转换器输出转换字长的频率（请参考采样率）。
Conversion Time: After sampling the signal, the conversion time is the time required for a SAR or
转换速度: 请参考采样率。
pipeline A/D converter to complete a single conversion. The conversion time does not include the
acquisition
转换时间：对信号进行采样后time or multiplexer，SAR
set-up逐次逼近转换器或流水线转换器完成一次转换过程所需的时间就是转换
time. The conversion time for a given device is less than the
throughput time.
时间。这里的转换时间不包括采集时间和多路复用器的开关设置时间。一会器件的转换时间要小于它的吞吐
Crosstalk:
量时间。 This term refers the condition in which a signal affects another nearby signal. With A/D
converters, this event is the occurrence of an undesirable signal coupling across a multi-channel A/D
converter from one channel that is not being used in the conversion
串扰：这个概念用来衡量一个信号对临近信号的干扰程度。数模转换过程中 to another channel that is part of the
，串扰是一种有害的信号耦合现
signal
象，它发生在多通道的A/D转换器中，从一个未使用的信道干扰另一个使用中的信道from
path. This undesired coupling is a result of capacitive or conductive coupling one channel to
。这种有害干扰是由信
another. This interference appears as noise in the output digital code.
道对临近信道电容耦合或者电阻耦合引起的，在数字信号输出端表现为噪声。
Cutoff Frequency: The cutoff frequency (fCUT-OFF) of a low-pass analog or digital filter is commonly
截止频率：低通模拟信号或数字滤波器的截止频率
defined as the –dB point for a Butterworth and Bessel (fCUT-OFF)
filter,一般定义在 Butterworth
or the frequency 和Bessel
at which 滤波器的
the filter –3dB
response
leaves
点上，或者是 the error band for滤波器的误差带边缘上
Chebyshev the Chebyshev filter. See。见图 Figure
8. .
fCUT-OFF
M�=�filter�order �
Gain (dB)
APASS
fSTOP
AMAX
ASTOP
Passband Transition Stop�band Frequency (Hz)

band
Figure 8. Key Analog and Digital Filter Design Parameters

8.
图模拟和数字滤波器设计的关键参数
Data Rate or Data Output Rate: The rate at which conversion results are available from a converter. For
a SAR converter, the data rate is equal to the sampling frequency, fS. With a delta-sigma
数据速率或数据输出速率：在这个频率上转换器能够正常进行转换并输出数据 converter, the ，
。对于SAR逐次逼近转换器
data rate is equal to the modulator即 frequency (fMOD) divided转换器
by the decimation ratio.
它的数据输出速率等于采样速率， f S。而对于 delta-sigma ，数据输出速率等于调制器的频率 (fMOD)除
Data
以抽样率 Valid。 Time: The time (as measured in A/D converter clock cycles) between the first clock transition
where data is valid and the last clock transition where data is no longer valid.
数据有效时间：它由A/D转换器的时钟周期来决定，从第一个数据有效的时钟脉冲过度点到下一个数据无效
Decibels (dB): Decibels are a logarithmic unit used to describe a ratio of two values; one value is
的时钟脉冲过度点
measured while the 中间这段时间就是数据有效时间
，other 。 may measure power, sound pressure, voltage, or
value is a reference. The ratio
intensity.
分贝(dB):分贝是一个对数坐标的单位，用来衡量两个数值的比；测量其中的一个数值，另一个作为参考量。
这个比率可以用来衡量功率、声压、电压或者强度。
ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 11

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Glossary of Terms
Glossary of Terms
dBFS: dBFS is the decibel measurement as it is referred to the full-scale input range.
dBFS: dBFS是用于表征输入的分贝大小的单位
dBc: Decibels referenced to a carrier, or decibels below a carrier. For example, a spurious signal or
distortion less than –0dBc means
dBc: 用来表示载波的强度大小 that the distortion is at least 0dB
，或者指低于载波强度大小的数值。比如 less than the specified carrier signal –
，一个杂散信号或噪声的强度小于
or desired signal level.
40dBc ，这说明杂散信号或噪声的强度至少比该载波信号
dBm: dBm represents a measured power level in decibels relative to mV.
dBm: dBm 表示每1mv测量的信号电压所对应的信号分贝强度
Decimation Ratio: The decimation ratio is the ratio between the output sampling rate of the delta-sigma
modulatordelta-sigma
抽样率：调制器的采样输出速率和delta-sigma转换器的数据输出速率的比值就是抽样率。抽样滤
and the output data rate of a delta-sigma converter as performed by the decimator. The
decimator is a block that decimates or discards
波器是一个用来抽样或过滤信号的模块 some results. The decimation ratio，sets
。抽样比率决定了调制器的数据采样的数量 the number of
再把调制结果加起来平
data samples from。
均，最后得出结果 the modulator that are averaged together to ，
高的采样率会选取更多的数据进行综合平均 get a result. Higher decimation ratios
因此得出的结果中噪声更小
average a greater number of values together, thereby producing lower noise results.
Delta-Sigma转换器(ΔΣ): Delta-Sigma转换器是个一比特（或多比特）的采样系统（见图9）.在这个系统
Delta-Sigma Converter (ǻȈ): A delta-sigma converter is a one-bit (or multi-bit) sampling system (see
中，多比特数据被连续地送到一个数字滤波器
Figure ). In this system, multiple bits are sent，在那里进行数学运算
serially 。这个图表显示了一个
through a digital FIR（有限冲击
filter where mathematical
manipulation
响应）滤波器is 。performed.
另一种可选择的滤波器是This diagram IIR（
illustrates
无限冲击响应a FIR (Finite
）滤波器 Impulse Response) filter.。Another filter
。请参考数字滤波器
option could be IIR (Infinite Impulse Response). Also see Digital Filter.
Sample�rate�(fS)
fS
Analog Delta-Sigma =�DR�(decimation�ratio)
fD
Input Modulator
Data�rate�(fD)
Digital Digital
Decimator
Filter Output
Digital�Decimating�Filter
(usually�implemented
as�a�single�unit)
NOTE: The analog portion of a delta-sigma converter can be modeled using a optional input Programmable Gain
注意(PGA),
Amplifier ：delta-sigma
followed转换器的模拟部分看成这样的一个模型即一个可选的输入可编程增益放大器
by a charge-balancing A/D converter.，The 后面
digital portion is modeled using a，low-pass digital
再接一个电荷平衡的 A/D 转换器。delta-sigma
filter followed by a digital decimation filter. 转换器的数字部分看成一个低通数字滤波器后面接上一个
数字抽样滤波器。
Figure 9. Block Diagram of a Delta-Sigma A/D Converter
图9.一个Delta-Sigma A/D转换器的方框图
Differential Gain: see Gain.
Differential Gain Error: see Gain Error.
差分增益: 见增益.
Differential Phase Error: The difference in phase between a reconstructed output and a small-signal
input.
差分增益误差: 见增益误差
Differential Nonlinearity (DNL): An ideal A/D converter exhibits code transitions at analog input values
spaced
差分相位误差 exactly LSB apart (LSB = VFS / n). DNL is the deviation in code width from the ideal LSB
: 重构后的输出信号与输入信号之间的相位差
code width. A DNL error less than –LSB can cause missing codes.
差分非线性度(DNL): 一个理想的A/D转换器的信号输出以模拟输入为模板，并且最高分辨率为1LSB(1LSB =
VFS / 2n).DNL是码元宽度与理想1LSB码宽的差值。当一个DNL误差小于–1LSB时就会造成输入码丢失。

2008
A Glossary of Analog-to-Digital Specifications and Performance Characteristics SBAAA – August 00 – Revised January
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Glossary of Terms
Glossary of Terms
DNLDNL is a在图像处理
critical specification for image-processing, closed-loop,
、闭环和视频应用软件中是一个关键参数 dc可以吧
and video applications. This is a ，
。在近似直流的模拟输入电压测量中
specification, where measurements are taken
DNL看成一个直流参数。其它的直流量参数包括偏置误差、增益误差、INL、未调整的总误差(TUE)和过渡误 with near-dc analog input voltages. Other dc specifications
include Offset Error, Gain Error, INL, Total Unadjusted Error (TUE), and Transition Noise. Figure 0
差。在图10the
illustrates 中，理想传输函数用实线表示
ideal transfer function as a，DNL 用虚线表示
solid line and the。DNL error as a dashed line.
111
110 Actual
Transfer
101 Function
Digital
Output 100 Ideal
Code
Transfer
011 Function
010
Wide�code�(>1�LSB)
001
000
Narrow�code�(<1�LSB)
Analog Input Voltage
NOTE:
注意：DNLDNL是理想码元宽度和测量码元宽度之间的差异值
is the difference between an ideal code width
。 and the measured code width.
Figure 10. Differential Nonlinearity Error
图10. 差分非线性度
Digital Filter: A digital filter uses on-chip digital functions to perform numerical calculations on sampled
values of the input signal. The on-chip digital functions are dedicated functions
数字滤波器：数字滤波器使用集成片上系统对采样的输入信号进行数学计算。在 delta-sigma
included in the转换器中
delta-sigma
，片
converter. A digital filter works by performing
上系统的数学函数采用的是专门的算法。数字滤波器的工作原理是通过对中间过渡信号进行数字化的数学运 digital math operations on an intermediate form of the signal.
This process contrasts with that of an analog filter, which works entirely in the analog realm and must rely
算，这个过程和模拟滤波器不一样，模拟滤波器是完全依靠电子元件（比如电阻、电容、晶体管等等）组成
on a physical network of electronic components (such as resistors, capacitors, transistors, etc.) to achieve
a desired filtering effect.
的网络的物理特性来达到预期的滤波效果，并且只能工作在模拟电路领域。
Digital Filter, Finite Impulse
数字滤波器，有限冲击响应 (FIR)Response
滤波器：有限冲击响应 (FIR) filter: A(FIR)
finite impulse response (FIR)。filter
滤波器是一类数字滤波器 is a type of a
之所以称为有限是因
digital filter. It is finite because its
为脉冲在它上面激起的响应最后都衰减为零。这种响应和无限冲击响应(IIR)不同，它的内部有反馈回路 response to an impulse ultimately settles to zero. This type of response，因
contrasts with an infinite impulse response (IIR) filter that has internal feedback and may continue to
respond indefinitely. An。FIR filter has a(FIR)
此可以无限地响应下去有限冲击响应滤波器有几个很有用的特点
number of useful properties. FIR 它可以保持在稳定状态这是因为
， filters are inherently stable.
， This
stability exists because all the
它所有的极点都位于原点上 poles are located ，
，也就都在单位圆内 at这就保证了它的稳定性
the origin and are therefore 。FIRlocated within the unit
滤波器是一个线性相位或者
circle. The FIR filter is a linear-phase or linear-plus-0°-phase response digital filter. A moving average
相位超前 90度的线性数字滤波器。滑动平均滤波器就是一个结构非常简单的FIR滤波器。
filter is a very simple FIR filter.
数字滤波器，无限冲击响应(IIR)滤波器：一个脉冲输入无限冲击响应(IIR)滤波器会形成无限长时间的非零响
Digital Filter, Infinite Impulse Response (IIR) filter: IIR filters have an impulse response function that is
non-zero
应 over an infinite length
。这个特点和有限冲击响应 (FIR)of 滤波器很不同
time. This characteristic contrasts with finite impulse response
，它只是形成了固定时间长度的脉冲响应。模拟滤波器可以 filters
(FIR), which
有效地实现IIR滤波器的功能。 have fixed-duration impulse responses. Analog filters can be effectively realized with IIR
filters.
数据接口，SPI™:串行外设接口，即SPI，是一个三线或是四线的接口。通过这个接口，A/D转换器可以典型
Digital Interface, SPI™: – Serial peripheral interface, or SPI, is a three- or four-wire interface. With this
地设置为从器件
interface, the A/D 。结合 SPI接口
converter ，A/D转换器可以通过主
is typically a slave device. A/D /从器件关系和外界进行通信，其中主器件可以构筑
converters with SPI capability communicate
using a master/slave
整个数框架 relationship, in which the master initiates the data frame.
。当主器件产生一个时钟脉冲信号并选中其中的一个从器件时 When the master generates
，数据就可以在二者之间输入或输
a clock
出 and selects a slave device, the data is either transferred in or out, or in both directions
，或者同时进行双向输送。
simultaneously.
SPI 指定了四个信号：时钟信号(SCLK);主器件数据输出，从器件数据输入(MOSI); 主器件数据输入，从器件
SPI specifies four signals: clock (SCLK); master data output, slave data input (MOSI); master data input,
slave data
数据输出 (MISO);
output从器件选择信号
(MISO); and slave (SS)。 select
时钟信号 SCLK是由主器件产生
(SS).(SCLK) is generated by，the master and input to all。slaves.
并且发送给所有的从器件从器件
MOSI carries data from master to slave.
数据输入(MOSI)是主器件发送给从器件的数据信号，从器件数据输出(MISO)则是从器件返回主器件的信号 MISO carries data from slave back to master. A slave device is 。
selected when the master asserts its CS signal. Because it lacks built-in device addressing, SPI requires
more effort and more hardware CS
当主器件给某个从器件发送片选信号时，than
resources 该从器件就被选中
IC™ when more 。由于缺乏内置的器件地址编码，当存在超过
than one slave is involved, but SPI tends
2
to be more efficient and straightforward
一个数量的从器件的时候 than I C in point-to-point (single master, single
，SPI比I C™方式需要更多的操做步骤和更多的硬件资源 slave) applications.
。但是在点对点（一个主

SPI can also achieve significantly higher
器件，一个从器件）的工作方式下，SPI比I C™方式要显得更有效更直接，而且SPI可以达到更高的数据传输 data
2 rates than I C.
速率。

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Glossary
Glossaryofof
Terms
Terms
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Digital Interface, I2C™: IC is a two-wire (SDA and SCL) Philips standard interface. The IC interface is
Glossary of-bit
Terms
an
数据接口， serial 2 bus 2with bi-directional data transfer capability. The speeds for I C are 00kbit/s, 00kbit/s
I C™: I C是一个双线(SDA and SCL)的飞利浦Philips标准接口方式，它是一个可以双向数据传输的 www.ti.com
and .Mbit/s. Devices connected to the network are addressable, having unique addresses. This
2I2C™: IC is a two-wire (SDA and SCL) Philips standard interface. The IC interface is
Digital
比特串行总线 Interface,
8 of Termsprotocol has C collision detection
的传输速率可达 100kbit/s, 400kbit/sto prevent
或者是 3.4Mbit/s.
interface
Glossary 。I and arbitration data corruption with two or more ，并且
接入网络的器件是可寻址的
an -bit serial bus with bi-directional data transfer capability. The speeds for IC are 00kbit/s, 00kbit/s
masters
地址唯一on line. 2
。这个接口协议具有冲突检测系统，当线上有两个或更多主器件的时候，能够做出判定并防止数据
and .Mbit/s.
Digital Interface, Devices
I C™:connected to the network
IC is a two-wire (SDA and areSCL)
addressable, having unique
Philips standard addresses.
interface. This
The IC interface is
interface
Dynamic
冲突
an 。 serial
-bit protocol
Range: bus haswithcollision
The ratio detection
of the
bi-directional dataand
maximum arbitration
input
transfer signal to
toprevent
capability. the data corruption
smallest
The speeds input
for I signal.
C arewith two or more
Dynamic
00kbit/s, range can
00kbit/s
masters
be
andspecifiedon line.
.Mbit/s. in terms
Devices of connected
SFDR or SNR. to theThis criticalare
network specification
addressable, sets the limits
having uniqueon addresses.
the detectableThis
动态范围：从最大信号输入速率到最小信号输入速率之间的范围。动态范围可以用 SFDR或SNR来衡量。这
maximum
interface and minimum
protocol has analogdetection
collision signal. and arbitration to prevent data corruption with two or more
Dynamic Range: The ratio of the maximum input signal
个关键的参数决定了模拟信号的最大和最小可探测范围。 to the smallest input signal. Dynamic range can
masters
be specifiedon line.in terms of SFDR or are
SNR. This critical specification sets the limitstheoninput
the detectable
Dynamic Specifications: These product data sheet specifications where to the A/D
maximumis
converter
Dynamic andan minimum
Range:
动态特性：这些是产品的数据资料说明 ac signal.
The ratio analog
This thesignal.
of group of ，
maximumspecifications includes:
input signal
用于描述在交流信号输入的情况下 to the Signal-to-Noise
smallest input A/D Rejection
signal.
转换器的特性 (SNR),
Dynamic 。range
这些特性包 can
Signal-to-Noise
be
括：specified
信噪比 in
(SNR), Ratio
terms
信噪比加上失真plus
of SFDRDistortion
or SNR.(SINAD
(SINAD This
或者 or SNR+D),
critical
SNR+D)， Effective
specification
有效比特数 Number
sets the
(ENOB), Of
limits Bits
on
总的谐波失真 (ENOB),
the Total
detectable
(THD), 无杂波动态
Dynamic Specifications: These are product data sheet specifications where the input to the A/D
Harmonic
maximum Distortion
and (THD), Spurious Free Dynamic Range (SFDR), Intermodulation Distortion (IMD), and
converter
范围 (SFDR), is anminimum
互调失真 ac signal.
(IMD)
analog
This
和全功率带宽
signal.
group of specifications
(FPBW)。见图includes:
11. Signal-to-Noise Rejection (SNR),
Full-power Bandwidth (FPBW). See Figure .
Signal-to-Noise
Dynamic Specifications: Ratio plus These Distortionare(SINAD
product or SNR+D),
data Effective Number
sheet specifications where Ofthe
Bitsinput
(ENOB),
to theTotal
A/D
Harmonic is
converter Distortion (THD),
an ac signal. Spurious
This group of
FREQUENCY�SPECTRUM Free Dynamic Range
specifications (SFDR),
includes: Intermodulation
Signal-to-Noise Distortion
Rejection (IMD), and
(SNR),
Full-power Bandwidth
Signal-to-Noise Ratio (FPBW).
plus See
Distortion
(8192�point�FFT,�F IN Figure
(SINAD
=�10.0022kHz, .or SNR+D), Effective Number Of Bits (ENOB), Total
�0.2dB)
0
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(THD), Spurious Free Dynamic Range (SFDR), Intermodulation Distortion (IMD), and
FREQUENCY�SPECTRUM
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(8192�point�FFT,�F Figure .
IN =�10.0022kHz, �0.2dB)
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�40
B FREQUENCY�SPECTRUM B:�Headroom�= �0.5dB
D �0.2dB)
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�60
0 A:�Fundamental�Signal�Magnitude �96dB
D:�Spurious�Free�Dynamic�Range�=
�40 B
�80
D C B:�Headroom�= �0.5dB �125dB
E:�Average�Noise�Floor�=
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F:�First�Harmonic�Magnitude�= �105dB
�60
�100 A:�Fundamental�Signal�Magnitude
�40 D:�Spurious�Free�Dynamic�Range�=
G:�Second�Harmonic�Magnitude�= �96dB
�96dB
D B:�Headroom�= �0.5dB
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�80
C E:�Average�Noise�Floor�= �125dB
�120
E C.�Signal-to-Noise�Ratio�= �85dB
�60 A F G F:�First�Harmonic�Magnitude�= �105dB
�100 D:�Spurious�Free�Dynamic�Range�= �96dB
�140 G:�Second�Harmonic�Magnitude�= �96dB
�80
C E:�Average�Noise�Floor�= �125dB
�120 A F G F:�First�Harmonic�Magnitude�= �105dB
�160
�100 E
�140 0 10 20 30 40 50 G:�Second�Harmonic�Magnitude�= �96dB
�120 Frequency�(kHz) E
�160
Figure11. (FFT点图)
Dynamic40Specifications (FFT Plot)
�140 0 10 20 30 50
图11. 动态特性
�160 Frequency�(kHz)
0 10 20 30 40 50
Effective Number of BitsFigure (ENOB): 11.ENOB
Dynamicis a critical performance
Specifications (FFTlimit with digital oscilloscope/waveform
Plot)
Frequency�(kHz)
recorders,
有效比特数as well as with image
(ENOB):ENOB 是个关键的性能参数processing, radar, sonar, spectrum
，尤其在数字振荡 analysis, and
/波形记录仪中 telecommunications ，
，同样还应用在图像处理
applications. This critical specification often describes the dynamic performance of the A/D converter. See
雷达，声纳
Effective ，光谱分析和电信领域中
Number of BitsFigure
(ENOB): 11.ENOB
。Dynamic is a Specifications
这个关键参数通常描述的是 (FFT
critical performance A/D Plot)
转换器的动态范围
limit 。同样参考动态特
with digital oscilloscope/waveform
also Dynamic Specifications.
性recorders,
。 as well as with image processing, radar, sonar, spectrum analysis, and telecommunications
•Effective
Effective
applications. Number
This critical
Number of Bits
of Bits vs SINAD—
specification
(ENOB): often is
ENOB describes
a critical the dynamic performance
performance of the
limit with digital A/D converter. See
oscilloscope/waveform
also
TheDynamic
recorders,units
• 有效比特数与SINAD—as Specifications.
of measure
well as with for signal-to-noise-ratio
image processing, plus
radar, distortion
sonar, (SINAD)
spectrum are
analysis,dB and
and the units of measure
telecommunications
• for ENOBsThis
applications.
Effective are critical
Number bits.of
SINAD is converted
specification
Bits vs SINAD—often into ENOBthe
describes through this performance
dynamic calculation: of the A/D converter. See
衡量信噪比加上失真
alsoThe
Dynamic (SINAD)大小的单位是dB，衡量ENOBs的单位是比特bits。SINAD转换为ENOB的公
ENOB�= units ofSpecifications.
(SINAD � measure
1.76) for signal-to-noise-ratio plus distortion (SINAD) are dB and the units of measure
• for
式如下所示Effective
ENOBs ： Number
6.02are bits.of Bits vs
SINAD SINAD— into ENOB through this calculation:
is converted
• Effective
The (SINAD Number
units of� measure
1.76) of Bits vs SNR of Delta-Sigma
for signal-to-noise-ratio Converters—
plus distortion (SINAD) are dB and the units of measure
ENOB�=
for ENOBs are bits. SINAD is converted into
This value defines the usable resolution of the delta-sigma
6.02 ENOB throughA/D
thisconverter
calculation:
in bits. ENOB is determined
by
•ENOB�= applying
Effective a
(SINADNumber fixed, known dc voltage to the analog
� 1.76) of Bits vs SNR of Delta-Sigma Converters— input and computing the standard deviation from
有效比特数与 Delta-Sigma
several conversions.
6.02 转换器的信噪比
Calculate ENOB usingSNR— data taken from the device. ENOB is equivalent to:
This value defines the usable resolution of the delta-sigma A/D converter in bits. ENOB is determined
• Effective
ENOB�=by applying Number
n � log
这个数值定义了 2a
(�fixed, of Bits vs
known
) delta-sigma SNR
dcA/D of to
voltage Delta-Sigma
转换器的可用有效比特 the analog inputConverters—
and computing
。ENOB 的大小由一个固定大小 the standard deviation
，已知的模拟直 from
several
This conversions.
value defines the Calculate
usable
流电压输入量，再通过几次变换计算出标准偏差得到。从器件上读出的参数可以计算出ENOB，其计算公式 ENOB
resolution using
of data
the taken
delta-sigma from
A/Dthe device.
converter ENOB
in bits. is equivalent
ENOB is to:
determined
where:
by applying
ENOB�= log2a(�fixed, known dc voltage to the analog input and computing the standard deviation from
等于•： σn=�standard )
deviation of dataENOB using data taken from the device. ENOB is equivalent to:
several conversions. Calculate
• n = number of converter bits
where:
ENOB�= n � log2(�)
• σ = standard deviation of data
where:
其中： • σ = standard deviation of data
• σ • =n数据的标准偏差
= number of converter bits
• n= 转换器的比特位数
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Glossary of Terms
Glossary of Terms
If . bits (the industry standard, with a crest factor = .) is subtracted from bits-rms, the resulting units
are 如果
peak-to-peak
2.72比特标准 bits.（
Noise
工业标准 volts， peak-to-peak
振幅因子等于(V PP) in
3.3） a signal is equal to (Noise
是由比特均方根简化而来 volts rms * * CF). The
，所得结果的单位是峰峰值
Noise bits peak-to-peak is equal to (Noise in bits
比特数。信号的噪声电压峰峰值(VPP)等于噪声电压均方根*2*CF。噪声峰峰值比特数等于噪声的比特均方根 rms – BCF [see Table ]). From the selected CF (crest
factor), the probability of an occurrence that exceeds defined peak-to-peak limits is predicted.
值– BCF[见表6].从所选的CF（振幅因子）就可以得出超过峰峰值限制的可能性概率。表6总结了振幅因子，
Table summarizes the relationship between crest factor, subtracted bits from RMS bits, and the
简化的均方根比特数和超出峰值限制的噪声百分数三者的关系
percentage of noise events outside the peak defined. 。
Table表6.6.Relationship Between Crest Factor, Digital

振幅因子，数字振幅因子和发生概率的关系
Crest Factor, and Probability of Occurrence
Crest Factor Crest Factor in Bits Percentage of
(CF) (BCF, bits) Occurrences (1)
. –. %
. –. 0.%
(Industry-standard;
accepted values)
. –. 0.0%
. –. 0.00%
. –. 0.000%
(1)
() 超过峰峰值限制的事件概率
Percentage of occurrences where peaks are exceeded
Effective Resolution: Effective resolution describes the useful bits from an A-D conversion as they relate
有效分辨率：在衡量输入信号噪声的时候
to the input signal noise, and is equivalent， to有效分辨率描述了
the effective numberA/Dof转换器的有效比特数，等于有效比特数
bits (ENOB). Volts or bits are the
units of measure
(ENOB)。 for this specification.
它们的单位是伏特或比特 This measurement can be confused with the actual
。通常这和产品数据资料表上写的实际分辨率不同 resolution that
。实际分辨率只是转换
is commonly stated in product
器输出器件的可用比特位数 data sheet titles. The actual resolution
，而不考虑这些比特位是否有无噪声 is simply the number of converter
。有两个不同的单位可以用来表示有效分辨
bits that are available at the output of the device, without clarifying whether or not these bits are
率，其中比特数均方根是用来表示输出数据的
noise-free. Effective resolution is expressed using。在直流输入信号的情况下 The specification70.1%
，有效分辨率描述了达到
two different units of measure. of bits的
rms refers to output
转换重复率的概率 data. This specification predicts
。与比特数均方根不同的是，电压均方根 the probability
(VRMS或Vof a conversion level of repeatability of
rms)是用来表示输入电压的。请参考有效
0.%
比特数。 for a dc input signal. Volts rms (V RMS or Vrms) refers to the input voltage. Also see Effective
Number of Bits.
有效分辨率带宽：在信噪比SNR降到输入满量程幅值的3dB的这个点上，转换器所能接受的最高输入频率就
Effective Resolution Bandwidth: The effective resolution bandwidth is the highest input frequency where
the SNR is dropped
是有效分辨率带宽。 by dB for a full-scale input amplitude.
Fall Time: The time required
下降沿时间：一个信号从 for a signal10%
90%幅值下降到 to fall from 0% of the
幅值所需的时间。 transition range to 0% of that range.
Fourth Harmonic
四次谐波 (HD4): The fourth
(HD4)：指的是基频波的 harmonic is
4倍频率的信号。four times the frequency of the fundamental.
Full-power(FPBW):
满量程带宽 Bandwidth (FPBW): The
在这个频率点上 frequency
，A/D where the reconstructed output of the A/D converter
转换器重构后的输出信号幅值比输入信号的满量程幅值小 3dB。is 其
dB below the full-scale value of a full-scale input signal.
它的动态或交流参数包括：信噪比（SNR）, 信噪比加上失真(SINAD或者SNR+D)，有效比特数(ENOB),总的 Other dynamic or ac specifications include the
Signal-to-Noise Ratio (SNR), Signal-to-Noise Ratio plus Distortion (SINAD or SNR+D), Effective Number
谐波失真 (THD),无杂波动态范围
Of Bits (ENOB), Total Harmonic(SFDR) 和互调失真
Distortion (THD),(IMD)。
Spurious见动态参数
Free Dynamic
。 Range (SFDR), and
Intermodulation Distortion (IMD); see also
满量程范围(FS or FSR): 见模拟输入, 电压范围, 满量程范围 (FS or FSR).Dynamic Specifications.
Full-scale (FS or FSR): See Analog Input, Voltage Range, Full-Scale (FS or FSR).
增益:输入值所放大的倍数，这里不考虑偏置误差。
Gain: Gain is a value at which the input values are multiplied with the offset error removed.
增益误差（满量程误差）：理像化的斜率（从零值到满量程范围）与实际所得的斜率（测量的零值到满量程
Gain Error (Full-Scale Error): Gain error is the difference between the ideal slope between zero and
范围）之间的偏差就是增益误差，对于差分输入的A/D转换器，满量程范围也包括负区间的满量程。其中的
full-scale (as well as negative full-scale for differential input A/D converters) and the actual slope between
误差计算不包括偏置误差
the measured zero point 。增益误差是个直流量的参数
and full-scale. Offset errors are，用的是近直流的模拟输入电压来测量。其它的关键
zeroed out for this error calculation. This is a dc
specification, using a near-dc
直流量参数包括偏置误差，DNL,INL和过渡噪声。见图12 analog input voltage for measurements. Other critical dc specifications
include Offset Error, DNL, INL, and transition noise. See Figure .

SBAAA – August 00
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Glossary
Glossary ofof Terms
Terms
111 Full-scale range =

111 Full-scale range =
Actual Difference�between�the�First
110 Actual Difference�between�the�First
110 Transfer and�Last�Code�Transition�Points
101
Transfer
Function and�Last�Code�Transition�Points
Function
Digital 101 Gain Error =
Digital
Output 100 Gain Error =
Output
Code 100
Full-scale�Error � Offset�Error
Code
Full-scale�Error � Offset�Error
011
011
010
Ideal Gain�errors�can�be�corrected
010
Ideal Gain�errors�can�be�corrected
001
Transfer in�software�or�hardware.
001
Transfer
Function in�software�or�hardware.
Function
000
000
Ideal�full-scale�range
Ideal�full-scale�range
Actual�full-scale�range
Actual�full-scale�range
NOTE: Gain error is the difference between the ideal gain curve (solid line) and the actual gain curve (dashed line)
注意NOTE:
with Gain
offset error is the difference
removed.
：增益误差是理想增益曲线
between the ideal gain curve (solid line) and the actual gain curve (dashed line)
（实线）与实际测量增益曲线（虚线）之间的差异值，其中不考虑偏置误差。
with offset removed.
Figure 12. Gain Error
Figure 12.
图12.Gain
增益误差Error
Gain Temperature Drift: Gain temperature drift specifies the change from the gain value at the nominal
Gain Temperature
temperature Drift:atGain
to the value TMINtemperature
to TMAX. It isdrift specifies
computed asthe
theTchange
maximum from the gainofvalue
gain at thethenominal
增益的温度漂移特性：增益的温度漂移特性是用来表征温度从 MIN变化到 Tvariation
MAX期间增益的改变情况 over 。entire
它等于
temperature
temperature to the
range value
divided at T
by (T
MIN to T –
MAXT . It).is computed
The units ofas the
measuremaximum
for this variation of
specification gain
is over
parts the
per entire
million
整个温度变化区间内增益的最大改变量除以 MAX MIN (T – TMINof)。这个参数的单位是每百万分之一每摄氏度 (ppm /
temperature
per degree Crange (ppm divided
/°C). by (TMAX – TMIN). The MAX units measure for this specification is parts per million
℃ per)。degree C (ppm /°C).
Group Delay: Group delay is the rate of change of the total phase shift with respect to angular frequency
Group Delay:
群时延：群时延是总相移的变化量与角速度的比率
or δĭ/δω, where Group delay
ĭ is the is the
total phase rateshift
of change
in radians,of the total
ω isphase
或者表示为δΦ
，and shift/ δω
the angular with respect
，其中Φ是总的相移
frequency to radians
in angular per frequency
单位是
，unit
or δĭ/δω,
time ， (ωω是角速度where ĭ
equal to πf), is the total phase shift
where f is the frequency in radians,
(hertz其中and ω
if group is the
delay angular frequency in
is measured in seconds). radians per
With unit
弧度
time ，单位是弧度每秒
(ω equalconverters,
to πf), where f is thedelay ( ω等于 2pf)，
frequency (hertz f 是频率（如果群时延以秒为单位，则 f 的单位是赫
delta-sigma the group is caused byifthe
group delay
digital is measured in seconds).
filters. With
兹 delta-sigma converters,
）。在delta-sigma 转换器中 the group delay is caused by the digital。
，群时延是由于数字滤波器造成的 filters.
Harmonic Distortion: The ratio of the rms input signal to the rms value of the harmonic in question.
Harmonic Distortion:
谐波失真：输入信号均方根与噪声谐波的均方根值之间的比率就是谐波失真
Typically, the magnitude The ratioinput
of the of the rms input
signal is 0.dBsignal to the
to dB rms full-scale
below value of 。 the harmonic
in一般输入信号的数量级比满量
order in question.
to avoid clipping.
Typically, the
When the input
程最大值小 magnitude
0.5dB signal
到1dB， of
is muchthe input signal is
lower than full-scale,
这是为了避免消顶失真 0.dB to dB below full-scale in order to avoid
other distortion entities may limit the distortion
。当输入信号比满量程最大值小很多的时候，clipping.
其它失真开始
When the input
performance as signal
a resultis of
much
the lower thanDNL.
converter full-scale,
When other distortion
determining the entities
ac may limit
linearity of a the distortion
device, harmonic
称为主导因素
performance ，最后造成信号的微分非线性
as awhen
resultaofsingle
the converter 。要测定一个器件的直流线性度的时候
DNL. When determining thecanac linearity ,就输入一个单频信号衡量
of a with
device, harmonic
distortion is used tone is applied. Harmonic distortion be specified respect to the
distortion
其谐波失真 is。
full-scale inputused when
它的大小用输入信号满量程范围
range a single
(dBFS toneoriswith
or dB), applied. dBFS
respectHarmonic
或todB 表示
the distortion
，或者是输入信号幅值大小
actual input can be specified
signal amplitude with
dBc respect
(dBc).表示。（
(Also tosee
the
见二次
full-scale
second input
harmonic range
- HD,(dBFS or dB), or with respect to the actual input signal amplitude (dBc). (Also see
谐波 -HD2，三次谐波 -HD3third
和四次谐波 harmonic - HD, and fourth harmonic - HD.)
-HD4）
second harmonic - HD, third harmonic - HD, and fourth harmonic - HD.)
2
III2C
2 C Interface See Digital Interface, IC.
接口协议见数字接口 2C.
C Interface See Digital, IInterface, I C.
Ideal Code Width
理想码元宽度 (q):
(q): (q): The ideal full-scale input
The ideal
理想的满量程输入电压范围除以二进制编码的总数 full-scale voltage range divided by the total
。其总数等于： number of code bins.
Ideal Code
The total Width
number of code bins equals: input voltage range divided by the total number of code bins.
The total number of code bins equals:
FS
q�= FS
q�= 2nn
2
Where:
其中，
Where:
• total number of code bins = nn;
• total number
• 所有的编码数 2ofnbits;
; code bins = ;
• n = number= of
• 比特数
n = number of bits;
• n• = FS = Full-Scale
; Range
• FS = Full-Scale Range
•IdealFSA/D
= 满量程范围
Converter Transfer Function: An analog voltage is mapped into n-bit digital values with no
Ideal
offset,A/D
gain,Converter
or linearity Transfer Function:
errors. See . analog voltage is mapped into n-bit digital values with no
Figure An
offset, gain, or linearity errors. See Figure .
Idle Tones: These tones are caused by the interaction between the其中不考虑偏置误差
delta-sigma A/D converter modulator
Idle A/D
Tones: These n个bit的数字信号
Idletones
tonesare caused
fromby the interaction
Onebetween the
理想转换器的传输函数：把模拟电压刻画为， delta-sigma A/D converter
、增益误差 modulator
、线性
and digital filter. come two sources. is inherent in the voltage being measured, such
and digital
as when
度误差。见图 filter.
6. Idle
the modulator tones come from two sources. One is inherent in the voltage being measured, such
output repeats in a pattern that cannot be filtered by the digital filter. This type of
as when the modulator output repeats in a pattern that cannot be filtered by the digital filter. This type of
闲音：闲音噪声是由delta-sigma A/D转换器中的调制器与数字滤波器之间的相互作用引起的。它有两个来
源，其中一个是内在的，来自于被测量的电压，比如调制器的输出重复工作在一种模式，而这种模式恰好
16
A术语词汇表
Glossary of
：Analog-to-Digital
模数转换的规格和性能特点 Specifications and Performance Characteristics SBAAA – August
ZHCA068-August 00 – Revised January
2006-Revised January 00
2008
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Glossary of Terms
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pattern occurs at 0V, one-half the FSR, three-fourths of the FSR, etc. The second source Glossary of Terms
of idle tones is
the chopping frequency being sampled in to the measurement. This sampled frequency produces a digital
是数字滤波器无法滤除的。这种模式会发生在
pattern of codes that oscillate 0V，within
at a slow frequency 一半的满量程 FSR电压
the passband. As 四分之三的满量程
，the FSRtones
name implies, idle 电压，等
can appear as a frequency in the output
等。第二个闲音噪声的来源是测量过程中采样的截止频率。这个采样频率产生的数字编码模式恰好足够低，conversion data with multiple dc input conversions at a constant
data rate. Patented techniques are available to reduce idle tone concerns.
在通带之内。也就是说，闲音可以看作转换器输出的一特定频率，由多个直流输入转换形成一固定的数据信
Input
号 range (FS or FSR): The specified range of the peak-to-peak,
。已有获专利的技术可以用于降低闲音噪声带来的影响。 input signal of an A/D converter.
Integral Nonlinearity (INL, also known as Relative Accuracy Error): An INL error is the maximum
输入范围 (FS or FSR):A/D转换器输入信号峰峰值的大小范围。
deviation of a transition point from the corresponding point of the ideal transfer curve, with the measured
offset and gain
积分非线性 (INL,errors zeroed. This specification
也叫做相对精度误差 can be referenced to a best-fit transfer function or an
):积分非线性是从一个传输点到相对应的理想传输曲线的最大偏差距
end-point transfer function. The best-fit
离，不考虑偏置误差和增益误差。这个参数对最佳传输函数或端点传输函数有一定参考意义 INL results will be one-half the error of the end-point。measurement
在测量同一个
method for the same device. The best-fit transfer function is determined with a least squares curve fit to
器件时候最佳积分非线性误差仅是端点测量法误差的一般
， function. This is a dc specification, where measurements
the transfer 。最佳传输函数可由最小二乘法计算得到
are taken with near-dc analog 。这是
input
voltages. The units，for
一个直流量的参数 INL are LSB. INL is a critical specification
测量的是近直流的模拟输入电压。它的单位为for image
LSB。 processing applications. Other
积分非线性在图像处理应用上是一
critical dc specifications include Offset Error, Gain, TUE, DNL, and transition noise. See Figure .
个非常关键的参数，其它重要的直流参数包括偏置误差，Gain, TUE,DNL和过渡噪声。见图13.
INL =�maximum�deviation
111 Actual between�an actual (dashed line)�code
Transfer INL�<�0 transition�point�and�its�corresponding
Function
110 ideal (solid line)�transition�point,
101
after�gain�and�offset�error�have
Digital been�removed.
Output 100
Code
011
Positive INL�means
Ideal transition(s)�later�than�ideal
010 Transfer
Function
001
Negative INL�means
000 transition(s)�earlier�than�ideal
INL�<�0
Figure 13. Integral Nonlinearity Error

图13. 积分非线性误差
Intermodulation
互调失真 Distortion (IMD): The A/D converter ，A/D
(IMD):当两个正弦信号同时加在输入端的时候 can create additional spectral components
转换器会产生新的频谱噪声。互调失真等于互 as a
result of the input of two sinusoidal frequencies
调分量的功率与原信号的总功率的比值。它的单位是 dBc( 当用的是绝对功率做参考的时候 )，或者是 simultaneously applied at the input. IMD is the ratio ofdBFS
power of the intermodulation products to the total power of the original frequencies. IMD is either given in
（当用满量程范围做参考的时候
units of dBc (when the absolute ）。 power of the fundamental isIMD3，
两个频率的互调失真或 used as是基波（频率在f1or
the reference) f2）的功率与影响最
或dBFS (when the
power of the fundamental is extrapolated to the converter
大的频谱成分（频率在2f1 – f2或2f2 – f1）的功率的比值。IMD3的单位是dBc（载波的单位是dB），这是在用 full-scale range).
Two-tone intermodulation distortion,
基波的绝对功率做参考的时候 or IMD, is the ratio of the ，
，如果用基波的满量程范围做参考 power
单位就是 of the fundamental
dBFS (满量程范围的单位是(at frequencies
dB)。
f and f) to the power of the worst spectral component at either frequency (f – f or f – f). IMD is
IMD 是一个关键的参数，被应用在雷达、声纳、扩频通信、电信和宽带数字接收器等领域。其它的动态或直
given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference,
or in units of dBFS（SNR）,
流参数包括信噪比 (dB to full-scale)
信噪比加上失真 when the power或者
(SINAD of the fundamental
SNR+D)，有效比特数 in extrapolated to the converter
(ENOB),总的谐波失真 (THD),
full-scale range.(SFDR)和全功率带宽(FPBW) 。
无杂波动态范围
IMD is a critical specification
内部缓冲器：如果 for radar, sonar, spread spectrum
A/D转换器有一个输入缓冲器作为它的输入 communication, telecommunication,
，它的输入阻抗就可以变得很高，这就可以隔 and
wideband digital receiver applications. Other dynamic or ac specifications include the Signal-to-Noise
绝转换器外部输入信号造成的采样效应的影响
Ratio (SNR), Signal-to-Noise Ratio plus Distortion ，同时提高输入阻抗。
(SINAD or SNR+D), Effective Number Of Bits (ENOB),
Total Harmonic
抖动: 见孔径抖动和时钟频率抖动. Distortion (THD), Spurious Free Dynamic Range (SFDR), and Full-power Bandwidth
(FPBW).
大信号：大信号是指一个信号的幅度峰峰值占到A/D转换器模拟信号满量程范围的90%以上。
Internal Buffer: If the A/D converter has an input buffer at its input, this provides a high impedance input
that isolates the external input signal from the sampling effects of the converter and provides a higher
input impedance.
Jitter: see Aperture Jitter and Clock Jitter.
Large Signal: A large signal is where the peak-to-peak amplitude of a signal spans at least 0% of the
full-scale analog range of an A/D converter.
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Glossary
Glossaryofof
Terms
Terms
Latency:
时延：Cycle latency: For A/D converters, cycle-latency is equal to the number of complete data cycles
between the initiation of the input-signal conversion and the initiation of the next signal conversion. The
周期时延：对于
unit A/D
of measure for 转换器
this ，周期时延等于输入信号转换的起始点到下一个信号转换的起始点之间的完
definition of latency is (n)-cycle latency, where n is a whole number. Figure
illustrates
整数据周期数 the cycle-latency
。它的单位是behavior (n)周期，of 其中two different
n是整数。图 A/D converters. Figure A shows。a图
14画出了两种不同时延的示意图 timing
14A画的是一
diagram for a zero-cycle latency A/D
个A/D转换器的零时延时间示意图； 14B
图 converter;
画的是 Figure
A/D B
转换器的 shows
4 a timing
周期时延时间示意图 diagram。for a four-cycle
一个拥有零时延的
latency A/D converter. An A/D converter with zero-cycle latency can also be described as having
A/D 转换器可以看成具有单周期完成或者单周期转换数据的能力
single-cycle settling or single-cycle conversion.
A. Zero-cycle�Latency
Single-Cycle
Conversion
N+2
N+1 N+3
N+0
Analog�IN N+4
Zero-cycle�latency N+5
N+6
N+7
Data�OUT N�5 N+0 N+1 N+2 N+3 N+4 N+5 N+6 N+7
Data
Invalid
B. Four-cycle�Latency
N+2
N+1 N+3
N+0
Analog�IN N+4
N+5
N+6
N+7
Four-cycle�latency
Data�OUT N�5 N�4 N�3 N�2 N�1 N+0 N+1 N+2 N+3
Data
Invalid
NOTE:
注意 With zero-cycle(A),
：对于零周期时延 latency
采样周期是从 N+0个周期开始
(A), the sampling period， N+0 isN+0
of并且第 initiated. N+1
The output data
个数据的输出是在第 of N+0 are acquired
个采样周期开始
before
之前。在 4周期时延中
the (B), 采样周期是从
sampling period N+0个周期开始
of N+ is initiated. ，而第N+0
With four-cycle latency
个数据的输出是在 4个周期之后
(B), the sampling period of。
N+0 is initiated. The
output data of N+0 are acquired after four cycles.
图14.
Figure 14. Input/Output A/D转换器的输入输出特性
Characteristics of an A/D Converter with
(A) Zero-Cycle(A)
Latency
零周期时延and与(B)
(B)Four-Cycle
4周期时延 Latency
时延时间：时延时间是指转换一个理想的阶跃输入信号
Latency-time: Latency-time is the time required for an ideal ，加上误差，到输出最后数字信号所需的时间
step-input to converge, within an error 。
margin, to a final digital output value. This error-band is expressed
这个误差带可以看成事先定义的输出电压总阶数的一个百分比 as a pre-defined percentage of the
。转换时延是从输入信号的获得开始算
total
起，output voltage step. The latency-time
到下一个信号转换的开始为止， of a
中间的这段时间就是转换时延conversion is that period between the ，
。与周期时延相比 time where （
转换时延 the
或稳
signal acquisition begins to the time the next conversion starts. In contrast to the cycle-latency
定时间）从不会等于零
specification, 。
the latency-time (or settling-time) is never equal to zero.
延迟时间，Delta-Sigma
Latency-Time, Delta-Sigma Converter:delta-sigma
转换器：对于 A/D转换器
For delta-sigma A/D converters,
，延迟时间更难确定 latency is ，因为delta-sigma
harder to define A/D
because delta-sigma A/D converters do，not
转换器并不是在某一时刻输入一个信号 output a code corresponding
它就相应地输出一个编码 to a single point in time. The
。ΔΣ转换器的输出编码是一段时间内对
code that ǻȈ converters output is the result of filtering or averaging the input during an interval of time; the
输入信号的滤波和平均，这段时间就等于转换器的采样时间。因此，我们测量一个delta-sigma A/D转换器的
interval is equal to the sample period. For this reason, we measure latency for a delta-sigma A/D
converter
延迟时间的时候 by starting at the beginning of a sample period,
，起始时间从采样周期的初始点开始 and measuring to the time that 。
，终止时间就是到获得数据的那一刻 data can be
实际上也可以把
retrieved.
接收数据所需的时间也算进延迟时间中去，因为delta-sigma A/D转换器总是有几个串行接口。data,
It may also be practical to include in the latency time the time needed to retrieve the 对于音频转since
delta-sigma A/D converters nearly always have serial interfaces. For audio converters, this additional
换器，这种额外的延迟时间影响非常大
latency can be very significant, even up，to甚至是采样时间的好几十倍。对于采样
several tens of sample periods. sinc滤波器的低速工业转换
For low-speed industrial
converters with sinc filters, it sometimes
器，延迟时间通常只有几个调制周期。对于 amounts to onlyA/D
delta-sigma a few
转换器 modulator cycles. For delta-sigma A/D
，所使用的滤波器总是带有群时延，所以
converters, filters with constant group delay
就没必要刻意区分群时延和延迟时间了。delta-sigma A/D转换器的延迟时间也常叫做稳定时间。 are almost always used, so there is no difference between
group delay and latency. The latency-time of a delta-sigma converter is often called Settling time.
A术语词汇表
Glossary of Analog-to-Digital Specifications and Performance Characteristics SBAAA – August 00 – Revised January 00
18 ：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008
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Glossary of Terms
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Latency-Time, SAR Converter: For SAR A/D converters, latency is typically very short;Glossary
it is the amount
of Terms
of time needed for the successive approximation process to complete. Data is typically available
immediately afterward.
延迟时间，逐次逼近 SARThis
滤波器 approach is typically equal
:对于一个逐次逼近 to the ，
SAR滤波器 conversion
延迟通常都很短 time, and exclusive of the
；所需的时间是整个连续逼
sample time. For SARs, which generally have an external continuous-time analog filter at the front-end,
近模拟信号的过程
group delay can be，a转换后的数据通常可以马上使用
more useful measurement, since 。这个过程基本上就等于转换所需的时间
the latency may be frequency-dependent.，其中不包括
采样时间。对于SAR转换器，通常都在前端外接一个连续时间的模拟滤波器，这种情况下可以用群时延更好
Latency-Time, Pipeline Converter: The number of complete clock cycles between the initiation of a
conversion and ，
地评估延时特性 when the data appears on the output driver
因为这里的延迟时间一般是频率相关的。 stage.
Least Significant Bit (LSB): The least significant bit is the bit representation
延迟时间，流失线转换器：从转换开始到数据输出中间的完整时钟周期数。 of the smallest analog input
signal that is converted, and is synonymous with the code bin width. The least significant bit defines the
最低有效位(LSB): 最低有效位代表了能够转换的最小模拟输入信号所对应的比特位，它和二进制码元宽度是
resolution of the converter. It is also referred to the furthest right bit in a binary digital word.
同一个意思。最低有效位同样也表示转换器能达到的最大精度，它也指数字二进制的右边最末位。
Major Carry Transition: The mid-scale point where the MSB changes from low to high and all other bits
change from
主进位转换：high to low, or where the
发生在量程范围的中点 MSB changes from high
，也就是当最高有效位 MSBto low and all other bits change from
从低变到高同时其它位从高变到低 low to
，或者最
high. These transition points are often where
高有效位MSB从高变到低同时其它位从低变到高的时候。在这些转换点的位置上，也是转换噪声最大的位 the worst switching noise occurs. (See also Most Significant
Bit or MSB.)
置。（见最高有效位或MSB）
Missing Code: A missing code is when a legitimate A/D converter output code that should exist is not
码元丢失：当 A/D转换器在理想情况下输出的合法码元不可用时
available. An increase ，就造成了码元丢失
in the analog voltage can produce an unexpected 。模拟电压的增大会导
smaller or the same digital output
code. See Figure .
致输出数字信号的不可预测，可能变小或者保持不变。见图17.
Modulator: At the input of a first-order
调制器：位于一阶调制器的输入端 modulator, the signal comes
，信号先通过一个加法放大器（见图 in 15）。
through信号接着进入一个积分器后输
a summing amplifier (see
Figure ). The signal then passes through an integrator that feeds a comparator. The comparator acts
入一个比较器，这里比较器就像一个
like a one-bit quantizer. The output of1比特的数字编码器。从比较器输出后分成两路
the comparator feeds forward to a digital filter ，一路输入一个数字滤
and back to a one-bit
Digital-to-Analog
波器，另一路返回到一个 (D/A) Converter.
1比特的数模 The(D/A)
signal
转换器at the，inverted
经过D/Aoutput of the D/A converter
转换器的反相输入端 is summed into
，最后返回输入端的加法
the。input
器 summer. The output of a0modulator
调制器的输出为一系列的数字 provides a stream of，
和1。这些输出经过时间平均后 digital ones and zeros. The time 。调制
与模拟信号的输入电压值成正比
average of this serial output is proportional to the analog input voltage. The order of the modulator is
器的阶数等于积分器和反馈环路的数目
equivalent to the number of integrators。and feedback loops.
Summing Comparator
Amplifier Integrator (1-bit�ADC)
Analog
Input
Digital
Filter
1-bit�DAC
NOTE:
注意 For the entire
: 要查看完整的 delta-sigma
delta-sigma ADC block
模数转换器 ADCdiagram,
模块图, refer
请参考图to Figure
9. .
Figure 15. First-Order Modulator Segment

图15. 一阶调制器模块图 (Delta-Sigma
(Delta-Sigma A/D转换器) A/D Converter)
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Glossary ofofTerms
Glossary Terms
Glossary of Terms
Modulator, continued:
Modulator, continued:
调制器，续：
Figure illustrates a second-order modulator. It is not uncommon to have a third-, fourth-, fifth- or
Figure
图16 illustrates
modulatora inside
画的是二阶调制器
sixth-order second-order modulator.
delta-sigma
。a在delta-sigma A/D It is not uncommon
A/Dconverter.
模数转换器内 to have
使用三阶
The，number of、 a third-,
四阶
output 、 fourth-,
五阶甚至六阶的调制器也
bits can alsofifth- or
be higher
sixth-order
than
不是罕见的事one. Amodulator
modulator
。 inside
can a
be
输出端的比特数也可以不只一个 delta-sigma
included in aA/D converter.
delta-sigma
。 The
A/D
调制器可以被集成在一个 number
converter of output
chip or it bits
can
delta-sigma A/Dcan
be a also be higher
stand-alone
模数转换器芯片
than one. A modulator
component. can beof
The combination included in a delta-sigma
a modulator A/D converter
and a processor chip or
(programmed to itimplement
can be a stand-alone
a digital filter)
内，也可以是一个独立的元件
component. The combination 。of 调制器和处理器
a modulator and（ a可以编程实现数字滤波器的功能
processor (programmed to ）能够共同组合成一个高
implement a digital filter)
results in a high-resolution A/D converter system.
resultsA/D
精度的 in a模数转换系统
high-resolution
。 A/D converter system.
Integrator Integrator 1-bit�ADC
Analog Integrator Integrator 1-bit�ADC Digital
IN
Analog OUT
Digital
IN OUT
� �
xi � � yi
xi yi
ei
ei
1-bit�DAC
1-bit�DAC
NOTE: For the entire delta-sigma ADC block diagram, refer to Figure .
NOTE:
注意 For the entire
: 要查看完整的 delta-sigma
delta-sigma ADC block
模数转换器 ADCdiagram,
模块图, refer
请参考图 to Figure
9. .
Figure 16. Second-Order Modulator Segment (Delta-Sigma A/D Converter)
Figure 16. Second-Order Modulator Segment
图 16. 二阶调制器模块图 (Delta-Sigma A/D Converter)
(Delta-Sigma A/D转换器)
Monotonic: This term implies that an increase (or decrease) in the analog voltage input will always
Monotonic: This term
produce no change implies
or an
单调性：这个特性说明的是输入模拟电压的增大 that an
increase (or increase (or
decrease) decrease)
（in或降低
the digital in the analog
code. voltagedoes
Monotonicity
）总会带来数字信号的不变或增加 inputnot
will（always
imply
或减少there
）。 are
单
produce
no no codes.
missing changeMonotonicity
or an increase
is a(or decrease)
critical in the digital
specification with code. Monotonicity
automatic control does not imply
applications. See there are
调性并不意味着没有码元丢失的现象。它在自动控制领域中是个关键的参数。见图17.
no missing
Figure . codes. Monotonicity is a critical specification with automatic control applications. See
Figure .
111
Non-monotonic�as�well�as
111
a�missing�code
If�the�output�code
Non-monotonic�as�well�as
110
a�missing�code
If�the�output�code
always�increases�when
110
101
always�increases�when
the�input�increases,�the
Digital 101 the�input�increases,�the
device�is monotonic.
Output
Digital 100 device�is monotonic.
Code
Output 100
Code 011
011
010
010
001
001
000
000
0 1/4�FS 1/2�FS 3/4�FS FS
0 1/4�FS 1/2�FSVoltage
Analog Input 3/4�FS FS
NOTE:
注意 In this graph,
:在这张图中 FS means Full-Scale.
，FS的意思是满量程 .
NOTE: In this graph, FS means Full-Scale.
Figure 17. Non-monotonic Transfer Function
图 17. 非单调传输函数
Figure 17. Non-monotonic Transfer Function
Most Significant Bit (MSB): The most significant bit is often considered as the furthest left bit in a binary
Most Significant
digital word.(MSB): Bit
The most (MSB): Thebit
significant most
cansignificant
最高有效位一般被认为是二进制数字的最左边一位 bit is
serve as the often
sign bit considered
in bipolar as the furthest
converters. left
For，more bitinformation
in a binary
最高有效位。在双极转换器中最高有效位可以当
digital the
about word. The most
definition significant
of the bit can
MSB, refer serve as
to Bipolar the sign
Offset bit Code
Binary in bipolar converters.
(BOB), For moreOffset
Complementary information
Binary
作符号位
about the。
Code (COB), 关于最高有效位
definition
Complementary MSB
of the MSB, 的更多定义请参考双极偏移二元码
refer
Straight toBinary
Bipolar Offset
Code Binary
(CSB), Code（BOB），偏移二进制补码
(BOB), Complementary
’Complementary Twos Complement (COB),
Offset 标准
Binary
(CTC)
Code (COB),
Code, or Unipolar
二进制补码 Complementary
(CSB),补码 Straight
(CTC)， Straight
Binary Binary Code
Code (USB). (USB).
或单级直接二进制码 (CSB), ’Complementary Twos Complement (CTC)
Code, or Unipolar Straight Binary Code (USB).
Multiplexer(MUX):
多路复用器 (MUX):多路复用器从多个输入中选择一个信号作为输出信号
A multiplexer selects one of several input signals into a single output signal.
。在带有多路复用器的 A/DAt the
转换器输
Multiplexer
input of an A/D(MUX): A multiplexer
converter with a selects oneone
multiplexer, of several
signal input signals
(which can be into
a a single output
single-ended or signal. At input)
differential the
入端
input，of多个信号通道中选择一个
an A/D with a（这里可以是一个单端信号或者是差分输入信号）作为输入信号。 input)
is selected fromconverter
several inputs. multiplexer, one signal (which can be a single-ended or differential
is selected from several inputs.
0
20 A术语词汇表
Glossary of
：Analog-to-Digital Specifications and Performance Characteristics SBAAA – August 00 – Revised January 00
模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008
0 A Glossary of Analog-to-Digital Specifications and Performance Characteristics SBAAA – August 00
Submit – Revised January
Documentation 00
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Feedback
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Glossary of Terms
Glossary of Terms
无误码：这个特性说明的是输入模拟电压的增大（或降低
No Missing Codes: This term implies that an increase ）总会带来转换输出的数字信号的增加
(or decrease) in the analog voltage input will（或减
always
少 produce an increase (or decrease) in 。
）。单调性并不意味着没有码元丢失的现象 digital output converter code. A converter with
一个拥有无误码的转换器具有单调性的特点。no见图 missing
17.
codes is also monotonic to specified bits. See Figure .
噪声，A/D转换器：只要不是一个直流无噪声的模拟输入，它的输出都会有噪声存在。通常的噪声包括随机
Noise, A-D Converter: Any deviation between the output digital code with a dc, noise-free, input analog
噪声，非线性噪声，如谐波失真和孔径不稳定。
signal. Examples of noise include random noise, nonlinearities such as harmonic distortion, and aperture
•uncertainty.
随机噪声–
• Random Noise–
A/D转换器输出信号的随机起伏。
A random fluctuation in the output code of an A/D converter.
• 不确定性噪声–
• Uncertainty Noise–
转换点通常不是一个确定的阈值电压，而是一段不确定的电压范围。一个给定编码的转换点会重复
The transition point is typically not a single threshold, but rather a small region of uncertainty. The
region of uncertainty is defined with，repetitive
出现在这一段不确定的电压范围内 code transitions on a given code.
把这些重复出现的转换点进行统计平均 The transition point。
，就得到最终的转换点 is这
the statistical average of these repetitive transitions.
是一个直流量的参数，其它的直流量参数包括偏置误差、增益误差、INL、未调整的总误差(TUE)。见图 This is a dc specification. Other dc specifications
include Offset Error, Gain, DNL, INL, and TUE. See Figure . (Also see Code Transition Point. )
18。（同样参考码元转换点）
Code
111
under�test
110
100%
101 0%
Digital Output
50% Center�of�code�width
Transition�Point
100
011
Low�side�transition
010
001
Transition�point;�uncertainty�noise
000
0 1/2�FS FS
Analog Input
NOTE:
注意：这个This3比特的
non-ideal
A/Dtransfer function of a -bit A/D converter illustrates the
转换器的非理想传输函数画出了每个编码的传输噪声。图中transition noise of every code.
，FS代表满量程范围。 In this
graph, FS means Full-Scale.
图18.非理想传输函数(3-bit A/D转换器)
Figure 18. Non-Ideal Transfer Function (3-bit A/D Converter)
Noise Power (NPR):

噪声功率比： Ratio (NPR): The dynamic performance
要测量一个带宽带输入的 A/D转换器的动态参数of an A/D converter with a broad bandwidth
，可以测量它的噪声功率比 input 在
(NPR)。
can be characterized by measuring the noise power ratio (NPR). In A/D converter applications where the
A/D 转换器的使用中当输入的信号包含大量互不相干的频率或窄带信号时，通常要求微弱信号的探测不能
input signal contains，a large number of incoherent tones or narrow bandwidth signals, it is generally
desired（that
被失真 distortion (resulting from combinations
这里的失真由多个强信号引起）所干扰。对于 of strong signal components)
A/D转换器的采样部分 should notNPR
，噪声功率比 interfere
等于范围外 with
detection of weaker signal components.
的功率谱密度除以范围内的功率谱密度 For an
。NPR A/D converter sample set, NPR
在宽光谱通信中这是个关键参数 is the ratio of the average
，所以在宽带信号应用中非常
out-of notch to the average in-notch power spectral density magnitudes. This parameter is a critical
需要 NPR接近理想水平的
specification A/D转换器
in spread spectrum 。
communication applications. A/D converters having measured noise
power ratios that closely match theoretical NPR, for an ideal N-bit device, are desirable candidates for
broadband (NMR):
串模抑制比串模抑制比是衡量抑制共模信号（直流或交流）串扰差分输入信号的能力。它等于不断
signal applications.
变化的共模输入信号与数字输出信号的比值
Normal-mode Rejection (NMR): Normal-mode 。NMR 和CMR的定义是一样的
rejection is the degree of ，请参考共模抑制比
rejection 。
of a common-mode
signal (dc or ac) across the differential input stage. This specification is the ratio of the changing input
common-mode signal to the resulting digital output. NMR is the same as CMR; also see Common-Mode
Rejection.

SBAAA – August 00
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转换比特位数(n)：转换比特位数(n)是指数字输出字长的比特的位数。A/D转换器输出的这些n位比特数可以
Glossary of Terms Converter Bits (n): The number of converter bits (n) represents the number of bits in the
Number
组成2的nof 次方种可能的编码。
output digital
Number word. TheBits
of Converter number of output
(n): The numbercodes that an A/D
of converter bitsconverter produces
(n) represents is n possible
the number of bitscodes.
in the
奈奎斯特定理：当用离散时间间隔对信号进行采样时候
output digital word. The number of output codes that an，这个定理在理论上要求采样速率必须大于两倍的输
A/D converter produces is n
possible codes.
Nyquist Theorem: When sampling a signal at discrete intervals, this theorem postulates that theoretically,
入信号带宽
the sampling 奈奎斯特频率是采样频率的一半
。speed must be greaterathan twice 当信号带宽比采样频率的一半更低的时候
。the bandwidth of the ，理论上原始信号
Nyquist Theorem: When sampling signal at discrete intervals, thisinput
theoremsignal being sampled.
postulates The
that theoretically,
Nyquist
the frequency
sampling
可以被重新还原出来 speedismust
half of
。 bethe sample
greater thanrate. When
twice the the signal bandwidth
bandwidth of the inputissignal
less than half
being of the sample
sampled. The
rate,
Nyquistthefrequency
original signal
is halfcan
of theoretically
the sample be reconstructed.
rate. When the signal bandwidth is less than half of the sample
偏置误差：A/D转换器的理想第一个代码转换点和实际代码转换点之间的电压差值，就是偏置误差。这是一
rate,
Offset the original
Error: signal
Offset canistheoretically
error the difference beinreconstructed.
voltage between the ideal first code transition and the actual
个直流量的参数，测量的是近直流的模拟输入电压，其它的直流量参数包括增益误差、DNL、INL、转换噪
code
Offset Error: Offset error is the differenceis in
transition of an A/D converter. This dc specification,
a voltage between where measurements
the ideal are taken
first code transition andwith
the actual
near-dc
code transition of an A/D converter. This is a dc specification, where measurements are takenNoise.
声。 analog input voltages. Other dc specifications include Gain, DNL, INL, and Transition with
near-dc
Offset analogUnipolar:
Error,
偏置误差，单极：在一个单极器件中 input voltages. Other，
In a unipolar dc specifications
device, include
offset error
偏置误差是第一个测量得到的转换点 is theGain, DNL, between
difference INL, and the
Transition
（也是一个最小的电压 Noise.
first measured）与第一
transition
Offset point (lowest
Error, Unipolar: In
个理想转换点之间的偏差 in voltage)
。a见图 and
unipolar the first ideal, transition point.
device, offset error is the difference
19。单极偏置误差的计算公式如下所示 (See
： between the first measured Error
Figure .) Unipolar Offset
is measured
transition pointand calculated
(lowest as shown
in voltage) and in
thethe following
first equation:point. (See Figure .) Unipolar Offset Error
ideal, transition
is measured (V[0:1]
Offset�Error�= and calculated
� (0.5)VILSBas) shown in the following equation:
Offset�Error�=
其中： (V[0:1] (0.5)V ILSB)
Where:
�
n
••
Where: VILSB
V =V
ILSB = VREF
REF /
2n ==理想的
ideal LSB LSB 所对应的电压值
voltage size; ;
•• V[0:]
V[0:1]
V =
ILSB = = analog nvoltage of first transition;
第一个转换点的模拟电压值
VREF / = ideal LSB voltage size; ;
•• V
V[0:]
VREF ==full-scale
= analog
满量程的电压值 voltage;of; first transition;
voltage
REF
n REF
= number of converter
voltage; bits
•• V
n= = full-scale
转换器的比特数
111
Offset Error =�Difference
Ideal
111
110 Transfer between�the�actual�(
Offset Error =�Differencedashed line)
Ideal
Function first�transition�point�and�the
110 Transfer between�the�actual�(dashed line)
101
Digital Function ideal�( solid line)�first�transition�point.
first�transition�point�and�the
101 First�(Ideal)
Output
Digital
100
Code
Actual ideal�(solid line)�first�transition�point.
Code Transfer
Output 100 First�(Ideal)
Transition
011 Actual
Function
Code Code
Transfer
Transition
011
010
Function Offset�errors�can�be
corrected�in�software�or
Offset�errors�can�be
010
001 hardware.
Offset�Error
corrected�in�software�or
001 hardware.
000
Offset�Error
000
0 1/4�FS 1/2�FS 3/4�FS FS
0 Analog Input
1/4�FS 1/2�FSVoltage
3/4�FS FS
NOTE: In this graph, FS means Full-Scale.
NOTE: In this graph,

注意:在这张图中 FS means Full-Scale.
，FS的意思是满量程 . Figure 19. Unipolar Offset Error
Figure 19.图19. Unipolar
单极偏置误差 Offset Error
Offset Error, Bipolar: For a bipolar device, offset error is the deviation of output code from mid-code or
mid-scale (or zero)
偏置误差，双极：对于一个双极器件
Offset Error, when
Bipolar: Forboth inputs，
a bipolar are tiedoffset
device, to a common-mode
当两个输入的信号都依赖一个共模电压时 voltage.
error is the deviation 偏离代码中部或量程中点
of output，code from mid-code or
mid-scale
（或者是零
Offset (or
Error, zero) when
）的数值就是偏置误差 both
Temperature Drift: 。 inputs are tied to a common-mode voltage.
Temperature drift specifies the change from the offset value at the
nominal
Offset temperature
Error, to the value
Temperature Drift: at TMIN to 时
Temperature T drift. It isspecifies
computedtheas the maximum
change from thevariation
offset of offset
value at theover
偏置误差，温度漂移：从温度 TMIN 变到 TMAX MAX ，偏置数值的变化量就是温度漂移值，它等于整个温度区间范
the entiretemperature
nominal temperaturetorange divided
the value at Tby
MIN
(Tto T
MAX –
MAX
T. It
MINis). The units
computed of
as measure
the for
maximum this specification
variation of areover
offset parts
围内偏置量的最大变化量除以
per
the milliontemperature
entire per degree Celsius (T(ppm/°C)
MAX – Tby
range divided MIN)。
orMAX
(T
单位是百万分之一每摄氏度
microvolts
– TMIN).per Thedegree (ppm/
units ofCelsius
measure
℃)或微伏每摄氏度(µV/℃)。
(µV/°C).
for this specification are parts
per million
Output DataperFormat:
数据输出格式：见双极偏移二元码 degree Celsius
See Bipolar(ppm/°C)
OffsetorBinary
（BOB）， microvolts
Codeper
偏移二进制补码 degree
(BOB), Celsius
(COB),
Complementary (µV/°C).
标准二进制补码 (CSB),补码
Offset Binary Code (CTC)，
(COB),或
Complementary
Output
单级直接二进制码 Straight
Data Format:
(USB) SeeBinary
BipolarCode (CSB),
Offset ’Complementary
Binary Twos Complement
Code (BOB), Complementary (CTC)
Offset BinaryCode, or Unipolar
Code (COB),
Straight Binary Code
Complementary (USB).
Straight Binary Code (CSB), ’Complementary Twos Complement (CTC) Code, or Unipolar
输出保持时间：转换器输出的数据的有效时间
Straight Binary CodeThe (USB). 。
Output Hold-time: amount of time that the output data of the converter is valid.
过量程回复
Output （也叫超量程回复或过电压回复
Hold-time: The(alsoamount of time that）：the 在模拟输入信号超过输入量程的绝对值
output data of or
theover
converter is valid. ，再返回到规定的电
Overrange Recovery known as out-of-range recovery voltage recovery): After the
压范围内
analog ，此时转换器调整到额定转换精度所花费的时间就是过量程回复
input signal goes beyond theasabsolute input range and or
returns 。
Overrange Recovery (also known out-of-range recovery over to the specified
voltage recovery):inputAfter
range,
thethe
overrange recovery time is the time required for the converter to
analog input signal goes beyond the absolute input range and returns to the specified make conversions at its rated
input accuracy.
range, the
overrange recovery time is the time required for the converter to make conversions at its rated accuracy.

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Glossary of Terms
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过量采样：一个过量采样的转换器，它的A/D采样率工作在一个远高于被转换的模拟信号的带宽频率 Glossary of Terms

。它的
Oversampling:
奈奎斯特频率fNYQUIST With: an oversampling converter, the sample rate of the A/D converter is at a much higher
frequency than the converted analog frequency bandwidth. The Nyquist frequency fNYQUIST is:
fNYQUIST > 2×fSIGNAL
fNYQUIST > × fSIGNAL
其中，fSIGNAL是输入信号中的最高频率。过量采样的好处在于可以降低通带内的量化噪声，并且把产生的
where fSIGNAL is the highest frequency of interest in the input signal. The advantages of oversampling are
the lowering of the。
谐波移到通带之外 quantization
把采样速率增大到两倍 noise contained
，信噪比 within the就能增加
SNR passband,3dB。and增大采样率同样可以使抗锯齿滤波
moving harmonics out of the
band of
器的设计更简单。 interest. Increasing the Oversampling Rate by two theoretically improves SNR by dB. Using
Oversampling techniques makes anti-aliasing filter design easier. (Also see Nyquist Theorem.)
Passband:
通带：对于模拟滤波器 With an analog filter, the frequency span from dc to the analog
，频率的范围从直流到模拟滤波器的截止频率 cutoff frequency is defined
，这段区域被定义为通带。通带内信 as
the passband region. The APASS，
号幅值的通过比率定义为 magnitude 见图of the response in the passband is defined as
20. 这些通带内的频率曲线可以是平坦的 APASS, as，
，没有起伏 shown
就像模拟的in
Figure 0. The response in the passband can be flat, with no ripple, as it is when an analog Butterworth or
Butterworth
Bessel filter 或者 Bessel滤波器
is designed. 。相反，Chebyshev
Conversely, a Chebyshev滤波器就有波纹起伏
filter has a ripple up，to一直延伸到截止频率边缘处
the cutoff frequency. The 。这个
magnitude 。 a filter is defined as ε.
of the ripple error of
起伏造成的幅值误差定义为ε
fCUT-OFF
M�=�filter�order �
Gain (dB)
APASS
fSTOP
AMAX
ASTOP
Passband Transition Stop�band Frequency (Hz)

band
Figure 20. Key

图Analog Filter Design Parameters
20. 模拟滤波器设计的关键参数
Parallel Interface: A parallel interface is where the A/D converter interface is capable of transferring more
than one bit simultaneously. The other type of A/D converter interface is a serial interface.
并行接口：装备并行接口的A/D转换器能够同一时间传输超过一个比特位的数据。其它类型的A/D转换器接口
Phase
是串行接口 Noise: Phase noise describes short-term, random frequency fluctuations (or time-based jitter) of a
。
clock or input signal. Frequency stability is a measure of the degree to which an oscillator maintains the
same value of frequency over a given time. When phase noise is measured,
相位噪声：相位噪声描述了时钟或输入信号在短期内频率的随机波动（或者时间上的抖动 it shows small
）。 variations
频率稳定性衡 in
the frequency phase angle with the signal magnitude constant.
量的是一个振荡器在给定时间内保持频率稳定不变的能力。 When observed
从测量得到的相位噪声可以看成 on a spectrum
， analyzer,
保持信号幅度
amplitude and phase noise appears as sideband noise on both sides of the carrier. Often, phase noise
不变的情况下，频率的相位角有小的波动。如果用频谱分析仪观看，幅度和相位噪声就像边带噪声一样位于
specifications refer to single-sideband noise. Most phase noise measurement schemes fold both
sidebands
载波频率的两边 together. Increased phase noise decreases
。通常相位噪声只是指单边带噪声 the magnitude of SNR, degrading the overall
，大部分相位噪声的测量方法都把两个边带的噪声合为一
converter performance.
个边带。相位噪声的增加会降低信噪比SNR的大小，破坏转换器的整体转换效果。
Phase Nonlinearity: Phase nonlinearity is the deviation of the phase response from a linear-phase
相位不确定性：由于频率而造成线性相位的背离形成了相位不确定性
response as a function of frequency. 。
流水线转换器：一个流水线转换器由一些连续的部件组成
Pipeline Converter: A pipeline A/D converter consists of a，number 每个部件可以和其它部件同时执行操作
of consecutive segments. Each （见图
segment
21）。 can execute
这些器件在操作过程中作用相似 its operation concurrently
， with other
并且只能解决一个到两个比特的数据 segments (see Figure ). The segments are
。每个部件都有一个采样 -保持
similar in their function and only resolve
器，一个低精度的闪烁A/D转换器和一个加法器，包括一个用来提供增益的中间级放大器。第一步先对输入 one or two bits. Each segment has a sample-and-hold, a
low-resolution flash A/D converter, and a summing stage, including an inter-stage amplifier for providing
采样，
gain. 在做第一步粗略的转换
Stage takes a sample ， of输出的结果是最高有效位
the input voltage and makes MSB， first coarse conversion.(Latch
the并把它输入第一个锁存器 1).当一个阶
The result is then
the MSB and its digital value is fed to the
段的工作结束后，模拟信号的差值结果被传给下一部分，当第一阶段未处理的剩余数据被接下的n阶段处理 first latch (Latch ). When a segment completes an operation, it
passes the analog difference
后，MSB位穿过n个锁存器，在转换器的最后阶段和转换数据结合到一起。 to the next segment. As the residue of the first stage gets resolved in the
subsequent n-stages, the MSB value ripples through the n number of latches in order to coincide with the
end of the conversion of the last stage.

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Glossary of Terms
流水线，续 :
Pipeline
如图 21 Converter, continued:
所示，转换器部件的块数和转换精度的比特数通常是一致的，每个阶段的输出都进入输出锁存
As
器， seen in Figure , the number of ，
然后所有的数据位都被锁存输出 segments is often similar to the number of bits
这样就可以在并行数据总线上使用它们了 of resolution. The
。整个转换过程造成的数据
outputs of each stage are combined in the output latch. Then, all data bits are latched in the output and
延迟（见图1）有几个时钟周期（请参考相应型号的转换器资料单）。
are available on the parallel data bus. This process results in a data latency (see Figure ) of several
clock cycles (refer to the respective product data sheet).
VIN
Stage�1 Stage i Stage n
VIN
Latch�1 Latch�1
Latch n Latch n-i
Digital Error Correction and Output Latch
Bit�1,�MSB Bit i Bit n,�LSB
Figure 21. Pipeline

图21. 流水线A/DA/D
Converter
转换器拓补结构 Topology
Pipeline Delay (Latency): see Latency, pipeline.

流水线迟滞(延迟):见延迟，流水线.
Power Dissipation: The A/D converter consumes this amount of power as a function of sampling
frequency
功率损耗：and A/Dquiescent current. This value is an important specification。
转换器消耗的功率用在了对频率采样过程和静态电流上面 for在对功率消耗要求很严格的场合
power-sensitive applications
and
这是个关键的参数，同样的还有元件各自所需的环境，包括电池能提供的电流，temperature
their respective environments, including battery-powered circuits, extreme 极端温度下的适应能力和器 conditions,
and/or space limitations.
件所占用的空间。
Power Down, hardware: The voltage that is applied to the A/D converter power pin is removed or made
电源断开，硬件：连接到
to be equal to 0V. With theA/D 转换器电源管脚的电路被断开
power down, software engaged,，the或者把电压降低到零。当电源切断后
power remains applied to the power，软件部
pin of
the device.
分开始介入，把电源重新加到器件的电源管脚上。
Power Down, software: In order to invoke ，
电源断开，软件：为了调用软件去关掉电源 a software power down, some A/D converters have a register
一些A/D转换器有一个寄存器选项允许转换器切换到静态电流
option that powers down the converter to a quiescent current that is lower than the current flowing during
状态，此时的电流要比正常工作状态的电流小。
normal operation.
电源电压抑制比 (PSRR):电源电压的变化比上它所引起的转换数据的变化
Power Supply Rejection Ratio (PSRR): The ratio of a change in the ，电源电压抑制比单位是
power-supply voltage to dB 或µV/V。
resulting bit
change. This specification
• 直流电源电压抑制比(DC PSRR或PSRR)— is expressed in dB or µV/V.
• DC DC Power-Supply
PSRR是转换输出的代码的变化量 Rejection Ratio (DC PSRR or PSRR)—
（换算成输入电源）比上直流电源的电压变化量
DC PSRR is the ratio of output code change (converted to input voltage) to the dc change in
• power-supply
交流电源电压抑制比 voltage.(AC PSRR)—
• AC AC Power-Supply
PSRR 是输出的谱功率比上加在正电源管脚的输入的交流功率
Rejection Ratio (AC PSRR)— ，这里的功率指的是某个频率的谱功
率， AC PSRR is the ratio of
各个谱功率共同组成 FFT the 。
图 output spectral power with respect to the 100mV
输入的交流电压波动幅值应限制在小于 injectedPPac-power on the positive
。交流电源电压抑制比单
supply
位是dB。 pin at that frequency, displayed on an FFT plot. The ac-input amplitude on the power supply
should be limited to less than 00mVPP. This specification is expressed in dB.
可编程增益放大器(PGA): 可编程增益放大器是一个数字编程有增益的模拟放大器。
Programmable Gain Amplifier (PGA): A programmable gain amplifier is an analog amplifier with
digitally-programmed gain.
量化：一个连续范围的模拟输入值被分成许多不重叠的子区域，这个过程就叫量化。在 A/D 转换器的输出
Quantization:
端，每个子区域都形成独一无二的离散的数值。这个量化的过程理论上决定了转换器的信噪比
Quantization occurs when a continuous range of analog input values are divided SNR（into 见信噪
non-overlapping
比）。 sub-ranges. Each sub-range becomes a unique, discrete value at the output of the A/D
converter. This specification sets the theoretical limit of the converter SNR. (See Signal-to-Noise Ratio.)
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Quantization Noise: The noise that an A/D
Glossary converter generates as
of Terms
量化噪声：A/D转换器产生量化噪声是由于把输入的连续信号切割成离散的数值 signal into discrete buckets. The ideal width of
。在理想状态下，these
这些离散 buckets is equa
Quantization Noise: The noise that an A/D converter generates
数值大小等于转换器的最低有效位LSB所对应的数值。任何一个A/D转换器都存在±1/2 个LSB的不确定性This
The as a consequence
uncertainty of any A/D of dividing
converter the
bit input
is ±/ LSB. ， characteri
signal into discrete buckets. The ideal width of these bucketswith is
noequal to the LSB
Differential size of the(DNL)
Non-Linearity converter.
errors. If it is assumed the re
这些描述对一个理想的没有差分非线性误差的转换器来说是成立的
The uncertainty of any A/D converter bit is ±/ LSB. Thisacross
characterization
an analog 。假设这个量化噪声是在输入的模拟信号
is truesignal,
input for a perfect
the rmsconverter
value of the triangular signal i
with no上叠加一个三角波
Differential Non-Linearity (DNL) errors. If it is assumed
，这个三角波的均方根值就等于信号的幅值除以 dividedthebyresponse
the √. of this error is a triangular
across an analog input signal, the rms value of the triangular signal is equal to the magnitude
� (LSB) of signal
divided by the √. 2
q
Quantization�Noise�(rms)�=��=
� (LSB) 12
q 3
量化噪声均方根 = 2
Quantization�Noise�(rms)�=��=
12
3 With:
• q = ideal code width
With:
• q = ideal code width Ratiometric Operation: This term describes an environment where
其中: reference voltage as is used to drive the signal source, such as a se
Ratiometric Operation: This term describes an environment
outputwhere
codethe is aconverter
function uses of thethe same
ratio of reference voltage to the signa
• q =理想码元宽度
reference voltage as is used to drive the signal source, such as a sensor. Under
value of the reference voltage. these conditions, the
output code is a function of the ratio of reference voltage to the signal source and is independent of the
value of the reference voltage. Record of Data: A record of data is a collection of samples that are
比率操作：这个术语描述的是转换器消耗相同参考电压情况下的环境 an A/D converter. ，就像驱动信号源（比如一个传感
Record of Data: A record of data
器），这种环境下，输出编码是参考电压与信号源的比率的函数 is a collection of samples that are acquired in a sequential fashion from
而且其输出独立于参考电压
an A/D converter. Resolution:， When describing the general。 performance of a converte
数据记录：A/D转换器连续地进行采样，把这些采样数据收集起来就是数据记录 output bits that an A/D converter can produce
。 number of possible in one conversion. Res
Resolution: When describing the general performance ofincrement a converter, resolution istothe
corresponding a LSB converter change. This critical sp
output 分辨率：衡量一个转换器的一般工作性能的时候
bits that an A/D converter can produce in one conversion. Resolution
analog input
，分辨率是一个 signal also
that canis the
A/D转换器一次转换所能输出的比特位数 besmallest
resolved. analog 。
increment corresponding to a LSB converter change. This critical specification determines the smallest
分辨率也是一个最低有效位LSB的变化量所对应的最小模拟增量 Rise Time: Rise 。这个关键参数决定了转换器所能分辨的输
time is the time required for a signal to rise from 0
analog input signal that can be resolved.
入模拟信号的最小增量。 that range.
Rise Time: Rise time is the time required for a signal to rise from 0% of the transition range to 0% of
that range.
上升沿时间：上升沿时间是一个信号从10%幅值范围上升到 Root-mean-square
90%幅值范围所需的时间 (rms): RMS 。 is a mathematical term for the stand
The calculation of rms is equivalent to the square root of the arithme
Root-mean-square
均方根(rms):RMS (rms): RMS is a mathematical
是一个数学名词 term for
，用来表示数据记录的标准偏差 the standard
difference 。deviation
between 均方根 the data from
(rms) a record
的计算公式等于平方值
and of data.
the mean). （数
The calculation of rms is
据与平均数的差）的算术平均值再求平方根。 equivalent to the square root of the arithmetic mean of the squared values (the
difference between the data and the mean). Root-sum-square (rss): For a given set of data, rss is the square-ro
和的平方根(rss)：对一组给定的数据，rss等于平方的和再求根 Sampling: 。Sampling assigns discrete time values to a continuous tim
Root-sum-square (rss): For a given set of data, rss is the square-root-of-the-sum-of-the-squares.
采样：采样过程把连续时间的信号划分为在离散时间上的数据。 signal.
Sample-and-Hold (or S&H): A sample-and-hold circuit has an analo
Sampling: Sampling assigns discrete time values to a continuous time
opens (samples) ， a short
for duration to capture (hold) the analog inp
Sample-and-Hold (or S&H
采样与保持（或）：采样和保持电路有一个可切换的模拟输入
S&H): A sample-and-hold circuit has an analog-switched 它打开（采样
input ）a一个短时间以获得
with function that （保
opens 持(samples)
）模拟输入电压 for a short duration to capture (hold) theSampling
analog input Time: Sampling time is the time required to sample an an
voltage.
of accuracy. Also see Acquisition Time.
Sampling Time: Sampling time is the time required（
采样时间：采样时间是采集一个模拟输入信号 to同时要求达到一定精度
sample an analog input signal to a 。
）所需的时间 specified
参考采集时间 level 。
of accuracy. Also see Acquisition Time. Sample Rate: The Sample Rate is the speed that a converter can co
采样率：转换器要连续转换多个数据所要求达到的速度就是采样率 conversions. This critical specification determines the largest allowab
。这个关键参数决定了输入的模拟信号所
Sample Rate: The Sample Rate is the speed that a converter signal.can continuously
Typically specifiedconvert several per second (sps) or hertz (Hz)
as samples
conversions. This critical specification determines the (sps)
允许的最大带宽。通常所用的单位是采样点每秒或赫兹(Hz).（同样请参考最大转换速率）
largest
Rate.)allowable bandwidth of the analog input
signal.逐次逼近
TypicallySAR
specified as samples per second (sps) or hertz (Hz). (Also see Conversion
转换器：在中等分辨率和中等采样率的转换器中常常采用逐次逼近 SAR转换器 Maximum。它的转换精度
Rate.) 从 SAR Converter: Successive-approximation register (SAR) converter
8 bits到18 bits，转换速率通常小于10MSPS。它具有低功耗和小形状因子的特点 choice for medium-resolution applications 。图22画出了典型的 with mediumSARsampling rate
SAR Converter:
模数转换器的结构图。 Successive-approximation register (SAR) converters are frequently the architecture of
resolution from bits to bits with speeds typically less than 0MS
choice for medium-resolution applications with medium sampling consumptionrates.andSARhaveA/D aconverters
small formrange
factor.inFigure illustrates a typ
resolution from bits to bits with speeds typically less than 0MSPS. They provide low power
consumption and have a small form factor. Figure illustrates a typical SAR converter architecture.
ZHCA068-August 2006-Revised January 2008 SBAAA – August 00 – 术语词汇表

Revised January 00
：模数转换的规格和性能特点A Glossary of Analog-to-Digital
25 Specific
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Glossary
Glossary ofofTerms
Terms
SAR转换器，续
SAR Converter,: continued:
R/C
Clock
Successive�Approximation�Register�and�Control�Logic CS
BUSY
CDAC Comparator
SS MSB
Analog Input Cap Output
Latches Parallel
and or�Serial
Three Data
VREF Bus
VREF State
Drivers
Buffer
5k�
Reference Internal
Input�or�Output Reference
Figure 22. Successive Approximation

图22. 逐次逼近SAR Register A/D Converter Block Diagram
模数转换器结果框图
In more recent designs, the topology of SAR A/D converters use a capacitive redistribution design
approach instead its predecessor architecture, the R-R ladder topology. The capacitive-redistribution,
在最近的设计中模数转换器的拓补结构采用了电容性的再分区设计方法，取代了原先的设计方
SAR converter uses，SAR a capacitive array at the analog input (see Figure ). The capacitive array and the
remainder
法，R-2R阶梯结构of the device can be manufactured in a CMOS
。使用电容性的再分区方法设计的 SARprocess, making it easy to integrate the SAR
模数转换器在模拟输入端有一个电容阵列（见图
converter
22）， with microcontrollers
这个电容阵列和其它部件可以使用 or microprocessors.
CMOS With
制造工艺进行制作 the topology
，使 shown
SAR in Figure ,
转换器更容易与微控制器或微处 the analog input
voltage is initially sampled by connecting the input signal to the bottom side of sampling capacitors. This
configuration is achieved22
理器集成在一起采用如图所示的拓补结构图
with ，通过连接输入信号到底部的采样电容
the sampling switch ，对模拟输入电压进行
(SS). The other ends of these sampling capacitors are
connected
初步采样。to the reference voltage. Once。the
这个构造由采样切换开关完成 capacitors are fully charged from
采样电容的另一端与参考电压相连 the analog input voltage,
，一旦输入的模拟电压对电容
the internal
充满电 capacitive array of the converter is
，转换器内部的电容阵列就和输入信号、disconnected
参考电压都断开了 from。 the input signal as well the voltage
reference.
Now既然输入信号已经被采样
that the input signal has， been sampled, the bottom
底部的最高有效位 side of the MSB capacitor
MSB电容就和参考电压相连了 is connected to the
，同时其它的电容都被接到
reference voltage while the other capacitors
系统地线。这样，最高有效位MSB电容的电荷被分布到其它电容里去。比较器的输入电压按照电荷分布状况 are tied to the system ground. With this action, the charge
from the MSB capacitor is distributed among the other capacitors. The comparator input moves up or
的不同上下浮动
down in voltage ，如果加在电容阵列上的电压比比较器的参考电压大
according ，最高有效位
to the way the charge is distributed. If the voltage acrossMSB 就被设成零array
the capacitive ，同时 is
greater
MSB than the comparator
电容被固定在电压 VREF。reference, an MSB equal to zero is generated and，
如果加在电容阵列上的电压比比较器的参考电压小 the MSB capacitor
最高有效位 is left
MSB就被设成
tied to V同时
“1”， REF. MSB
If this电容被固定在电源地线
voltage is less than the
。 comparator reference, an MSB bit equal to '' is generated, and
the MSB capacitor is connected to ground.
With当最高有效位
the determination of the value
MSB确定之后 of the MSB, the
，转换器开始检查 MSB converter
的下一位的数值 then examines
。要完成这一步 the MSB– value. This
，可以在其它电容都
process is done by connect the MSB– capacitor
接地的情况下，把MSB-1位的电容接到参考电压上。比较器再一次重复前一步的工作，比较这个电压和内部 to the voltage reference while the other capacitors are
tied to ground. Once again, a comparison of this voltage to the internal voltage reference is done with the
参考电压的大小。如果电压比比较器的参考电压大
comparator. In this analysis, if this voltage is greater ，MSB-1
than the位就被设成零同时MSB-1
comparator，reference, an位的电容被固定在电
MSB– equal to
zero is generated and the MSB–
压VREF。如果电压比比较器的参考电压小， MSB-1位就被设成 capacitor is left tied to V . If this voltage
REF“1”，同时MSB电容被固定在电源地线is less than the comparator
。以
reference, an MSB–
上过程不断被重复，直到电容阵列被充分利用。 bit equal to one is generated and the MSB– capacitor is connected to ground. This
process is repeated until the capacitive array is fully utilized.
The在一个转换器的前端接有多路复用器的情况下
SAR architecture is ideal for applications where a multiplexer may be used before to the converter,
，或者转换器只需要每几秒钟做一次测量的情况，或者在
applications where the converter may only
需要快速测量的场合下，采样SAR转换器的结构就很适合。它的转换时间在各种情况下都不会发生改变 need to make a measurement once every few seconds, or ，而
applications that require a fast measurement. The conversion time remains the same in all cases and has
且与流水线和 delta-sigma转换器相比
little sample-to-conversion ，SAR的采样
latency compared to a -pipeline
转换时间延迟相对很短
or delta-sigma 。因此SARSAR
converter. 转换器很适合以下实时
converters are
ideal for real-time
的应用场合，如工业控制applications
、摩托控制 such as
、 industrial
电源监控、 control,
便携电池器件 motor control,
、PDA、 power management,
测试仪器和信号数据采集。
portable/battery-power instruments, PDAs, test equipment, and data/signal acquisition.
26
A术语词汇表
Glossary of
：Analog-to-Digital
模数转换的规格和性能特点 Specifications and Performance Characteristics SBAAA – August 00
ZHCA068-August – Revised January 2008
2006-Revised 00
www.ti.com
www.ti.com
www.ti.com Glossary
Glossaryof
ofTerms
Terms
Second Harmonic (HD2): The second harmonic is two times the frequency of the fundamental. Glossary of Terms
Second
二次谐波Harmonic
Settling Time
(HD2):(as it (HD2):
relates The
二次谐波是基频波频率的两倍 to ǻȈsecond harmonic。 isThe
A/D converters): two settling
times the frequency
time of thefilter
of the digital fundamental.
in a delta-sigma A/D
converter
Settling reflects
Time (as the order
it relates of the digital filter
to ǻȈ A/D converters): internal
The to the converter.
settling time
time of the digital filter in aindelta-sigma
This is given cycles and A/D
稳定时间（ΔΣ
equal to the A/D
number 转换器与此有关）： delta-sigma A/D 转换器中数字滤波器的稳定时间反应了转换器内置
converter reflects theoforderconversions required
of the digital filter for the signal
internal to thetoconverter.
propagateThis through
time the filter.inSettling
is given cycles time
and can
be an
数字滤波器的阶数issue to consider
。 after
这个时间的单位是周期数 power-up, when ，switching channels
它等于信号穿过滤波器所需的转换周期数 with the input
equal to the number of conversions required for the signal to propagate through the filter. Settling time multiplexer, 。 after
用输入多路复用an input
can
step
be response, or
an issue to consider
器进行切换通道时 re-starting
，会造成电源的启动 the converter
after power-up,，when after a long
这时稳定时间就成为必须考虑的问题 wait time.
switching channels with the input ，multiplexer,
同样在输入一个阶跃响应或 after an input
step response, orRatio
Signal-to-Noise
是长时间之后重启转换器的情况下 re-starting
(SNR): theThe
converter after a long
，signal-to-noise
都必须考虑稳定时间 ratiowait
。atime.
is calculated rms value that represents the ratio
of ac signal
Signal-to-Noise power to noise power below
Ratio (SNR): The signal-to-noiseone-half of the sampling frequency.
ratio is a calculated rms ， The noise
value power excludes
that represents the ratio
信噪比(SNR)
harmonic ：在低于采样频率一半的条件下
signals and dc. ，交流信号功率除以噪声功率计算所得比值的均方根就是信
of ac signal power to noise power below one-half of the sampling frequency. The noise power excludes
噪比其中，噪声功率不包括谐波信号和直流
The 。
harmonic
ideal signals
SNR forand
SAR dc.and pipeline converters 。 with a full-scale sine wave input to an A/D converter is
.0n +.dB;
The一个完整的正弦信号输入
ideal SNR for n isSAR equalandto pipeline
the number
SAR 或流水线 ofA/D
convertersconverter
with abits.
转换器时 SNR can
，理想的信噪比是
full-scale sinebe specified
wave 6.02n with
an respect
input+1.76dB，
to A/D其中 to full-scale
n等于转换器
converter is
input
.0n range
+.dB;(dBFSn is orequal
dB) or to with
the respect of
number to converter
the actualbits.
inputSNRsignal
canamplitude
be (dBc).
specified withThe three to
respect different
full-scale
的比特位数。信噪比单位可以是dBFS或dB（对于完整输入信号）或者是dBc（对于实际输入信号）。有三个
formulas
input range for(dBFS
SNR are: or dB) or with respect to the actual input signal amplitude (dBc). The three different
不同的公式可以表示
formulas for SNR PSSNT:
are:
SNR�(dB)�=�10log 10 ,�where�P is�the�signal�power�and�P is�the�noise�power.
S N
P
PNS
SNR�(dB)�=�10log10 ,�where�PS is�the�signal�power�and�PN is�the�noise�power.
PN
SNR�(dB)�=�10log10 rms�signal
rms�noise
SNR�(dB)�=�10log10 rms�signal
rms�noise
(n - 1) q
(2 � )
(n - 1) q2
SNR�(dB)ideal =�10log10 (2 � ) =�6.02n�+�1.76�(dB)
q 2
SNR�(dB)ideal =�10log10 =�6.02n�+�1.76�(dB)
q12
12
Where:
其中:
• q = the LSB size
Where:
• q•• = 最低有效位
n
q= = number
the LSB of
LSB 对应的大小
bits
size
• n• = 转换器的比特位数
n= number
The ideal SNR for aofdelta-sigma
bits converter first-order modulator is .0n + .dB + 0log0(fS / (BW)),
where
The f
ideal is the
S SNR for converter sampling
a delta-sigma frequency
converter and BWmodulator
first-order is the6.02n
maximum
is+.0n frequency
+ .dB of+ interest.
0log0(f
对于delta-sigma 转换器的一阶调制器，其理想的信噪比等于 1.76dB + 10log10(fS S / (BW)),
/ (2BW)), 其中fS是
where
Other f is
dynamic
转换器的采样频率 S the converter
or ac
，BW sampling
specifications
是最高频率include frequency and BW is the maximum frequency of
the Signal-to-Noise Ratio plus Distortion (SINAD
。其它的动态或者交流参数包括信噪比加上失真 interest.
(SINAD或者 or SNR+D),
SNR+D)、
Effective
Other Number
dynamic or Of
ac Bits (ENOB), Total
specifications Harmonic
include the Distortion (THD),
Signal-to-Noise Ratio Spurious
plus Free Dynamic
Distortion (SINAD Range
or SNR+D),
有效比特数(ENOB、总的谐波失真(THD)、无杂波动态范围(SFDR)、互调失真(IMD)和全功率带宽(FPBW)。
(SFDR),
Effective Intermodulation
Number Of Bits Distortion
(ENOB), Total(IMD), and Full-power
Harmonic Bandwidth
Distortion (FPBW). Free
(THD), Spurious (AlsoDynamic
see Quantization
Range
Noise.)
（请参考量化噪声）。
(SFDR), Intermodulation Distortion (IMD), and Full-power Bandwidth (FPBW). (Also see Quantization
Noise.)
Signal-to-(Noise
信噪比加上失真 (SINAD Ratio plus 或者Distortion) (SINAD or SNR+D, also
SNR+D ，也叫总谐波失真加噪声 ) ：called
SINAD Total Harmonic
结合计算了 SNR Distortion
和总谐波失真
plus Noise):
Signal-to-(Noise
(THD)。在频率低于采样频率一半 SINAD is the calculated
Ratio plus Distortion)
（不包括直流combination
(SINAD of SNR
or SNR+D,
）的条件下 and total harmonic distortion (THD).
also called Total Harmonic Distortion
，它等于基波输入信号的幅值均方根除以所有其 SINAD is
the
plusratio of the rms
Noise): SINAD is theamplitude of the
calculated fundamental input signal
combination of SNR and total to the rms sum
harmonic of all other
distortion spectral
(THD). SINAD is
它频谱信号的和的均方根
components below 。SINAD 的理论最小值等于理想信噪比 SNR 或者 6.02n + 1.76dB（如果是 SAR或流
the ratio of the rms one-half
amplitudeofofthe thesampling frequency
fundamental input (excluding
signal to the dc).
rmsThe
sumtheoretical minimum
of all other spectralfor SINAD
is equal to the
水线转换器
components ）。 idealone-half
below SNR or of .0n + .dB frequency
the sampling with SAR and pipelinedc).
(excluding converters.
The theoretical minimum for SINAD
is equal to
SINAD�= �20log the ideal SNR
�SNR/10or .0n +
+THD/10 .dB
or with SAR and pipeline converters.
10 (10 +�10 )
+THD/10
SINAD�= �20log10 (10 �SNR/10
+�10 ) or
PS
SINAD�=�10log10
PNP+�PD
S
SINAD�=�10log10
PN +�PD
其中:
Where:
• P•S 基波信号的功率
Where: ;
PS is the fundametal signal power;
• P is
• P•N 所有频谱的噪声功率the power of all ;the noise
PNS is the fundametal signal spectral components; and
power;
• P••D所有频谱的失真功率
P
PDN is
is the
the power
power of
of all
all。 the
the distortion spectral
noise spectral components
components; and
•
SINAD P is the power of all the distortion spectral
is Deither given in units of dBc (decibels components
to 的单位是
carrier) when
当基波的功率用绝对功率值来衡量时，SINAD dBc（the absolute power of）；
相对于载波的分贝数 the 当基波的功率被外
fundamental is
used
SINADas the reference,
is either given in or dBFS (decibels
units of的单位是 to
dBc (decibels full-scale) when
to相对于满量程的分贝数 the power of the
carrier) when the absolute fundamental is extrapolated
推到转换器的满量程值，SINAD dBFS（）。 power of the fundamental is
used as the reference, or dBFS (decibels to full-scale) when the power of the fundamental is extrapolated
ZHCA068-August
SBAAA 2006-Revised
– August January
00 – Revised 200800
January A Glossary of Analog-to-Digital Specifications
术语词汇表 and Performance Characteristics
：模数转换的规格和性能特点 27

Feedback
Glossary of Terms
to the converter full-scale range. SINAD is a critical specification for digital oscilloscope/waveform
recorders, as well as geophysical, image processing, radar, sonar, spectrum analysis, video,
telecommunication, and wideband digital receiver applications. Other dynamic or ac specifications include
the Signal-to-Noise Ratio (SNR), , Effective Number Of Bits (ENOB), Total Harmonic Distortion (THD), www.ti.com
Glossary of Terms
Intermodulation Distortion (IMD), and Full-power Bandwidth (FPBW).
Small Signal: A voltage input signal whose peak-to-peak amplitude spans not more than 0% of the full
input range ofSINAD
the A/D converter./
在数字振荡波形记录仪中是个关键参数，它同样还广泛用在地球物理学、图像处理、雷达、声
纳、频谱分析、视频、电信和宽带数字接收应用中。其它的动态或者交流参数包括信噪比 (SNR)、有效比特
Spurious Free Dynamic Range (SFDR): The distance in dB on an FFT plot from the fundamental input
数(ENOB、
signal to the highest spur.(THD)、
worst or总的谐波失真 SFDR can 互调失真 (IMD)和全功率带宽
be specified with respect(FPBW)。
to full-scale input range (dBFS or
dB), or with respect to the actual input signal
小信号：输入信号的峰峰值电压小于A/D转换器满量程输入值的10%， amplitude (dBc). (See Figure .)那就算是小信号
SFDR is a critical
。
specification for telecommunication and video applications. Other dynamic or ac specifications include the
Signal-to-Noise
无杂散动态范围 Ratio (SNR), Signal-to-Noise
(SFDR): 在FFT图中， Ratio plus Distortion (SINAD or SNR+D), Effective Number
从输入的基波信号到最糟的或是最高频率杂波的距离（单位是dB）。
Of Bits (ENOB), Total Harmonic Distortion (THD), Intermodulation
SFDR 单位可以是 dBFS 或 dB（相对于满量程输入范围），也可以是 dBc（相对于实际的输入信号幅值）， Distortion (IMD), and Full-power
Bandwidth (FPBW).
（见图23）。SFDR在电信和视频应用中是个关键参数，其它的动态或者交流参数包括信噪比 (SNR)、信噪
Static Specifications: Static specifications are the A/D converter specifications pertaining to a dc signal
比加上失真(SINAD或者SNR+D)、有效比特数(ENOB、总的谐波失真(THD)、互调失真(IMD)和全功率带宽
input. These specifications generally include Offset Error, Gain Error, DNL, INL, and TUE.
(FPBW)。
Step Response: The step response is the time required for the output digital results to reflect the rated
accuracy 静态参数：静态参数是
of the converter after the
A/Dinput voltage goes from the lowest input voltage
转换器的输入为直流量的情况下所对应的参数。to the highest input
这些参数包括偏置误差、增益误
voltage (or vice-versa).
差、DNL、INL和转换噪声。
SPI (Serial Peripheral Interface): See –Digital Interface SPI. （或者反过来）时，数字信号的输出要达到指定精度
阶越响应：当转换器的输入电压从最低值上升到最高值
Successive Approximation Register
所需的时间就是阶越响应。 Converter (SAR): See SAR Converter.
Synchronous Sampling: Synchronous
SPI (串行外设接口 ): 见 –数字接口 sampling
SPI. is where the input signal is phase locked to the
sampling of another signal and/or to the A/D converter sampling frequency.
逐次逼近寄存器转换器 (SAR): See SAR转换器.
Temperature, Specified: The temperature range where electrical specifications apply. If the device is
taken beyond
同步采样 the specified temperature range, the typical, maximum, and
: 同步采样是输入信号与另一个被采样的信号相位锁定 minimumA/D
，或者是与 specifications
转换器的采样频率相位锁定do not 。
apply.
温度，参数：电子器件能够工作的温度范围。如果器件的工作环境超出规定的温度范围，那些典型指标、最
Temperature, Storage: The temperature range limiting storage conditions. If the device is stored at
大最小指标参数都不再适用。
temperatures beyond the stated storage temperatures, damage to the device may occur.
温度，存放：温度范围限制了存放条件。如果器件存放的环境超出规定的存放温度，可能会对器件造成损害。
Temperature, Junction: The maximum allowed internal junction temperature. If this junction temperature
is exceeded, the device may stop operation。and/or
温度，结：允许的最大内部结温度 damage may occur.，器件可能会停止工作，而且/或者造成损害。
如果结的温度超过规定值
Temperature, Operating: The temperature range limits
温度，工作：器件能够持续工作的温度限制 where the product continues
，这个条件不是必须满足的。 to operate, but not
necessarily to specification.
热噪声：热噪声是由电阻产生的。理想状况下，热噪声等于：
Thermal Noise: Thermal Noise is generated by a resistor. Ideally, this noise is equal to:
电阻热噪声=
Thermal�Resistor�Noise�= 4kTRB
Where: 其中:
–
• k •= Boltzmann's
k = 波尔兹曼常数 constant,, .
1.38×× 0
10–23;;
• T = temperature in degrees Kelvin; and
• T =开尔文温度;
• B = bandwidth
• B = 带宽
Thermal Impedance: Thermal impedance quantifies a component or device capability to dissipate heat.
In electronics, this heat is normally generated by the device power. With components, the overall thermal
热阻抗：热阻抗衡量一个元件或者器件的散热能力，在电子元件中，热量一般由器件的电源产生，再加上各
impedance causes a rise in temperature that is linearly dependent on the power dissipated in the device.
The coefficient is called θ, and has the units，of并且与电源扩散到元件中的热量成线性关系
个元件的热阻抗就造成了温度升高 °C/W. 。这个参数定义为θ，单位
为℃/W。
Third Harmonic (HD3): The third harmonic is three times the frequency of the fundamental.
三次谐波
Throughput rate: (HD3): 三次谐波是基波频率的三倍
Throughput rate is the inverse of 。
throughput time.
Throughput Time: The time required for the
吞吐量：吞吐量就是吞吐率的反比。 converter to sample, acquire, digitize, and prepare for the
next conversion. This time is also the
吞吐率：转换器采样、收集、数字化并准备下一转换所花的时间 minimum conversion time in a continuous conversion application.
，这个时间也是连续转换数据所需的最小时
Timing Jitter:
间。 See Aperture Jitter.
Timing Phase
时间抖动 Noise: See Aperture
: 见孔径抖动 . Jitter.
时间相位噪声: 见孔径抖动.

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Glossary of Terms
Total Harmonic
总谐波失真 (THD):Distortion (THD): The rms sum of the powers 。
各个谐波功率的和的均方根比上输入信号功率 of这个比值的单位用均方根分贝值
the harmonic components (spurs)
Glossary of Terms
(dB) 或均
ratioed to the input signal power. This ratio is specified in rms decibels (dB) or rms dBc. The formula
Total
方根 dBc
Harmonic
表示，THD Distortion (THD):
计算公式如下： The rms sum of the powers of the harmonic components (spurs)
describing THD is:
ratioed to the input signal power. This ratio is specified in rms decibels (dB) or rms dBc. The formula
describing THD
THDRMS =�20log 10 is:((10
HD2/20 2
) +�(10
HD3/20 2
) +�(10
HD4/20 2
) +.�.�.) or
HD2/20 2 HD3/20 2 HD4/20 2
THDRMS =�20log10 ((10 ) +�(10 ) +�(10 ) +.�.�.) or
PS
THDRMS =
P
PO
THDRMS = S
Where: PO
其中 :
• PS = power of the first harmonic (signal power); and
Where:
• PS = 一次谐波功率 (信号功率);
• PO = power of the first specified harmonics
• P••O =P S = power of the first harmonic (signal power); and
指定的一次谐波功率
HD = magnitude of the second harmonic
• PO = power of the first specified harmonics
• HD2 = 二次谐波的幅值
Significant
• HD INL errors of the
= magnitude of theA/D converter
second typically appear in the THD results. THD is usually specified
harmonic
with转换器明显的积分非线性误差
A/D the input signal close to full-scale; see Figure .
INL一般都出现在总谐波失真 THD中。THD一般都由近满量程的输入信号指
Significant INL errors of the A/D converter typically appear in the THD results. THD is usually specified
定见图 23. signal close
， the input
with to full-scale; see Figure .
FREQUENCY�SPECTRUM
(8192�point�FFT,�FIN =�10.0022kHz, �0.2dB)
0 FREQUENCY�SPECTRUM
B(8192�point�FFT,�FIN =�10.0022kHz, �0.2dB)
0
�20
B A:�Fundamental�Signal�Magnitude
�40
�20
Amplitude�(dB)
�60 A:�Fundamental�Signal�Magnitude
C.�Signal-to-Noise�Ratio�= �85dB
�40
D:�Spurious�Free�Dynamic�Range�= �96dB
Amplitude�(dB)
�80
�60 C C.�Signal-to-Noise�Ratio�= 85dB
E:�Average�Noise�Floor�= ��125dB
A F G D:�Spurious�Free�Dynamic�Range�= �96dB
F:�First�Harmonic�Magnitude�= �105dB
�100
�80
C E:�Average�Noise�Floor�= �125dB �96dB
G:�Second�Harmonic�Magnitude�=
A F G F:�First�Harmonic�Magnitude�= �105dB
�120
�100 E G:�Second�Harmonic�Magnitude�= �96dB
�140
�120
E
�160
�140
0 10 20 30 40 50
�160
Frequency�(kHz)
0 10 20 30 40 50
NOTE: THD is the aggregate of Frequency�(kHz)
harmonics (F, G, etc.) above the fundamental input signal (A).
NOTE:注意
THD is the
: THD aggregateFigure
是输入基波频率信号 (A)23.
of harmonics Total Harmonic
(F, G, etc.)
之上的谐波 (F, G,above theDistortion
etc.)的总计 fundamental FFT Plot (A).
input signal
Figure 23. Total HarmonicFFT

图23. 总谐波失真 Distortion
图 FFT Plot
THD is either given in units of dBc (decibels to carrier) when the absolute power of the fundamental is
used as the reference, or dBFS or dB (decibels to full-scale) when the power of the fundamental is
THD is eithertogiven
当基波的功率用绝对功率值来衡量时
extrapolated in units offull-scale
the converter dBc (decibels，THD
range. toTHD
carrier)
的单位是 is awhen
dBc（ the
critical absolute power
相对于载波的分贝数
specification of the
）；fundamental
for geophysical 当基波的功率被外 is
applications.
used as the reference, or dBFS
Other dynamic or ac specifications
推到转换器的满量程值，THD的单位是 or dB (decibels
include to full-scale)
the 相对于满量程的分贝数
dBFS（ when the
Signal-to-Noise Ratio (SNR), power
）。THD of the fundamental
Signal-to-Noise
在地球物理学应用中是个关 is
Ratio plus
extrapolated
Distortion to theorconverter
(SINAD SNR+D), full-scale
Effective range.
Number THDOf isBits
a critical
(ENOB), specification
Spurious for geophysical
Free Dynamic applications.
Range (SFDR),
键参数
Other ，其它的动态或者交流参数包括信噪比
dynamic or ac specifications include (SNR)、信噪比加上失真
the Signal-to-Noise (SINAD
Ratio (SNR), 或者 SNR+D)、
Signal-to-Noise 有效比特数
Ratio plus
Intermodulation Distortion (IMD), and Full-power Bandwidth (FPBW).
Distortion
(ENOB)、 (SINAD
无杂散动态范围 or SNR+D), Effective
(SFDR)、互调失真 Number
(IMD) Of Bits
和全功率带宽 (ENOB), Spurious
(FPBW)。 Free Dynamic Range (SFDR),
Total HarmonicDistortion
Intermodulation Distortion plus and
(IMD), Noise: See Signal
Full-power to noise(FPBW).
Bandwidth ratio plus distortion.
总谐波失真加上噪声: 见信噪比加上失真。
Unadjusted
Total Harmonic Error (TUE):
Distortion plusTUE is aSee
Noise: dc specification
Signal to noisethatratio
determines the overall deviation of digital
plus distortion.
code as it differs(TUE):
总的未调整误差 TUE是个直流量参数
from ideal. This error includes Offset, Gain, and nonlinearity errors
，它决定了数字编码偏离理想值的总量 in its calculation.
。在计算中，这个误差包
Total Unadjusted Error (TUE): TUE is a dc specification that determines the overall deviation of digital
括偏置、it增益和非线性误差
differs from ideal.。This error includes Offset, Gain, and nonlinearity errors in its calculation.
TUE�=�OFFSET�+�GAIN�+�INL�+�DNL
code as
Transfer Function (transfer
传输函数（传输曲线）： curve): An A/D converter representation of the average digital
A/D转换器的数字输出编码的平均表现与模拟输入信号的对比图
TUE�=�OFFSET�+�GAIN�+�INL�+�DNL 。（见图 output
10）code
compared to the analog input value. (See Figure 0)
Transfer Function (transfer curve): An A/D converter
转换点：输出的数字信号从一个编码跳到下一个 representation of the
，此时对应的模拟输入电压。（average
见图10） digital output code
TransitiontoPoint:
compared The analog
the analog input voltage
input value. at which
(See Figure 0) the digital output switches from one code to the next.
转换噪声 : 见代码转换点和不确定性
(See Figure 0) 。
Transition Point: The analog input voltage at which the digital output switches from one code to the next.
Transition
双频互调失真
(See : 见互调失真
FigureNoise:
0) (IMD)。
See Code Transition Point and Uncertainty.
Two-Tone Intermodulation
Transition Noise: See CodeDistortion: See Intermodulation
Transition Point and Uncertainty.Distortion (IMD).
Two-Tone Intermodulation Distortion: See Intermodulation Distortion (IMD).

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Glossary of Terms
Glossary of Terms
Undersampling: In an undersampling system, the sampling rate of the A/D converter is lower than the
input frequency, causing ，A/D
欠采样：在欠采样系统中 aliasing to lower frequencies. With undersampling
转换器的采样率比输入频率低，造成低频的混淆现象 circuits, 。
the采样欠采样电路
bandwidth of the
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，感
signal of interest (ǻfSIG) is centered at a higher frequency than the sampling frequency (fSAMPLE) of the
Glossary of Terms
兴趣的信号频率带宽 (ΔfSIG)被放置在一个比转换器采样率(fSAMPLE)更高的频率上。
converter:
Undersampling:
fSAMPLE > (ǻfSIG In an
) undersampling system, the sampling rate of the A/D converter is lower than the
input frequency, causing aliasing to lower frequencies. With undersampling circuits, the bandwidth of the
ǻf SIG isoflimited
signal by(ǻf
interest an analog bandpass filter that acts like an anti-aliasing filter in this system. The
SIG) is centered at a higher frequency than the sampling frequency (fSAMPLE) of the
Δbandwidth
converter: of the
fSIG的大小由模拟带通滤波器限制， sample-and-hold (or这个滤波器在系统中就像抗混叠滤波器
track-and-hold) function of the input of。A/D the A/D converter must be
转换器中采样保持电路的
capable of handing these high-frequency signals.
fSAMPLE > (ǻf
带宽必须足够大 )
能够处理这些高频的信号
，SIG 。
Uncertainty: Refer to Code Transition and Noise.
ǻf
不确定性SIG is limited by an
: 参考转换编码和噪声. analog bandpass filter that acts like an anti-aliasing filter in this system. The
Unipolar Offset:
bandwidth of the sample-and-hold (or track-and-hold) function of the input of the A/D converter must be
单极偏置
capable
• Error– : handing these high-frequency signals.
of
See
误差Offset
•Uncertainty: – Error.to Code Transition and Noise.
Refer
•见偏置误差Drift–
Unipolar Offset: .
See Offset Error.
•• Error–
漂移–
Unipolar
See OffsetGain:Error.
Drift– .
见偏置误差
• Error–
单级增益 Gain
See Offset
: Error.
Error.
•Unipolar
Drift–
• 误差– Gain:
• See
Error– Gain Error.
见增益误差 .
Unipolar
See Gain Straight
Error.Binary Code (USB): With the lowest input voltage, the digital count begins with all
•zeros 漂移and
• Drift– – counts up sequentially all ones with a full-scale input. Straight Binary is a digital coding scheme
for unipolar voltages only. The representation of 0V is equal to a digital (0000, for a -bit system). The
见增益误差 Seefull-scale
analog Gain . Error.
–LSB digital representation is equal to (). With this code, there is no digital
representation
Unipolar Straight
单级直接二进制码 for (USB):
analog
Binaryfull-scale.
Code (USB):
从电压最小的输入开始 See With
Tablethe
.
，lowest input voltage, the digital，count
数字的编码从全为零开始增加 begins with all
数值持续增长到满量程输
zeros and counts up sequentially all
入。直接二进制编码是只用于单级电源的数字编码。0V电压用数字0000（(1)对于一个ones with a full-scale input. Straight Binary is a digital coding scheme
(2) 4-bit的系统）表示，比满
for unipolar voltages only. The Table 7. Unipolar
representation Straight
of 0V is equalBinary Code(0000,
to a digital for a -bit system). The
量程值小 1个最低有效位
analogMNEMONIC
full-scale –LSBLSB 的模拟电压所对应的数字是
digital
DIGITALrepresentation
CODE is equal 1111.这样就没有对应模拟满量程值的数字值了
VTR–to (). With this code, there is no digital
VCODE VTR+
。见表7.
representation for analog full-scale. See Table .
Zero 0000 — 0.000 0.
+VLSB 000
Table 7. Unipolar 0. Binary
Straight
表7. 单级直接二进制码 (1)(2)
Code 0.
(1) (2) 0.
000 0. .0 .
MNEMONIC 00CODE
DIGITAL .
VTR– .
VCODE .
VTR+
/ FSR
Zero 000
0000 .
— .00
0.000 .
0.
+VLSB 00
000 .
0. .
0. .
0.
00
000 .
0. .0 .0
.
0
00 .0
. . .
/ FSR 000
000 . .000
.00 .
00
00 . . .
00
00 . .0 .
.0
0
0 .
.0 . .
/ FSR 00
000 . .00
.000 .
0
00 . . .
0
00 . .0 .0
.
+FS 0
.
.0 .
. .
—
/ FSR 00 . .00 .
() 0 . . .
Also known as straight binary; FS = 0V.
() 0VTR+ = upper code transition
. voltage; VCODE = (digital
.0 code)0 × VLSB, VTR+.0
VTR– = lower code transition voltage; = VCODE +
(/)VLSB
+FS ; VTR– = VCODE – (/)V LSB
. .0 . —
(1)
() 也叫做直接二进制码， FS = 10V.
Also known as straight binary; FS = 0V.
(2)
() VTR– = 下转换电压码元; VTR+ = 上转换电压码元; VCODE = (码元)10×VLSB, VTR+ = VCODE +(1/2)VLSB; VTR– = VCODE – (1/2)VLSB.
VTR– = lower code transition voltage; VTR+ = upper code transition voltage; VCODE = (digital code)0 × VLSB, VTR+ = VCODE +

2008
0 A Glossary of Analog-to-Digital Specifications and Performance Characteristics SBAAA – August 00 – Revised January
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参考
参考电压（也叫做模拟参考电压）：这个参考电压决定了模拟输入的范围。对于给定器件的实际模拟输入范
围，请参考产品的资料单。这个电压源可以是A/D转换器内置的或者外接的。
• 参考误差–
参考误差是实际参考电压值(VREFP – VREFM) 或VREF偏离理想状态的数值。参考电压的单位一般用百分比或电压
绝对值来表示。
零域误差(或零码误差): 见偏置误差(单级).
参考文献：
• 下面的文献都可以从德州仪器(TI)的网站上(www.ti.com)下载，不能被下载的文献会特殊标明。
• Albanus, J. (2000.). Coding schemes used with data converters. Application report SBAA042.
• Anonymous. (1995.) Understanding data converters. Application report SLAA013.
• Baker, B. (2005.). A Baker's Dozen: Real analog solutions for digital designers. Burlington, MA:
Elsevier/Newnes.
• Institute of Electrical and Electronics Engineers, Inc. (2001.). IEEE STD-1241-2000: IEEE Standard for
Terminology and Test Methods for Analog-to-Digital Converters. Available at IEEE.org.
• Oljaca, M. and Hendrick, T. (2004.). Data converters for industrial power measurement. Application
report SBAA117.

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可访问以下 URL 地址以获取有关其它 TI 产品和应用解决方案的信息：
产品
放大器 http://www.ti.com.cn/amplifiers
数据转换器 http://www.ti.com.cn/dataconverters
DSP http://www.ti.com.cn/dsp
接口 http://www.ti.com.cn/interface
逻辑 http://www.ti.com.cn/logic
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微控制器 http://www.ti.com.cn/microcontrollers
应用
音频 http://www.ti.com.cn/audio
汽车 http://www.ti.com.cn/automotive
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数字控制 http://www.ti.com.cn/control
光纤网络 http://www.ti.com.cn/opticalnetwork
安全 http://www.ti.com.cn/security
电话 http://www.ti.com.cn/telecom
视频与成像 http://www.ti.com.cn/video
无线 http://www.ti.com.cn/wireless
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Glossary of Terms

A Glossary of Analog-to-Digital Specifications and

Data Data Data

Hold Sample Hold

 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008

50% 100% Center�of�code�width

Glossary of Terms www.ti.com

MNEMONIC DIGITAL CODE VTR– VCODE VTR+

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 

10 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008

Passband Transition Stop�band Frequency (Hz)

Figure 8. Key Analog and Digital Filter Design Parameters

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 11

12 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 00

Analog Input Voltage

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 13

�20 (8192�point�FFT,�FIN =�10.0022kHz, C.�Signal-to-Noise�Ratio�= �85dB

Table表6.6.Relationship Between Crest Factor, Digital

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 15

111 Full-scale range =

Analog Input Voltage

Figure 13. Integral Nonlinearity Error

Figure 15. First-Order Modulator Segment

Noise Power (NPR):

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 21

Glossary of Terms www.ti.com

NOTE: In this graph,

22 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008

过量采样：一个过量采样的转换器，它的A/D采样率工作在一个远高于被转换的模拟信号的带宽频率 Glossary of Terms

Passband Transition Stop�band Frequency (Hz)

Figure 20. Key

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 23

Latch n Latch n-i

Digital Error Correction and Output Latch

Bit�1,�MSB Bit i Bit n,�LSB

Figure 21. Pipeline

Pipeline Delay (Latency): see Latency, pipeline.

24 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008

 A Glossary of Analog-to-Digital Specifications and Performance Characteristics Submit

ZHCA068-August 2006-Revised January 2008 SBAAA – August 00 – 术语词汇表

Figure 22. Successive Approximation

28 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008

Figure 23. Total HarmonicFFT

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 29

30 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 00

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点 31

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 2008

ZHCA068-August 2006-Revised January 2008 术语词汇表：模数转换的规格和性能特点

12 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 00

A Glossary of Analog-to-Digital Specifications and Performance Characteristics Submit

ZHCA068-August 2006-Revised January 2008 SBAAA – August 00 – 术语词汇表

30 术语词汇表：模数转换的规格和性能特点 ZHCA068-August 2006-Revised January 00