FP 32

Multiplication and Electronics and

communication Dept.
Addition in 221EC3354
Salonee M Satute
pipelined
environment
Aim of the project
• To achieve the timing analysis of whole combinational logic

FP Multiplication FF1 FF2 FF3

Fig1. Timing analysis resolved by cascading the FFs

• Fig 3 : Reference for adding delays from vlsi-
expertsite
Problem of adding FFs

• FP multiplication and addition has input as numbers in floating point and

output as multiplication/addition of that numbers.
• But at its output side, back-to-back flip flop must be added for avoiding
timing issues.
• This structure creates problem after synthesis
• Formal verification is done between RTL and Netlist.
• But netlist dose not match with RTL because of cascaded flip flops
Solution of previous problem
• Flip flops to be pipelined
• Pipelined structure will occur in simulation and netlist.
• Formal verification between synthesis and RTL done successfully
• C model(design verification program) to be written to be verified with
RTL(of pipelined flip flop structure)

FP MULT FF FP MULT FF FP MULT FF

Fig 2 Solution Diagram – Pipelined Structure

Pipelined Structure
0 pipeline
Combinational Logic

Combinational Logic Combinational Logic 1 pipeline

Combinational Logic Combinational Logic Combinational Logic 2 pipeline

Combinational Logic Combinational Logic Combinational Logic Combinational Logic 3 pipeline

Formal Verification of pipelined structure

FP MULT FF FP MULT FF FP MULT FF

Formal verification

C Model
Following algorithms to be followed:

• Dadda Algorithm
• Karatsuba Algorithm
• Urdhva-Tiryagbhyam Algorithm
• Trojan Models
Basic Algorithm
for C/RTL
implementation
Future scope

Posit number system to be introduced in this project

Posit number system has more precision than IEEE 754 number
system
ML design work mostly between -1 to 1. It works more efficient in
Posit number system