Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity seg7anodechung is

Port ( I : in STD_LOGIC_VECTOR (3 downto 0);

SEG : out STD_LOGIC_VECTOR (6 downto 0));

end seg7anodechung;

architecture Behavioral of seg7anodechung is

begin

SEG <= "1000000" when I = "0000" else --0

"1111001" when I = "0001" else --1

"0100101" when I = "0010" else --2

"0110000" when I = "0011" else --3

"0011001" when I = "0100" else --4

"0010010" when I = "0101" else --5

"0000010" when I = "0110" else --6

 "1111000" when I = "0111" else --7

"0000000" when I = "1000" else --8

"0010000" when I = "1001" else --9

"0001000" when I = "1010" else --A

"0000011" when I = "1011" else --B

"1000110" when I = "1100" else --C

"0100001" when I = "1101" else --D

"0000110" when I = "1110" else --E

"0001110"; --F

end Behavioral;

file tb:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity seg7anodechungtb is

end seg7anodechungtb;

architecture Behavioral of seg7anodechungtb is

component seg7anodechung

Port ( I : in STD_LOGIC_VECTOR (3 downto 0);

SEG : out STD_LOGIC_VECTOR (6 downto 0));

end component ;

signal I : std_logic_vector(3 downto 0) := (others => '0');

signal SEG : std_logic_vector( 6 downto 0);

begin

uut: seg7anodechung port map (

I => I,
SEG => SEG );

stim_proc: process

begin

I <= "0000";

wait for 5 ns;

I <= "0001";

wait for 5 ns;

I <= "0010";

wait for 5 ns;

I <= "0011";

wait for 5 ns;

I <= "0100";

wait for 5 ns;

I <= "0101";

wait for 5 ns;

I <= "0110";

wait for 5 ns;

I <= "0111";

wait for 5 ns;

I <= "1000";

wait for 5 ns;

I <= "1001";

wait for 5 ns;

I <= "1010";

wait for 5 ns;

I <= "1011";

wait for 5 ns;

 I <= "1100";

wait for 5 ns;

I <= "1101";

wait for 5 ns;

I <= "1110";

wait for 5 ns;

I <= "1111";

wait for 5 ns;

wait;

end process;

end behavioral ;