DESIGN

CIRCUTS &LOGIC
circuit
DIGITAL basically s combinanonal
logic

A emiconductor
Read OmlyMemory 6) a

ofthese
eiemens one
memry (
(a
set
offip-hop
crruit wich flip-fiop
sad gaes
(d)all of the above
3 seqaoal
c specified by
PLA K (c)
the
Number of ouiptrS

12The size of the ib} Namber of inputs then the

bipoiar
memoreS have

pruduT t e r z e s memories
TOt with bipoBar a m e and
are cheaper
access
compared
ben
HOS memories (b) faster but are cheaper
ime
and are costty
tE} SSower a c S s
ime
(d)slower access
(c) faster access üme and art costi

14 Which one of the following

semaconductor RAM
is a volatile memory

(6) semiconductor ROM

(c) femite core
(d) none of the above
S AVD & DIA
a
15. Programmable logic
(a) ROM marices
16. The Read Only Memory
PLA make use of
(6) RAM matrices

consists of
(b)
(c)

a
PROM mamces

decoder followed by an
(d) Silo memory

encoder
CONVERTERSS
(a) A mulapierer followed by
a decoder
(d) None of
these 11.0 INTRODUCTION
ic} an by a decoder
encoder folloued It is important for a system to convert the available signal into digital form and vice-versa.
17. PAL consists of the following matrix
OR matix There are basic two types of converters named A/D converter and D/A converter.
(a) Fixed AND m2trix and a programmable as
OR matrix
b) Programmable AND matrix anda fixed
(d Both AND and OR matrix
are programmable The process of conversion from an analog signal to digital signal is referred to as
(c) Both AND and OR matrix are fixed
(ADC or A/D converter an Analog to Digital Converter.
18. The refreshing cyce is required by the memory
(c) RAM1 (d) All of these Whenever, the output of the system
(b) Dynamic MODs
a I ROM required to be in analog form then the digital inputs are fed to D/A converter to
back the original analog signal. For this get
19. Dynanic menory cells are constructed using purpose Digital to Analog Converter (DAC or D/A Converter) is used.
(b) Transistors (c) FET's (d) Flip-Flops
fa) MOSFETS
20. Semiconductor memories are 11.1 DIGITAL TO ANALOG (D/A) CONVERTERSS
a) volatile and smaller in size (b) volatile and larger in size
(d) non-volatile and smaller in size Types of DIA converters are
c) non-volatile and larger in size
1.
Binary Weighted Resistance D/A converter
ANSWERSs 2. R-2R Ladder D/A converter
1. d 2 (6) 3.(c) 4.(a) 5. (b) 6. (a) 7.(4 . (a)
9. 610. (d
iL. (o) 12 (4 13.0 14.(b) 15.6 16(6) 17. (6) 18. ( 19. ()20. (a 11.1.1 Binary Weighted Resistance D/A Converter
Functional block diagram of
binary weighted resistance DAC for 3-bit input data is as shown in fig.
oosUPPLEMENTARY PROBLEMS 11.1.

1. Give classification of
semiconductor memories. 20LSB)
2. Differentiate RAM and ROM semiconductor memories.
3. Explain EPROM and EEPROM memories. Why they are called
Digital
Inputs
- Resistance
Divider Analog
4.
as erasable memories ? Output
Compare SRAM and DRAM. 2 Circuit
5. Explain
memory cell in detail. (MSB)
6. Explain read/write
cycles for RAM with suitable
7. Write timing waveforms.
short notes on (a) PLA Fig. 11.1 Functional block diagram of Binary
8. Obtain a
(b) PAL (c) FPGA.
memory of size 16 x 2 using 4 x 2 size of
Weighted D/A Converter.
9. Differentiate PLA
and PAL. memory IC's or
chips.
10. Write short notes on
(a) Masked ROM. (b) PROM.
843
 DESIGN
& LOGIC A/D AND D/A
DIGITAL
CIRCUITS
analog
oupuis
Let us take an example cONVERTERS
844 digital inputs
and their corresponding
. Snows
TABLE 11.1 M$B LSB 845
Analog Outputs If digital input is 001 i.e, V,V,V,= 001
Digital Inputs Let us assume
logic 0 0V
+1V and
logic l = +7V
0
+2V Its equivalant circuit is as shown in fig. 11.3.
+3V
+4V
0
+5V 2
V=1
+6V OV
1
+7V.
outputs
Table 1. Shows digital inputs and
their corTesponding
of 001 the output wil
0V and I=+7V. Now, for an input
-R R
100 w l l provide an output of+4V, The
are 0 =
that the digital input levels
Let us assunme

of O10 will provide an output of +2V,

and an input of
digital
umiary, an input signals 001 and 010.
1nput 011 is seen to be a
combination of desired +3V output for the 011 input is achi.
bit is added to the +2V
from the 2 bit, the chieved.
f the +1V from the 20shown in table. 11.1.
VA
Desired output levels are into an equivalent-
two things in orderto
change the digital input analog
hus,the resistive divider circuit must do
output volitage.
L The 2 bit must be changed to +1V and 2
bit must be changed
to +2V, and 2* bit must be changed to + 4V RR
must be summed together to form the analog output
2 These three voltages represents the digital bits and they
oltage.
is shown in fig. 11.2 for a 3-bit digital input.
is internal structure as

Flg. 11.3 Equlvalent clrcult of Binary

Digital Inputs Welghted Resletance D/A Converter for glven
2 0 According to Millman's theorem input (001)2:
(MSB) LSB)
V/R+VR,/2)+V, R,14)
1/R +1/(Ro/2)+1/(R4) 6:Vo+7 V, V, =V2=0V

Analog Output (VA) 1/R+0+0 +1v

RRo R R Ro
So, the output is analog+ 1V.
It will be more clear if we consider
another data.
If the digital data is 011, we have
Flg. 11.2 Internal structure of Binary Weighted Resistance D/A Converter.
logic 0 = 0V
It can be solved by using Milman's theorem.
According to Millman's theorem equation is given by logic 1= 47V [Assumed dataj

VR1/R/B,+V, /R,+V,/R,
+1R +1/R +1/R, t..
 DESIGN
CIRCUITS & LOGIC D AND D/A
344 801e 11.I shows
DIGITAL
digital inputs
and
corresponding
their
analog ouputs

TABLE11.11
Let us take an example
ONVERTERSS
MSB LSB 845
Analog Outputs If digital input is 001 i.e.,
Digital Inputs
V2V,Vo 01=

OV Let us assume
logic 0=0V
0 +1V and logic 1 = +7v
0
+2V
ts equivalant circuit is as shown in fig. 11.3.
+3V

+4V
+5V
+6V OV OV TN1
+7V.

and their corresponding outputs

Table 1. Shows digital inputs of 001 the output will
=0V and 1t7V.Now,for an input
the digital input levels are 0 L
Let us assume that010 will provide an output of +2V, and an input of l00 will provide an output of +4v. Th
he digital
imlarly, an input of combination
input O1l is seen to be a signals O01 and 010.
of
bit, the desired +3V output for the 011 input is achi.
2
If the +1V from the 20 bit is added to the +2V from the chieved.
Desired output levels are shown in table. 11.1.
the digital input into an equivalent
Thus, the resistive divider circuit must do two things in order to change .

analog
Output voltage.
1. The 20 bit must be changed to +1V and 2 bit must be changed to +2V, and 2 bit must be changed to +d
4V. R>Ro
2. These three voltages represents the digital bits and they must be summed togetner to form the
analog output
put
voltage.
Its internal structure is as shown in fig. 11.2 for a 3-bit digital input.

Digital Inputs Fig. 11.3 Equlvalent circult of Binary

Welghted Reslstance D/A Converter for glven input
2 According to Millman's theorem (001)2
(MSB) LSB)
V. /Rg+V,/R,/2)+V, /R,/4)
1/R+1/R /2)+1/(R /4) (:Vo+7 , V, =V,=0V)

Analog Output (VA)

RLRo
So, the output is analog
+1V.
It will be more clear if we consider another
data.

Fig. 11.2 Internal structure of Binary Weighted Resistance D/A If the digital data is 011, we have
It can be solved
Converter.
by using Millman's theorem. According to Millman's theorem logic 0= OV
equation is given by logic 1 = +7V [Assumed data)
v-/R +V/R+V,/R, +V,/R.************
1/R +1/R +1/R, +1/Rg t..
 DESIGN A/D AND D/A CONVERTERS
CIRCUITS &LOGIC
DIGITAL
fig. 11.+
shown in Vo
Digital fnputs 847
846 lts equivalent
circuit is as
27
+7V= 1
V2
(LSB) (MSB)
OV
2R
-R -RR 2R
2

w-
w-
2R R
B R C R D
A
Analog
Output
Fig. 11.5 Internal structure of R-2R Ladder
R >Ro It uses the formula
digital to analog converter.

VA= V20+V,2 +V,22 +V,2 +

2
Lets take an example
Weighted Resistance DA converter tOr
given input data (0011
01)2 If digital data is 0101 ie., 4-bit data
structure of Binary
Fig. 11.4 Internal Let us assume logic 0 = OV
According to Millman's theorem
logic 1 = +16V
(:2 = 16 for 4-bit)
VR+VRg/2)+ V, (R4) (: Vo=+7 V, V, =+7V, V2=0V) LSB MSB
Digital Inputs = 0101
Ro R/2) R/4)

7R+7/R/2) +0
2 2
R Ro R n= Number of bits.
Here, n =
4(as data is 4-bit)
2R 2R 2R 2R
. . ww
2R A
w-
R B R R VA
D
Analog
Output
Thus, analog output is +3V.
VA VoX2+V2+V,2 +V216x1+0x2+16x4+0x8 16+64 80
16 1 6 5V
11.1.1.1 Drawbacks or Disadvantages of Binary Weighted Resistance D/A Converter Thus, the analog output is +5V.
2 16
There are two drawbacks of resistive divider or binary weighted resistance D/A converter
Similarly, if the given data is 1000, we get
1. Each resistor in the network have a different value.
2. More resistors are used thus much greater currents are needed. 0x20 +0x2 +0x2 +16x22 16x8
VA= 2*
gv
For Example
Thus, analog output is 8V for binary 1000.
In 10-bit system, the current through the MSB resistor is approximately 500 times as large as the current through LSB
resistor.
Due to these drawbacks second types of resistive network is used called
11.1.3 Performance Characteristice of D/A Converters
as 'R-2R ladder' network 1.
Resolution Resolution is the reciprocal of the number of discrete steps in the D/A outputs. Thus, resolauion
:

11.1.2 R-2R Ladder D/A Converter depends the number of bits in digital system. It is given by following equation
on a

It overcomes the drawbacks of resistive network in which

different values of resistances are used. R-2R ladder maxe
use of only two values of resistor i.e. R and 2R. It is as shown in
fig. 11.5 for a 4-bit digital input. R where, N= Number ofbits.
 DESIGN
IRCUITS &LOGIC AD AND D/A CONVERTER
DIGITAL
4 Maximum deviaion is specifñed by linearity which is
gvesdy *R=- LSB 49
Prenesànce s LSB =Resolution is Volts =0.1 V
i epected oupuL. 1
pertena
s
e n as a
a i o n is 5V and accurac)Y iS £0.1th Therefore.
LSB= 0.05 V
hd be eter than 0.5 of LSR
mkiealy
aruy Thus, Range = 2.84 0.05 V
a S Vor
errs a =

5.Quantization eror is givea by

A 1x *uay
sheuk be better than 0.2

r 0 tf fill a e .
aoverner iSB s ideal
ir
aevener spaiies
the axuay
wruh w t x h the perfoDma

erease) QE
LSB 0.05 0.0
63 0.00079
The ineariy afe in the
earity: analos 2-1 26-1
ener hen LSB. %QE =0.079
e mean shuid de st ieast aquai
w or
I11.2 ANALOG TO DIGTAL (AD)
e g Time: Wieever a ága nput is
apd h DiA TT.
TIEATES
a vahs
OUEput to
value within some
sets a
Types of AD converters are: CONVERTERS
r ss Iis paraTeter telis the speed of D/A cOns
1. Simultaneous or Flash or
init range is -LSB and Parallel Comparator A/D converter
h ofhe sins valae The 2 Continuous Counter AD (Parallel A/D converter).
of switches ampifier.
esisaors etc. in the
devac Converter or Up/Down Counter AD converter
*kuistai by ae 65 . It meets 3. Single slope A/D converter. (Counter tpe AD
EAMPLE 1.i A 6-bit R-2R iadder DA
caaverter has reference voltage
of standard in
4. Dual slope A/D converter.
converter)
2 Ful Scale voltage 3. Output for 011100
Caleuiaie 1. Resalution in Vols and Pervrentage
5. Seccessive
4 Range in output for (
5 Quantization error
approximation A/D converter.
11.2.1 Simultaneous or Flash or Parallel
SOLUTION: 1 Resolution = The Comparator AD Converter
procesS of converting analog
conversion is simultaneous method. Forvoltage digital is known as A/D conversion. The simpiest method used for its
to
this simultaneous A/D converter is
FResolution x100=X100 or
R 1.578 % It
consists number of operational amplifiers. For three bit (i.e.. usedd
of
6 for 6-bit) N= number of possible
combinations. (from formula 2 N, ie., numberK,of bits
Thus, for 3-bit we have 2° 8.
=
n =
X1 Xg). (N- 1) op-amps are used.
and N=number Where,
Resoluion in Volts =R= =01IV =
Hence, (8-1) 7 op-amps are used.
= of possible combinations)
There is one reference voltage which is
different for different op-amps. The
Op-amp as a
comparator is used here.
to get the
output of op-amp. For
simplicity analog and reference voitages are
difference starting from compared
reference
Ful scale voitage (FSV) 1sgiven by FSV=V2e 6.5 =6.5x=6398=6 example, for 1 op-amp V,=reference voltage 0.5V, voltages
=
are in the slot of 1V
for 20d op-amp 0.SV. For
2 If the analog signal is less than V,= 1.5V, for 3 op-amp
3 Output for 011100 is given by 0.5V, comparator outputs are '0'. If the V,=2.5V and so on.
0.5V but less than 1.5V, than the 1* analog signal is equal to 0.5V and geater than
comparator is
coresponding comparator outputs and digital output High are asothers
and are Low.
Similarly, the range of analog inputs,
or binary inputs shown in table l1.2.

TABLE 11.2
Here, data is Analog Inputs
0 Comparator Outputs Binary Outputs
Vs (Volts)
MSB V V V V o LSB
th 6th 5th 4th 3rd 2nd st
Vs <0.5 0
and 0.5 Vs< 1,5
n=6 (for
six bit data) Or, Vout 0+0+1x22+1x23 +1x24+0
2 1.5 s Vs<2.5 0 0 0
Here. 0
Logic l= +6.5 V
[Because, reference voltage V, = 6.5 V] 2.5 Vs<3.5 0 0
Logic 0 = 0 Vv
3.5 s Vs <4.5
6.5x 2+6.5x2+6.5x24 4.5s Vs «5.5 0
64
also, S.5Vs<6.5
o65284 v Vs2 6.5
 DESIGN
&1OGIC erene vo S
CRCUITS
then itit is take as
v, then ADAND DA ERTERS
in
DIGITAL than

I, *,"
FRIRT
and
and thuN,
ihus, giv¢s the
"' i is clear frm the figrwre 18
gees
ivw i
V
wth
etceKe
alage
oni t
vaPsli vtage
gl
th*wigt

V, 4Etage*
Y(Outpu)
V
Comparator with ,and
V,voltages.
sv
11.6 faAWInE pOInis
F The tahle gives
can hr iengnd
i e
art hagrun

sv

v,V
Coaverter is as shown in figure I1.7, svy
E S r Flash or Parallet AD
V,V
sv3sv
V,
sv2sv

v,
svSV

V,V
0.5V
Analog Reference (V)
InputVoltage
V, * 5V
Digital
Outputs

Fig. 11.8 Internal etructure of

From figure 11.8, we get output parallat AD conserter fo anakog input
X, X, X, 30t voltage V,5
Thus, V,5V =(01
0.5V 11.2.2 Continuous Counter AD Coeverter
Analog Reference It make use of D/A
fer u down Counter AD Coaverte
Input (V) Voltage (V,) converter in it Te maun
coengnens of his cunverter ane
Voltage 1. D/A converter
Fig. 11.7 Internal structure of parallel A/D 2. Comparator
Lets take an exarnple Converter
Let V,
analog Input 5SV
=
3. Up-down counter
The output shouid be
10i in
digital 4. Control unit and

5. Latches.
 &LOGIC
DESIGN AD AND DIA
DIGITAL CIRCUITS If the input is constant, the counter
cOunt, the reference voltage V,becomes a
backs down on count
hewn c
CONVERTERS
when a
852 It 1s as shown in figure 11.9 comparison
s to up again. So, f the input 18 a bit less than analog output voltageV the takes place. Due to this backing 853
Analog
constant, this back and forth action ,
comparator output
down on
Control
output waveforms. goes
continuous and due to which we High anai count
e
nput
Logic EXAMPLE
calculate:
11.2 A counter type AD
converter contalns a 4' blt
get such type or
binary ladder and ls driven
V, Comparator 1. Conversion time and converslon rate. by a 2MHz cdock,
2. Resolution.
Up Down Command
Command Clock IVis relerence voltage for ladder network and is 2V.
Reference sOLUTION:
Voltage
Do Conversion time 2
D/A
Converters
D
D2-
Q1 Up/Down
Counter
1.
t)=
ses
Clock rate 2x1068sec
Conversion rate = =
D3 - t10-=125x10f conversions/se
Resolution = S
2-1
FSVFull Scale voltage)
FSV 22-1)_2x15 =1,875V
Latches
(Because, n=4)
Resolution, R =85,1875_
2"-1 150.125V

112.3 Single Slope AD Converter

Digital Output
It does not required a DIA converter. It
Rg. 11.9 Black diagram of counter type AD converter. as shown in figure 11.11.
uses a linear
ramp generator to produce a constant slope reference
The analog input which is to be viewed as digital is given to the comparator i.e. op-amp at its non-inverting input. The voltage. It is
output of D/A converter is the reference voltage V, which is to be compared with the analog input at
reference voltage V, is less than the
V; comparator. If the
analog input V, i.e. V, <V, the output of comparator goes High i.e. "1' and due to
which the counter is in
up mode via control logic. Thus, the counter gives the binary counts and an analog reference
ia obtained from the D/A
converter which is then output
compared with the analog voltage Vi, Whenever, the V, i.e. reference D |Digital
voltage becomes equal to V, i.e. analog voltage then the Latches
output of comparator goes Low i.e. '0 and the counter comes
down mode
through control logic. If the analog input is increasing then the counter starts in the D,| Outputs
decreasing, the counter continues to count back i.e. down. It is as shown in counting up and if input is Ramp Dtor 4bits)
figure 11.10. Generator
12+ Continuous
T Analog Signal
10+
Ramp
Control

Time () Logic
Magnitude D/A Converter Output op-amp as
Comparator
Clear
Counter

Analog Clock
Input
Fig. 11.10 Input-output Time ()
waveforms for counter type A/D converter lg. 11.11 Black diagram of single slope AD converter
 apacitor in the feDA CONVERTERS
he integraung
op-anp uses a
DESIGN The

& LOGIC voltage of in

CIRCUITS

Output ing op-amp is elback path as

DIGITAL
given by ^ clearly shown
s in
855
Tts main components are
3. Counter figure
2. Comparator 6. Latches
volts. So, the i.
1. Ramp Generator
5. Control Logic and ramp
generator ouput 1s
zero

comparator. "
nput the output voltage is inteos
4. AND gate is used) output romthe
is 0000(if 4-bit Thus,
..is varying we get a analogsinput voltage. If
a High becas0
initially i.e. output and gives ANLD gate is used
is at this point
reset
Counter reference voltage V, the ramp
generator. If
starts e d ramp. Vin
xedhe utput of integrator be zenroramp fixed as well
AND
8 greater than
the counter and Or tne input
to gate goes
geV clock to the Because any
ell as W e get anoutput-Vin which is a
outp
the
comparator
enables the
clock will be
disabled and
counter stops.
and
Ltt Voltage Vin 1S appliea through initially t variable slope at its output
goes Low the
eaches a specified count, it willelectronic
it equals the analoo
nparator output input, hC suiteh
i n c r e a s e until

output will be Low. 1V/ms. Ramp

output will Teset
switch S, we i.e. starts from
oet Sarts 0000 (for 4-bit counter). A positive
assume that the slope ofthe
ramp
generator is
is stored in
the latches by
control logic.
througn
Ne hen -Nis Swicnes. At this
instant the gain and the cortr counieT)..
ut and the counter starts counting. When
Let us and the counter output that the
ramp is also 4V andd hhas
l s point the ramp is reset
a Let assume that the analog voltage V be 4V at the point of compar+son. Thismeans
ciock reguency
is 100 KHz, 400 C Connecied
amplifier
integrating amplifier 1s
tne
is now aa capacitor C starts
gc switches to the
negative reference voltage
for 4ms. r
the
positive starts discharging linearly due to constant ci to analog input
dischargine oge-V proportional
citor discharges, the positve fixed slope ramp
us has been Hígh counter is in the
for 4ms. As the comparator output At the
point
or
compaison the
from reset which starts at-V.
the counter number can be displayed as 4V. This cone counter starts
Deen running
have been allowed to pass through
the gate to reach
oncept
this binary e comparator
puuses and decoding, ouput becomes Low and it disahiee state, when the
Inary state representing 400.
With proper scaling
digital outpuVoltage
ined from latches. This cool t
mtout can be obtained When output of integrator becomes zero due
b eons and the
1S used in digital voltmeters.
analog input Vin orV. completes oneLthrough AND gate. Thus, the counter
conversion cycle.
c The binary count is
stops tne
11.2.4 Dual Slope AD Converter A/D
proportio
it is free from the
noise which is not
overcome by single slope converter
2.5 Successive Approximation AD
Dual slope A/D convertoris used because
called dual slope because it uses a fixed slope as well
ell as
as
Ttis the most widely used A/D convertor. It has t nverter
It uses op-amp as integrator amplifier for ramp
generator. It is
onversion time. Forn-bit
n-bit A/D
s functional blocks of successiven-sicceoeti
variable slope ramp. It is as shown in figure l1.12. shorter converter n-successive Ythan the digital ramp AD converter but it has much
steps are required for
approximation AD completir
Heting the approxination process.
Integrator Unit Gain 1. Comparator
Convertor (Binary ladderconverter
2. D/A
be
are

Analoge- Amplifier as a Comparator 3. Control Logic 4. Successive may used)

R
Input www- SAR consists of flip-tlops and level amplifiers.Aproximation Register (SAR)
V;=Vin Integrating8 It is as shown in
figure 11.13.
Amplifier Analog Input Voltage
Vref Electronic
Reference Electronic
Switch Control
Voltage
Logic V, Control Logic
(Reference| Comparator
Voltage) CLK

S- R
Counter Flip Flops Flip Flops
are USed

Clock
SAR

Level Amplifiers
Latches

TIIT
D3 D2 D Do
Latches

Digital outputs
DA Converters
Digital Outputs
Fig. 11.12 Black diagram of Dual Slope A/D
Converter. Approximation Type AD Converter.
Fig. 11.13 Black diagram of Successive
 DESIGN
AD AND DIA
DIGITAL
CIRCUITS
flip-flops.
The output of
&LOGIC
these wen as
as
flip-tlops
are given to level.
amplifi s
tne analog reference
and
2
rence voltage V 6 Performance
11.2.6 Perfo haracteristics of A/D Con CONVERTERS J
856 logic is used to
set
ladder
or reset thenetwork. It gives digital ouputs basic
conditions
. olution :It is defined as the voltage input
change necessary for one bit
857
thento
three
rier which is a binary There are output levels are 2" 1 .
to D/A converter
the flip-flops. 1alog voIage, then MSB (most
voltage, then (most eie significant number
of
change in the output. For n bit ADC, the
resets
logic al than theinputanaiog
converteris less
control
the
y from D/A Resolution =ulscale input
Vie.
reference voltage
bit) is set to '1' by control logic. No.of O/P levels
Full scale P
set to T. 2"- 1
0' and nextbit is tputs from SAR
outputs SAR Example: 10 bit ADC having
V , > V , then
MSB is reset to (zero)
clock to fip-tlops
and we ger ugital
by using an VP voltage range of-10 and +
V, then the control logic
disables the 10V. The resolution is given by
J.
fV,=
latches.
Voltage I/P 10-(-10)_ 20
Let us consider an example for its working reset to zero. 1.e. V, =0.
2 -1 210-1 1023 19.5 mV.
us assume
that the counteriS
is Let V, = 4V and let
+Dit SAR used.
is set to 1, % Resolution= x 100%
Now, V,<V, MSB 2" -1
+0000
(Because, (1000,) (8),1)
=

Output of SAR will be

2-1X100X100
For 4 bits, % Resolution =
6.7%.
1000 15 (Because, n=4)
Now, V,= 8V and V, = 4V (Or)
reset to zero. Resolution may also be defined in two ways
is set and first one
V,>V, next MSB
(a) A DAC that can provide number of different
analog output values is called Resolutions.
0100 For a DAC having n-bits
4V
Now V,=4V and V, =
Resolution 'R' =2".

V,=V (b) A DAC in which the ratio

in digital output 0100.
of change
in output voltage resulting from
bit) at the digital inputs is known as resolution.
a change of 1 LSB (i.e., 1least significant
Clock is disabled by control logic and we get 4V as analog voltage
Consider another example for its working Resolution for n-bit DAC is given by
Let Analog Voltage be V, = 5V and intially V, =0, thus V,< V, First MSB in set to 'l', output of SAR = 1000.
Resolution R= Where, VoFS =Full scale output voltage.
Again, V,=8V and V, = 5V
2-1
V,>V VOES
Ist MSB is reset to '0' and 2nd MSB is set to l', output of SAR = 0100 . Percentage Resolution 6R' =
x100.
Again, V,4V, and V, =5V Input-Output equation can also be obtained for DAC, if the resolution is known, we have
,<V Vo= Resolution x D
Next MSB is set to 1, output of SAR = 0110
where, Vo= Output voltage.
Again, V,=6V, and V, =5V D =Decimal value of the digital input.

3
V,>V
MSB is set to zero and 4h bit is set to '1', output of SAR = 0101. R
RwhereR Resolution. Then, S% Resolution=R
Vo =
*l00 x100
V,=V;=5V
Now clock is disabled by control
logic and output of SAR 0101 is obtained as digital output through latches.
= 2.Accuracy: The
be usefully provided.
accuracy of given ADC ie. amalog to digital converter determines the number of bits which
a can

EXAMPLE 11.3 Find the conversion time & conversion

rate for a successive
having 2MHz clock and a 5-bit binary ladder containing reference approximation AD converter The accuracy of an ADC consists of quantization error system noise etc. Typical vaBues are t 0.02% of the full scale
voltage of 8V. reading.
sOLUTION: For Example: Consider an ADC OR with input range of t 10V. Ifthe accuracy is 0.02% of full scale reading. The
maximum error due to such accuracy limitation is 2mV.
Conversion time e) Clock rate 2x10° (Or)
Accuracy may also be defined as the diference berween the actunl analog output and the expected analog o .
Because t=2.5 sec. percentage. In ideal case the accuracy of DAC should be ar
warst
given digital input in applied. Itis expressed
in
when a

1
Conversion rate = t o f its LSB.
2.5x10-6
4x 10° Conversion u sec.
Accuracy 202" -1)
 D
cycles isgND DA
DIA COONVERTERS
CIRCUITS & LOGIC
DESIGN frequency
of the integration AND
858
DIGITAL
It is the time
refers to the
time requires
IOr a complete
easurment by analog
measurment k
The
by
version Time
to digital converter.
or Setting Time :
(Or)
f 859
equivalent. It is ent on the
dependent integrator time constant "t and
It is t required for conversion of analog
signal into its digital amplifiers ere,
a n d .

Such a comparator is able to h are constants and

ume P handle e
o

output and switches response imDe. determines the r a l . will beseen that
GE TO TIME CONVERTER unipolar analog signals.
input

line'. Linearnty of converter direcuy

a
a 'best staraight
ve
4.
Linearity: Linearity is basically of errors betweens the nominal and actual ratios to the full scale anal
VOLTAGE

output fredue is proporional to

calibration. The linearity error should be alue
L14
aCeuracy of the converter. It is the
difference
and independent of full
scale
Converter,
The Voltage to ume Converter,.
Esponding to a given digital input
e single slope and dual cOnveris the input analog
examples are.

slope ramp voltage or carent

comverters. (Already
discussed inlevel
CaTent level into an
LSB.
5. Stability : When all the parameters such as gain, linearity eror, monotonicity and offset must be specified
the stability or the converter.
d over L5 CLIPPING AND CLAMPING CIRCUITS accurate time duraion s
acCr
aricles 11.2.3. ang1124.)
1.

e pOwer suppiy ranges and full temperature then these parameters represent 11.5.1 Clipping Circuits
6. Monotonicity : The output of AD convertor should not decrease or skip at any point tor a continuously increac

input signal. It is known as monotonicity of A/D convertor.

When a porion of the input
signal voltage above
called as
rc i t the amplitmdecipping circuut below certain level is
or
a
(Or) or cippe. Soch circuits
a

used in digtal clipped

or n
not miss any step backward during its entire range stepped by
a counter, then it is etc. 1 or ne
nput signal voltage as required inaresach
fa
converter does said to ve a amplitude
a5 limiter or a
imier. Tbe computers, raaio
converter having good monolonicity. also
(a) Positive clipper
application cipping crcut
cipping circuits are of basic two
types:
11.3It isVOLTAGE TO FREQUENCY CONVERTER
as shown in figure 11.14
(b) Negative clipper
1.5.1.1 Positive Clipper

Comparator clipper circuit is as shown in fig.

consists of a diode 11.15. The
outputis taken across
Ro It in) and resistor
a (Rg). Tbe diode acts as an ideal V-TR
itch between the sourc and the load. Diode in
(D
acts as a closed
switch,
when the input voltage Deganve (L, <0)
iS
V and as an
open switch whea the
AND
Integerator input voltage is posiuve zero
or (Le.,
current through diode, When it acts asVinz0).
Comparator gate Counter The resistor (Ris to limit the
closed switch.
Clk-
Working:
Vref During the positive half cycle of the input voltage, the terminal '" is
Rg.11.15 Crcult of Positive Clipper
the diode and acts
positive with respect to "b. Thus, it reverse
biases (Din) it as an open
switch. Therefore, there is no output voltage during the positive half cyce Ox
Rg. 11.14 Black diaggram of voltage to frequency Digital Outputs the input voltage as shown in the waveforms of fig. 11.16.
Here the input analog voltage is integrated and fed to a conaverter
aPplied. Wbenever input voitage exceeds comparator. To the comparator, a reference voltage
voltage the comparator changes the state. This Vref
the comparator reference is
be
integrator and the process repeats itself. The resets
+in
output of counter gives the desired integration cycles are counted in a counter for fixed time
duration. The
digital output.
fhe integrator is realized an
by inverting amplifier and has time constant then Input
gven by the output of
integrator at time "t' is voltage Vin

(where= RC, i.e., time constant)

f the Vis the comparator reference

voltage, then the time t = T and is
given by Output Time ()
voltage Vo

Hence -Vo circult.

posittve Cipper
and Output weveiormsfor
Fig. 11.16 Input