Digital System Design

Assignment#3
Batuhan Kenan EREN – B1805.010034
Rüstem ELEÇ – B1805.010026
The 4-bit subtractor Karnaugh map:

ABCD

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

A 4-bit subtractor can be designed using Karnough Map minimization. The Charlie Coleman tool can
be used to model the design using array instantiation.

The output of the subtractor can be expressed as:

Out = A'B'C'D + A'B'C + A'B + A

Which can be implemented using the following Verilog code:

module subtractor(

input [3:0] A,

input [3:0] B,
output [3:0] Out

);

assign Out = A[0] & A[1] & A[2] & A[3]

| A[0] & A[1] & A[2] & ~B[3]

| A[0] & A[1] & ~B[2] & ~B[3]

| A[0] & ~B[1] & ~B[2] & ~B[3];

endmodule