IET Renewable Power Generation

Research Article

Non-pilot protection scheme for multi- ISSN 1752-1416

Received on 25th December 2018
Revised 19th July 2019
terminal VSC–HVDC transmission systems Accepted on 17th September 2019
E-First on 21st November 2019
doi: 10.1049/iet-rpg.2018.6265
www.ietdl.org

Mohammed Elgeziry1, Mahmoud Elsadd2, Nagy Elkalashy2, Tamer Kawady2 , Abdel-Maksoud Taalab2,
Mohamed A. Izzularab2
1Egyptian New and Renewable Energy Authority, Cairo, Egypt
2ElectricalEngineering Department, Minoufiya University, 32511, Shebin El-Kom, Egypt
E-mail: t_kawady@ieee.org

Abstract: High-voltage direct current (HVDC) transmission systems are nowadays ideal candidates for interconnecting
renewable energy resources to the electrical grids. This study presents a communication-less protection scheme for HVDC
transmission systems with a multi-terminal voltage source converter (VSC). The existence of a tie-busbar is also considered,
which represents a challenge for protection selectivity functions without the aid of a communication channel. The proposed
scheme identifies the faulted segment on either a DC busbar or a line segment based on monitoring the calculated rate of
change of the current-to-voltage ratio. This criterion is sensitive to detect the faults as the current increases rapidly in a few
milliseconds, while the voltage decreases in the same time frame remarkably. Once the fault detection criterion is satisfied, the
faulted section can be identified by checking the summation and direction of all branch currents at each busbar individually
without utilising communication links. For investigation purposes, the proposed scheme is tested via a four-terminal HVDC
system with two tie-busbars. Different simulation cases are evaluated with a variety of fault conditions using MATLAB/
SIMULINK. The results corroborate the reliability, security, and efficacy of the proposed protection scheme for multi-terminal
HVDC transmission systems.

1 Introduction the differential concept, overcurrent, undervoltage, or distance

DC transmission systems have many advantages as compared with
conventional AC ones. The parameters of AC transmission lines
raise different technical issues regarding the losses, system
stability, and the limit of the transmitted power over long distances
[1, 2]. Recently, high-voltage direct current (HVDC) systems have
an increasing interest in research studies regarding active and
reactive power control for voltage source converter (VSC)–HVDC
applications. The direction of the power can be reversed by
changing the current direction and maintaining the DC voltage
polarity. It is, therefore, preferable for DC systems as compared
with the conventional line commutated converter HVDC systems.
Hence, VSC-HVDC systems are promising for the world trend
towards maximising the utilisation of green and renewable energy
resources all over the world [3, 4].
The protection schemes of DC systems are more complicated
than the corresponding ones in AC grids owing to different
reasons. Short circuit currents are very high owing to the low
resistance of the DC line segment. Cable capacitance is dominant
during the first few milliseconds yielding a high rising rate of the
fault current. This is unfortunately accompanied by a high
sensitivity of the DC converters to overload conditions. Also,
switching the DC current is more sophisticated as it does not have
zero crossing points. Hence, a suppression mechanism is needed to
dissipate the energy in the DC switching devices [5]. Moreover,
protecting multi-terminal (MT) DC (MTDC) systems is considered
as a challenge, where the control system of the converter stations is
corrupted during the fault and it may not be able to block such
currents. On the other hand, identifying the faulted section and
fault location routines face serious difficulties in MTDC systems
due to the low impedances of DC line segments [6]. The art of
science of protecting MTDC systems was outlined covering
different issues such as the number of terminals, connection
configuration, detection and identification criteria, busbar
protection, fault resistance, communication methodology, and the
response time. The most popular protection techniques of MTDC
systems depend on the voltage (or current) measurement based on
functions using travelling wave propagation theory [7].
The differential algorithm provides accurate fault detection and
perfect selectivity in steady-state cases [8, 9]. It needs a
communication channel between both cable ends, where those
issues regarding communication reliability are still faced [10, 11].
Also, a false decision may be taken due to the currents of the
distributed capacitances, which may adversely affect the relay
performance [12]. In [13], the performance of the contemporary
differential protection is improved by compensating the distributed
capacitive current via utilising low pass filters at the terminals.
However, this method needs >5 ms to clear the solid faults and
larger time for high resistive faults. Moreover, it needs an accurate
determination of the parameters of the line segments to design the
related low pass filters.
Distance protection can be utilised depending on the travelling
wave phenomena as seen in [14]. Owing to the low impedance of
the cables in DC systems, the errors in calculating the short circuit
loop impedance result in significant errors in computing the
distance. Moreover, these difficulties are increased due to the fault
transients resulting from the abrupt frequency changes of DC
systems [15]. Hence, its suitability for large and complex DC
systems as well as for high resistive faults may not be guaranteed
[16].
Other protective functions such as overcurrent and undervoltage
relaying were utilised as well. However, the low line impedance in
MTDC may seriously affect the discrimination of the faulted line
[17]. The derivative of the current or voltage can be used to
enhance the protection speed [18]. However, it may be influenced
by the accompanied fault transients. In [10, 19], fast detection
methodologies for DC line faults were proposed in a time <1 ms. In
[20], a reliable protection scheme was presented for DC line faults
depending on the rate of change of the DC reactor voltage in order
to increase the speed, accuracy, reliability, and robustness of its
performance. Although it detected the DC line faults within 1.4 ms,
it cannot detect busbar ones. In [21], three independent fault
criteria were utilised including the wavelet analysis and voltage

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Fig. 1  Description of a four-terminal HVDC transmission system
(a) Four-terminal meshed HVDC test model, (b) Protection scheme connection at
station busbar B1
amplitude. This makes the protection scheme more reliable and
faster (within 1 ms). Unfortunately, it can detect DC line faults
only.
Travelling wave protection techniques were used for MTDC
utilising various signal processing techniques such as wavelet
transform to identify the characteristics of the reflected (or
received) current and voltage waves at the line terminations [22–
24]. The protection algorithm in [23] proposed a DC line pilot
protection applying a polarity comparison of the initial current
travelling wave, whereas it utilised the current differential theory
for busbar protection. The algorithm can detect the DC line fault
and busbar fault within 3 and 2 ms, respectively. Issues affecting
travelling wave protection were treated in [25] including border
distortion, noises, high resistance ground faults, close-up faults,
transients caused by lightning, and different DC line terminations.
In [26], the presented algorithm detected the line fault using
travelling waves within 6.5 ms. Unfortunately, it did not detect the
busbar faults. Moreover, it suffered from different technical
limitations regarding the sensitivity and the required sampling rate.
High-frequency transients were utilised for MTDC systems with
fast fault detection within 0.1 ms for DC line faults only [27]. It
was based on capturing the related high-frequency components
during the fault with the discrete wavelet transform. It, however,
needed a very high sampling rate. It was also very sensitive to the
fault location, fault inception time, fault resistance, and cable
parameters. In [28], the frequency spectrum was used to detect the
faults in two-terminal DC systems only.
An artificial neural network (ANN) was utilised for protecting
DC systems as well. In [29], ANN techniques were applied with a
low sampling frequency of 10 kHz. The algorithm was tested for
DC line faults in a three-terminal system only needing at least 3.6  satisfied together during fault conditions. Even fast lightning
ms to detect the fault and 4.5 ms for classification. Therefore, the
total fault clearing time reached 8.1 ms in addition to the required
circuit breaker time. Unfortunately, it did not detect busbar faults
as well. Moreover, the ANN methods suffered from the consumed
time for designing and training purposes. Also, the performance of
the trained network was guaranteed only for the pre-selected
system with its own parameters [14].
This study presents a novel primary protection scheme for
MTDC systems to identify and isolate the faulted segment without
3034
a communication channel. The proposed scheme provides the main
protection for busbars and transmission lines based on local
measuring of the busbar voltage and branch currents to calculate
the rate of change of the current–voltage ratio for each branch. The
scheme can discriminate between busbar and line faults
successfully. After the detection stage, the faulted segment is
identified based on the summation and direction of all branch
currents connected to the busbar. As compared with other past
travelling wave-based schemes, the proposed scheme overcomes
its most common problems such as the possible mis-coordination
of the protective devices with the existing of tie-busbars. On the
other hand, the reliability of the proposed scheme is enhanced
remarkably owing to the non-communication operation. Moreover,
its security against mal-operation in transient cases is guaranteed
via two security conditions depending on the sign of the rate of
change of both current and voltage signals. Also, its immunity
against noisy signals is verified with robust three-sample
windowing using a reasonable sampling frequency. This facilitates
its implementation and utilisation in the field successfully. The
proposed scheme is tested with a four-terminal HVDC grid with a
symmetrical monopole configuration with two tie-busbars. A
detailed analysis of different faults and abnormal conditions is
carried out using MATLAB/SIMULINK. The results confirm the
efficacy and practicality of the presented scheme.
2 Proposed protection scheme
The proposed protection function is introduced using a four-busbar
HVDC transmission system (B1, B2, B3, and B4) as well as two
tie-busbars (B5 and B6) as shown in Fig. 1a. As illustrated in
Fig. 1b, DC voltage and current signals are extracted for relaying
computation. A fully solid-state DC circuit breaker (DCCB) is
utilised at each branch. This selected DCCB type is characterised
with an interruption time <1 ms [30]. First, the protection
algorithm for the DC transmission lines and the busbar is
described. Then, the coordination issues due to the existence of the
tie-busbars are clarified.
2.1 Proposed fault detection and faulted segment
identification technique
The flowchart in Fig. 2 illustrates the proposed primary protection
algorithm. At each busbar, the DC voltage and branch currents are
extracted at a sampling frequency of 20 kHz. This sampling
frequency is selected based on the required speed and the aimed
sensitivity of the protection scheme. First, the conductance ‘Ʊ’ is
computed as the ratio of the measured DC current to the DC
voltage (i/v). The rate of change of the conductance (dƱ/dt or
simply d´Ʊ) for each branch is then monitored to detect the fault
occurrence. Once the fault is detected and confirmed with the
concurrent security conditions, the proposed selectivity criterion is
initiated to classify the fault type as a busbar or a line fault. In case
of busbar fault, the protective relay gives a trip order to all DCCBs
to isolate all connected branches with the faulted busbar.
In order to avoid the false tripping during transient cases such
as lightning or switching surges, two different security constraints
are employed combining the sign of both di/dt and dv/dt quantities
to pinpoint the fault cases correctly as illustrated in Table 1. The
calculation of the di/dt and dv/dt quantities is performed similarly
to the calculation of d´Ʊ by applying the three samples moving
average filter. The tripping condition is the only issue when d´Ʊ is
positive exceeding the predetermined threshold level in addition to
a positive di/dt as well as a negative dv/dt value. As illustrated in
the aforementioned table, these security constraints are only
strikes or sudden load variations do not satisfy these constraints.
Both fault detection and identification criteria are described as
follows.
2.1.1 Fault detection criterion: When a fault occurs on a branch
of the MTDC system, the branch current rises quickly in a short
time, while the voltage decreases simultaneously. Accordingly, the
magnitude of the current to voltage ratio (Ʊ) increases as shown in
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Fig. 2  Flowchart of the proposed protection mechanism at busbar B1
Table 1 Tripping selectivity with respect to the adopted
security criteria
Case di/dt sign dv/dt sign d´Ʊ (sign and Action
value)
fault + − +↑ trip
sudden load + − +* none
increasing
sudden load − AV AV none
decreasing
lightning AV + AV none
Sign: + positive sign; − negative sign.
Value: ↑ over the threshold; * lower the threshold.
AV: any value.
Fig. 3a. Consequentially, d´Ʊ increases rapidly as compared with
the rate of change of the current (di/dt) within the first few
milliseconds as shown in Fig. 3b.
For security purposes, calculation of the detection criterion d´Ʊ
is performed by applying a moving averaging filter depending on
the average of three consecutive samples to reduce the undesired
noise. The moving average filter tends to smooth out any rapid
changes in a signal as a form of low pass filtering [31, 32].
According to the selected sampling frequency of 20 kHz, the time
interval for each sample is 50 μs yielding a 150 μs data window.
Based on the recent advances in microprocessors and digital circuit
technologies, this sampling rate is technically applicable. Owing to
the simplified computation burden of the proposed detection
algorithm, the overall detection time does not exceed ∼0.2 ms.
This delay owing to the filtering action is considered suitable for
protecting HVDC systems, as a few milliseconds of time are
available in DC grids for the DCCB to operate after a DC short-
circuit fault [10]. The calculation window (moving window) is
sliding on the wave by a step of one sample as shown in Fig. 3c. At
each time step, the averaging process is performed based on the
recent sample in addition to the last memorised two samples as
described in the windows W3, W4 or W5 in the aforementioned
figure. As soon as the net average amplitude of d´Ʊ exceeds the
IET Renew. Power Gener., 2019, Vol. 13 Iss. 16, pp. 3033-3042
© The Institution of Engineering and Technology 2019
selected threshold value, the detection stage is satisfied. This
detection phase is issued based on the first propagated surge
created by the fault event. Hence, the fault detection process is
completely achieved before the travelling wave reflection stage.
2.1.2 Faulted line identification criterion: Identifying the faulted
branch is based on both the current value and the current direction
as long as the d´Ʊ is positive and over the predetermined threshold.
As seen in (1), the sum of each incoming current Iinis normally
equal to the sum of each outgoing current Iout. This equality is
satisfied during branch faults, where the currents from other
branches are fed into their collecting busbar towards the fault point.
Then, the faulted branch is identified when its current is outgoing
from the busbar and equal to the current summation of the other
branches as described in (2)
∑ Iin = ∑ Iout (1)
N−1
If = ∑ In (2)
n=1
where Ifis the current of the faulted branch, N is the number of
branches connected to the busbar, and Inis the current of the nth
non-faulted branch. This was illustrated in Fig. 4a for a fault at F1
on the line L12 between busbars B1 and B2, where the current IL12
is equal to the sum of other branch currents IL13, IL15, and IS1,
respectively. Then, the installed DCCBs on this faulted branch are
initiated to isolate the fault.
The proposed identification criterion is verified for a double-
circuit transmission line as well. For fault F3 on the line L12-C2 in
Fig. 4b, the current summation criterion remains applicable at the
main busbars B1 and B2 by the currents IL12 and IL21 by the
current sums of Is1 + IL13 + IL15 and Is2 + IL24 + IL26, respectively.
Then, both line circuits should be isolated. In order to isolate the
faulted circuit only, an additional condition is applied for the sub-
busbars (b1 and b2) to identify the faulted circuit precisely. This
can be realised by comparing the currents of both circuits, where
the faulted circuit has higher current levels (IL12-C2 > IL12-C1 and
IL21-C2 > IL21-C1). Circuit 1 only of the line L12 designated by L12-
C2 and L21-C2 can be isolated, while the other circuit remains in
service.
2.2 Faulted busbar identification criterion
Based on Kirchhoff's law, the busbar fault is identified if the
currents of the connected branches to a certain busbar have the
same direction towards the fault. For a fault at F2 in Fig. 4a, all
branch currents IL12, Is1, IL13, and IL15 fed the busbar fault, where
all branch currents were incoming into the faulted busbar. This
criterion is quite sufficient to identify busbar faults correctly.
2.3 Security enhancement against tie-busbar
The existing of a tie-busbar can lead to a mis-coordination between
the installed relays at the connected lines to the tie-busbar under
those faults close to (or on) the tie-busbar. Such faults are
accompanied by different impedance values of the short-circuit
loops from each station to the fault point due to either the
inequality of lines lengths connected to the tie-busbar or the
asymmetry of the installed DC reactors through each short-circuit
loop. F5 and F6 are examples for such fault cases as shown in
Fig. 1a. Then, the relay(s) on other healthy lines connected to the
tie-busbar may incorrectly operate owing to exceeding the
predetermined threshold value of d´Ʊ. Two different solutions are
suggested for avoiding the unwanted tripping of the healthy
segments. First, a forced time delay is maintained for inhibiting the
opening of the lines connected to the tie-busbar from the station
sides (DCCBs 15, 26, 35 and 46 in Fig. 1a). Alternatively, the DC
reactors at the tie-busbar side are redesigned carefully.
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Fig. 3  Comparison of electrical measurements under a fault condition in
time domain
(a) Amplitude of the current, voltage and current to voltage ratio of the faulted line,
(b) Amplitude of the current derivative, voltage derivative and derivative of the
current to voltage ratio of the faulted line, (c) Three samples moving average window
Fig. 4  Currents’ directions under fault conditions
(a) Fault on line L12 and busbar B1, (b) Fault on line L12 in case of the double circuit
configuration
2.3.1 Forced time delay: In this method, the coordination is
achieved by applying a definite delay time for the blocking signal
of the DCCBs of the connected lines to the tie-busbar from the
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station sides. This time delay must be profiled according to the
following constraints:
• The forced delay time must be more than the clearing time of
the fault from the tie-busbar relaying point (i.e. 1.25 ms).
• The forced delay time in addition to the blocking time of the
DCCB of the faulted line must be lower than the delay time of
the backup protection scheme (i.e. 3 ms).
Consequently, a delay time setting of 1.5 ms is quite sufficient for
this target. In spite of the simplicity of this method, it suffers from
the unnecessary delay time for all faults occurred at any point of
the connected lines to the tie-busbar even for those faults occurring
near to the station busbars. To overcome this unnecessary delay
time, increasing the utilised DC reactors at tie-busbar is an efficient
alternative.
2.3.2 Redesigning the DC reactors of tie-busbars: The
selected DC reactors play a role in controlling the rate of current
rise, where increasing the DC reactor decreases the rate of current
rise as illustrated in Fig. 5. This consequently delays the
corresponding fault current to reach the predetermined threshold
level of d´Ʊ at the remote busbar. Hence, the mis-coordination
problem can be eliminated by selecting the DC reactors at the tie-
busbar side to be greater than the corresponding ones at the station
sides of the branches. When a fault occurs close to the tie-busbar,
the calculated d´Ʊ of the healthy lines connected to the tie-busbar
does not reach the threshold level before clearing the fault from the
tie-busbar side. After clearing the fault from the tie-busbar side, the
current distribution is changed, and the summation criterion cannot
be satisfied at all healthy lines. This method is advantageous by
eliminating the unnecessary time delay for isolating the faults at
the connected lines to tie-busbar and far away from the tie-busbar.
Accordingly, this method is utilised with the proposed scheme.
These values are obtained via extensive simulation tests with solid
fault cases which are considered as the worst fault conditions.
Accordingly, the setting procedure is suggested, in which the DC
reactor of the 100 km length branch is found to be 85 mH.
3 Selected simulation system
An HVDC system with four symmetrical monopole VSC stations
with a rating of 400 MVA (±200 kV DC) is selected as a simulation
example as illustrated in Fig. 1. To enhance the continuity of the
system, two tie-busbars (B5 and B6) are considered. The tie-busbar
is involved to let each station connect to the adjacent station by two
different paths: a direct DC line and through the tie-busbar. A
DCCB ‘CB56’ is inserted between B5 and B6 to isolate faults on
B5 or B6 while permitting the other one working. Consequently,
the system is still maintained tied via the healthy one. Stations S1
and S2 operate in the rectification mode and the other two stations
S3 and S4 operate in the inverting mode. The simulated model was
built using the MATLAB/SIMULINK. The VSC stations transmit
power from (or to) a 4000 MVA, 230 kV, 50 Hz AC system. The
rectifiers and inverters are three-level neutral point clamped VSC
converters. All DC line segments were modelled with the
frequency-dependent distributed parameter model in MATLAB
using the parameters in Table 2.
The active and reactive powers are controlled in the
rectification operation mode, where the pole-to-pole DC voltage
and the reactive power are controlled in case of the inverting
operation mode. The minimum DC reactor is calculated based on
the system voltage rating and the operating time of the protection
scheme to clear the fault [10]. It is assumed that the solid-state
DCCB has an operation time of 1 ms and its minimum breaking
capability is 9 kA. The relay response time to detect the fault is
assumed to be 0.2 ms and the time delay of the measuring due to
wave propagation in the longest line is 0.4 ms. Therefore, the
maximum required operation time can be ∼2 ms. Hence, the
maximum rise for the fault current is 4.5 kA/ms. Then, the DC
reactor should be ≥200 kV/4.5 kA/ms. Therefore, a DC reactor of
50 mH is suitable.
IET Renew. Power Gener., 2019, Vol. 13 Iss. 16, pp. 3033-3042
© The Institution of Engineering and Technology 2019
 4.1 Load variation impacts
Investigating the impacts of load variations is essential to
determine the sufficient threshold level of d´Ʊ to avoid false
operation during normal conditions. A sudden increase in the load
from 0.15 to 1.15 p.u. resulted in a maximum value of d´Ʊ of 205 
p.u. as shown in Figs. 6a and b.

4.2 Solid DC fault cases

Fig. 5  DC reactor effect on the rate of change of current When a fault occurs, all stations operate in the rectification mode
and feed the fault resulting in a DC voltage collapse. Cable
Table 2 Four terminals simulated model parameters capacitance impacts the fault current level remarkably, where the
Line Length, km R, Ω/km C, L, transient fault current may sometimes reach more than 5 p.u.
μF/km (mH/km Different fault types such as pole-to-earth or pole-to-pole faults are
considered at different fault locations such as the line fault at F1,
L12 90 0.0139 0.231 0.159
the busbar fault at F6, and at the line fault close to the tie-busbar at
L13, L34 75 F5 as depicted in Fig. 1a.
L15, L26 100
L24 120 4.1.1 Pole-to-earth fault: Fig. 7 illustrates the results of a positive
L35 70 pole-to-earth fault at F1 on the line L12 at the instant of 1.5 s. The
L46 60 AC side has significant changes in the voltages and the currents as
DC ratings 400 MVA, (±200 kV DC), shown in Figs. 7a and b, respectively. The AC voltages are
1 kA decreased first to 20% of their nominal value. Then, they are
AC ratings 4000 MVA, 230 kV, 50 Hz, restored by the control system. The AC currents are increased in all
Short-circuit power 30  phases with 56% of their nominal level. The DC current at station
GVA S1 is increased to 3.2 p.u. as shown in Fig. 7c, which represents a
severe case for semiconductor components. Hence, the protection
DC reactor 50 mH
scheme must detect and isolate such faults rapidly to avoid
base voltage 200 × √2/√3 kV converter damage. The currents in the lines L13 and L15 feeding
base power 400 MVA B1 are increased to 2.3 and 1.36 p.u., respectively, owing to the
base current 400/(200 × √2/√3) kA cable capacitors. This results in a current of 6.8 p.u. through the
L12 line between busbars B1 line L12 to the fault point F1. The aforementioned current levels
and B2 satisfied the summation criterion for identifying the faulted line.
The voltage of the DC bus VDC-B1 is collapsed rapidly as shown in
Fig. 7d. This represents a challenge for MT HVDC systems owing
to their low impedance values. The variation of d´Ʊ of the pole-
earth fault case at F1 of both ends of the faulted line L12 is
illustrated in Figs. 8a and b, respectively, where a significant
increase of d´Ʊ of both B1 and B2 stations (>2000 p.u.) is
recorded. On the other hand, the variation of d´Ʊ for the non-
faulted line L34 did not exceed 284 p.u. for both line-ends as
illustrated in Figs. 8c and d. Similarly, d´Ʊ does not exceed 200 
p.u. for the tie-busbar as shown in Fig. 9.

4.1.2 Pole-to-pole fault: For a pole-to-pole fault at F1 on line

Fig. 6  Response of the proposed scheme to a load change
(a) Load power changes from 0.15 to 1.15 p.u., (b) d´Ʊ values for all branches
connected with B1
However, the refined DC reactors for the connected segments to
the tie-busbar should be computed as a function of their line
lengths. Since long line length has more reduction in the
propagated wave amplitude and sharpness, longer lines need to be
equipped with lower DC reactors with inverse proportional to the
line length. With the suggested setting of an 85 mH reactor for the
100 km line, the values of the DC reactors of L51 and L62 are
considered to be 85 mH as both lines are 100 km as well. Similarly,
the lines L53 and L64 have DC reactors of 120 and 140 mH,
respectively.
4 Setting profile of the proposed scheme
The proposed scheme was tested with the constructed four-terminal
HVDC system shown in Fig. 1. Loading variations were analysed
first. Then, DC faults with both pole-to-earth and pole-to-pole fault
types were investigated to determine a sensitive and secure
threshold setting of d´Ʊ.
L12, the value of the d´Ʊ reached 4000 p.u. during the first 2 ms
for busbars B1 and B2 as shown in Figs. 10a and b, respectively.
The DC currents increased rapidly to >6 p.u. for L12 within 4 ms at
B1 and to >5 p.u. within 6 ms at B2 as shown in Figs. 10c and d,
respectively. As illustrated from the results, the summation
criterion is still satisfied similarly.
4.2 Selecting the setting profile of d´Ʊ
As depicted from both loading and faulty testing cases, d´Ʊ did not
exceed 284 p.u. for heavy loading variation as well as for healthy
lines during fault conditions. Also, d´Ʊ reached a remarkable
higher-level during faults (>2000 p.u.). Hence, the selected
threshold value of d´Ʊ was selected to be 500 p.u. This selected
threshold is close to two times of the d´Ʊ for the applied load
change as well as lower than the resulting levels during fault cases.
For pole-to-earth faults, the value of d´Ʊ is clearly changed for
the faulted and non-faulted lines. However, it exceeds the selected
setting limit for the faulted ones only. Fig. 8 shows the values of d
´Ʊ for all busbars during the applied fault at F1. d´Ʊ reached the
selected setting limit at the two sides of the faulted line L12 after
50 and 530 μs as described in Figs. 8a and b, respectively. Then,
adding the blocking time of the solid-state DCCB (1 ms) and the
approximated relay time (0.2 ms) resulted in total clearing times of
1.25 and 1.73 ms for B1 and B2 sides, respectively. d´Ʊ does not
reach the setting limit for the healthy lines at B3, B4, B5, and B6

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Fig. 7  System performance under the pole to earth fault at F1
(a) Station1 AC voltage, (b) Station1 AC current, (c) B1 branches currents, (d) B1-DC
voltage
Fig. 8  d´Ʊ values in case of the pole to earth fault at F1
(a) d´Ʊ for B1, (b) d´Ʊ for B2, (c) d´Ʊ for B3, (d) d´Ʊ for B4
Fig. 9  d´Ʊ values in case of the pole to earth fault at F1 for the tie-busbar
within the maximum allowable time for the main protection
scheme (2 ms after the fault instant) as shown in Figs. 8c and d.
Similar situations were realised as well for pole-to-pole faults.
Table 3 summarises the resulting d´Ʊ under different fault cases.
As an example, d´Ʊ reached the setting limit within 70 and 600 μs
for fault at F2 on the line L24 for both sides of the faulted line.
Similar results were obtained for faults at F3, F4, F5, and F6 as
well. Thus, the suitability of the selected setting edge for d´Ʊ was
verified.
5 Performance evaluation of the proposed
protection scheme
5.1 Faults at station terminals
As illustrated in Fig. 11a, a pole-to-ground fault at F1 on line L12
at 1.5 s. The role of the protection scheme is to detect the fault and
isolate faulty line L12 only. Then, the DC system should be
restored to its normal operation after clearing the fault. As station
S1 still has its rated value, currents IL13 and IL15 are increased to
compensate for the current of the isolated line. Fig. 11b shows the
3038
time line of the proposed protection scheme, where d´Ʊ reached
the threshold value after 50 μs from the fault instant at 1.5 s. The
protective relay takes only 0.2 ms for executing the algorithm and
initiates a trip signal at 1.50025 s to the solid-state DCCB to
interrupt the fault within 1 ms at a time of 1.50125 s. Fig. 11c
shows the measuring currents at substation S2, where there is no
current between stations S2 and S1 due to the operation of
DCCB21. As noted from the results, clearing the fault did not
affect the operation of station S2, which was continued to operate
near its normal operation in the inverting mode. The currents in the
other lines IL26 and IL24 were increased to maintain the required
current for station S2. Fig. 11d illustrates the status of all station
currents keeping their original current levels before the fault.
As depicted from Fig. 12, the voltages of both DC and AC sides
of substation S1 were insignificantly impacted with the applied
fault at F1. Hence, the capability of the proposed protection
scheme to identify and isolate the faulted line is verified without
utilising communication facilities.
5.2 Faults close to the tie-busbar
For a fault at F5 on line L53 close to the tie-busbar, the value of d
´Ʊ for the protective relay on the tie-busbar reaches the threshold
value within 20 μs from the fault instant as shown in Fig. 13a.
Then, a tripping signal was issued to the DCCB53 to isolate the
fault from the tie-busbar side as shown in Fig. 13c after the
relaying time of 0.2 ms. Therefore, the fault was blocked from the
B5 side within 1.22 ms (considering a solid-state DCCB with a
blocking time of 1 ms). For the other side of L53, all branches
connected with the busbar B3 fed the fault through the segment
L53. d´Ʊ reached the threshold value within 0.3 ms after the fault
instance as shown in Fig. 13a. Then, the corresponding protective
relay detected the fault on line segment L53 from busbar B3 within
0.2 ms. Accordingly, a tripping signal was issued to DCCB35 to
block the gate signal of the insulated-gate bipolar transistors
feeding the fault from B3 side within 1 ms. Hence, the fault was
detected and isolated within 1.5 ms as depicted in Fig. 13d.
The results visualised a successful detection and isolation of the
faulted line from both line sides without utilising communication
facilities. Then, the related stations maintained their normal
operation as demonstrated in Fig. 14. On the other hand, d´Ʊ of
other branches connected to the tie-busbar (L15, L26, and L46) did
not reach the threshold level as shown in Fig. 13a with the
originally designed DC reactors at the tie-busbar. By utilising the
refined DC reactors at the tie-busbar, d´Ʊ of the other healthy
branches connected to the tie-busbar (L15, L26, and L46) did not
reach the threshold level as shown in Fig. 13b. Fig. 14a shows the
instantaneous current distribution after the fault instant, where all
branches connected with the tie-busbar feed the fault. The
identification criterion is achieved for L53, L35, and L26. After the
fault clearing by blocking DCCB53 and DCCB35, the system
restored its normal operation with the current distribution shown in
Fig. 14b. Although the summation criterion is achieved at L26, the
fault detection criterion was not satisfied as the values of d´Ʊ did
not reach the threshold value as shown in Fig. 13a. Hence, line L26
was still connected and successful relaying coordination was
achieved under this critical case.
5.3 Faults on the tie-busbar
For the fault at F6 on tie-busbar B5, d´Ʊ for all branches connected
to tie-busbar B5 exceeded the threshold value within 70 μs from
the fault instant as shown in Fig. 15a. After the relaying time (0.2 
ms), the busbar protective relay detected the fault and identified it
as a busbar one, where all currents are incoming towards B5.
Therefore, the corresponding protective relay blocked all DCCBs
connected to B5 (DCCB56, DCCB51, and DCCB53). Thus, the
fault was blocked from B5 within 1.27 ms considering the DCCB
blocking time of 1 ms.
In this case, the identification criterion is achieved for L35 and
L26. As shown in Fig. 15b, d´Ʊ reached the threshold value for
L35 within 0.8 ms and for L26 within 1.2 ms before clearing the
faulted tie-busbar. Therefore, the protective relays installed on B2
IET Renew. Power Gener., 2019, Vol. 13 Iss. 16, pp. 3033-3042
© The Institution of Engineering and Technology 2019
and B3 detected the fault and identified the faulted line wrongly
and blocked the DCCB26 and DCCB35, respectively, as discussed
in Section 2.3. Then, the refined DC reactors at tie-busbar
overcome this problem. Fig. 15c illustrates the recorded d´Ʊ values
for all branches connected at tie-busbar where it reaches the
threshold value within 70 μs from the fault instant. The busbar
protective relay detects the fault and identifies the busbar fault as
all current directions are incoming towards B5.
The fault is cleared within 1.27 ms. On the other hand, as
shown in Fig. 15d, d´Ʊ reached the threshold value for L35 within
1.3 ms and for L26 within 2.5 ms. Therefore, the fault was cleared
before the protective relays at B2 and B3 detect the fault. As shown
in Fig. 16a, the busbar protection algorithm detected the fault and
identified a busbar fault condition blocking all DCCBs connected
to the busbar B5 (DCCB56, DCCB51, and DCCB53). Then, the
system restored its normal operation with the resulting current
distribution shown in Fig. 16b.

5.4 Influences of fault resistance

Fig. 10  System performance under the pole to pole fault at F1
(a) d´Ʊ for B1, (b) d´Ʊ for B2, (c) DC current for B1, (d) DC currents for B2
As the fault resistance increases as d´Ʊ, unfortunately, decrease
under the same fault conditions. Consequentially, the fault
resistance inversely affects the sensitivity of the proposed detection
method. The critical fault resistance was obtained via excessive
simulation tests that have d´Ʊ = 500 p.u. The fault resistance limit
is characterised by different factors including the nominal current
and the power rating and the voltage level. In this system, the
voltage rating for each pole is 200 kV and the rated current is 1 kA.
Thus, the virtual load resistance is 200 Ω.
To avoid the operation of the protection scheme in case of
overload, the maximum current limit is considered as 1.25 kA,
consequentially the maximum virtual resistance is 160 Ω.
For the same pole-to-earth fault case F1, a fault resistance was
of 150 Ω was added in the fault path. The d´Ʊ reached the setting
value at both terminals of the faulted lines B1 and B2 after 1.2 and

Table 3 d´Ʊ profile for various fault cases

Faults
Lines Features F1 F1 F1 F1 F1 F1
L12 dʹƱ, pu 500 350
time, μs 50 2000
L13 dʹƱ, pu 500
time, μs 350
L15 dʹƱ, pu 400 500
time, μs 200 1200
L21 dʹƱ, pu 500
time, μs 530
L24 dʹƱ, pu 500 265
time, μs 50 2000
L26 dʹƱ, pu 420 500
time, μs 2000 1200
L31 dʹƱ, pu 284 500
time, μs 2000 50
L34 dʹƱ, pu 500
time, μs 380
L35 dʹƱ, pu 500 500
time, μs 300 800
L42 dʹƱ, pu 202 500
time, μs 2000 550
L43 dʹƱ, pu 380 500
time, μs 2000 50
L46 dʹƱ, pu 600 500
time, μs 2000 800
L51 dʹƱ, pu 150 170 −500
time, μs 2000 2000 70
L53 dʹƱ, pu 285 500 −500
time, μs 2000 20 70
L62 dʹƱ, pu −157 220 −500
time, μs 2000 2000 70
L64 dʹƱ, pu 110 380 −500
time, μs 2000 2000 70
No values denote the healthy line which is not connected with the faulted line; Italic values denote the faulted line and identification criteria achieved; bold values denote the healthy
line which is connected with the faulted line.

IET Renew. Power Gener., 2019, Vol. 13 Iss. 16, pp. 3033-3042 3039
© The Institution of Engineering and Technology 2019

Fig. 11  Evaluation of the proposed protection scheme under fault case
‘F1’
(a) B1 branch currents, (b) Time line of protection scheme operation, (c) B2 branches
currents, (d) Stations DC currents
Fig. 12  AC and DC voltages profile under F1 fault
(a) DC voltage at B1, (b) Station 1 AC voltages
Fig. 13  Evaluation of the proposed protection scheme under fault F5
closed to the tie-busbar B5
(a) d´Ʊ values for all branches connected with B5 and B6, (b) d´Ʊ values for all
branches connected with B5 and B6 with tuned DC reactor, (c) Currents values for all
branches connected with B5 and B6, (d) Currents values for all branches connected
with B3
0.7 ms as shown in Figs. 17a and b, respectively. As illustrated in
Figs. 17c and d, the protection scheme detected the fault and
blocked it from the B1 side within 2.4 ms. As illustrated in
Fig. 17b, the period of the dƱ/dt value above the threshold is 1.501  On the other hand, increasing the utilised DC reactors at the
− 1.5007 = 300 μs (it should be equal to three samples to have an
average value over the threshold). Therefore, the optimum
sampling frequency with the same sensitivity (for faults with 150 Ω
fault resistance) should be above 10 kHz. Thus, the selected 20  can be detected by the relays at the tie-busbar side as shown in
kHz sampling rate is perfect for realising the aimed sensitivity.
Table 4 summarises different fault cases including solid and non-
solid faults with the refined DC reactors. For a solid fault at F6, the
protection scheme installed at B5 took 800 μs for detecting the
3040
Fig. 14  Current distribution under fault F5 closed to the tie-busbar B5
(a) Current distribution during the fault at F5, (b) Current distribution after blocking
the fault at F5
Fig. 15  Evaluation of the proposed protection scheme under fault F6 on
the tie-busbar B5
(a) d´Ʊ for all branches connected with B5 and B6, (b) d´Ʊ for all branches connected
with B5 and B6 from station sides, (c) d´Ʊ for all branches connected with B5 and B6
with refined reactors, (d) d´Ʊ for all branches connected with B5 and B6 from station
sides with refined reactors
Fig. 16  Current distribution under fault F6 on B5
(a) Current distribution during F6, (b) Current distribution after blocking F6
fault at B6, whereas the fault was cleared after 2 ms. As verified
from the results, the refined DC reactors at the tie-busbar side,
succeeded to keep the aimed security by inhibiting unnecessary
tripping of healthy branches for those faults near or at the tie-
busbar without utilising an extra time delay. This facilitated a
secure, sensitive and fast protection scheme even with severe fault
conditions. Therefore, utilising the refined DC reactors was
preferred as compared with the forced time delay method.
connected branches to the tie-busbar impacted the sensitivity limit
for the inserted relays at the tie-busbar. With the refined DC reactor
on the branch L53 of 120 mH, a fault resistance up to only 100 Ω
Fig. 18.
IET Renew. Power Gener., 2019, Vol. 13 Iss. 16, pp. 3033-3042
© The Institution of Engineering and Technology 2019
 characterised by no time delay under line faults far away from the
tie-busbar. This provides a powerful, fast, and reliable protection
scheme for HVDC systems. The performance of the proposed
scheme was thoroughly investigated via a detailed simulation of a
three-level VSC-based system with four-terminals and two tie-
busbars. The simulation results corroborated the precise
performance of the proposed scheme with a fast fault detection
time up to 0.25 ms. Furthermore, relaying coordination and scheme
security were verified for all applied simulation tests.

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