applied
sciences
Article
Resonant Asymmetrical Half-Bridge Flyback Converter
Yeu-Torng Yau 1,2
Citation: Yau, Y.-T. Resonant
Asymmetrical Half-Bridge Flyback
Converter. Appl. Sci. 2022, 12, 6685.
https://doi.org/10.3390/
app12136685
Academic Editor: Matti Lehtonen
Received: 1 June 2022
Accepted: 29 June 2022
Published: 1 July 2022
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Appl. Sci. 2022, 12, 6685. https://doi.org/10.3390/app12136685
1 Department of Ph.D. Program, Prospective Technology of Electrical Engineering and Computer Science,
National Chin-Yi University of Technology, Taichung 411030, Taiwan; pabloyau@ncut.edu.tw;
Tel.: +886-902316306
2 Department of Electrical Engineering, National Chin-Yi University of Technology, Taichung 411030, Taiwan
Abstract: The active clamp flyback (ACF) converter is gradually becoming popular in the application
field of low or medium output power range due to its advantage of soft switching and high conversion
efficiency. An asymmetric half-bridge (AHB) flyback converter has been proposed in previous studies.
The main advantages of the AHB flyback are the same number of components as the ACF converter
and the soft switching technique. In this paper, an AHB flyback converter with constant off-time
(COT) plus pulse frequency modulation (PFM) is proposed, so that the resonant time is not affected by
the input voltage and load, and can achieve a wide range of zero voltage switching (ZVS) operating
range. Compared to pulse width modulation (PWM), the PFM control with COT can make the system
more stable. Finally, a prototype circuit with a specification input of 48 V to an output of 2.5 V/8 A is
made for verification.
Keywords: asymmetric half-bridge; flyback converter; constant off-time; resonant converter
1. Introduction
The flyback converter is widely used in the low to medium output power range
because of the advantages of fewer circuit components and simple control. Compared with
the LLC converter, the flyback converter requires fewer components, but the switching
voltage stress of the flyback converter is higher than that of the LLC converter. The voltage
stress of the main switch of the flyback converter is the input voltage plus the reflection
voltage and spike voltage. The snubber circuit is added to switches of the flyback converter
to reduce the voltage surge. However, the voltage stress of an LLC converter is only equal
to the input voltage, so low-voltage components can be used. The advantage of flyback
converter over LLC converter is the wide input voltage and the simple control method,
so that no pre-stage voltage regulator is required. Although the research in [1,2] provides
the input voltage range with wide variation range of switching frequency, it also results
in efficiency reduction and EMI problems. The multi-level approaches proposed in [3–11]
make LLC converters extend the operating voltage range, but still have the problems of the
number of components, complex structure, and difficult control, so as to make it difficult to
balance cost and performance. Based on the reasons above, the flyback-based topologies
are still attractive solutions.
To increase conversion efficiency, more technologies have been added to the conven-
tional flyback converter, such as quasi-resonance (QR) [12–15] or active clamping [16–19] to
achieve zero-voltage switching (ZVS) and reduce switching loss. Synchronous rectification
(SR) [20,21] can also be applied to reduce the conduction loss and further improve the
conversion efficiency. The difference in the number of components between the active
clamp flyback (ACF) converter and the LLC converter is that the ACF converter needs only
a single secondary SR switch, which is the cost advantage of the ACF converter.
The asymmetric half-bridge (AHB) flyback converter has been proposed in previous
studies [20–29], whose main advantage is that the number of components is the same
as that of ACF converter, and it also provides the same voltage stress on the switching
https://www.mdpi.com/journal/applsci
 that of ACF converter, and it also provides the same voltage stress on the switching ele-
ments
that as theconverter,
of ACF LLC converterand it with ZVS turn-on.
also provides Mostvoltage
the same studiesstress
of AHB on flyback
the switchingconverters
ele-
Appl. Sci. 2022, 12, 6685
adopt as
ments pulse
the width modulation
LLC converter with(PWM) control. Most studies of AHB flyback 2converters
ZVS turn-on. of 23
adoptHowever,
pulse width previous
modulationresearches
(PWM) in control.
[20–27] suggest that PWM should not be used be-
cause Toff of PWM
However, mode varies
previous within
researches the[20–27]
input voltage
suggestand thatload
PWM condition
should to notaffect
be usedthe ZVS
be-
operation
cause Toff ofasrange.
elements PWM
the LLC In converter
mode[28], the with
varies AHB
with flyback
the
ZVS inputconverter
turn-on. voltage is unstable
and
Most studies load
of AHB with the
condition
flyback to PWMthe
affect
converters control
ZVS
method.
operation The
range.article
In [20,30]
[28], proposes
the AHB
adopt pulse width modulation (PWM) control. a resonant
flyback AHB
converter flyback,
is unstablewhichwithprovides
the PWM a ZVS func-
control
tion on
method. its
The
However, switches.
article However,
[20,30]
previous the
proposes
researches efficiency
a resonant
in [20–27] atAHB
suggest light load should
that flyback,
PWM and dynamic
whichnotprovidesresponse
be used a ZVSare
because not
func-
mentioned.
T of PWM mode varies with the input voltage and load condition
tionoff on its switches. However, the efficiency at light load and dynamic response are not to affect the ZVS
operation range. Inhigh
The resonant
mentioned. [28], step-down
the AHB flyback converter
converter [31],isshown
unstable in with the 1,
Figure PWM control with
is proposed
method.
constant The article
off-time (COT)
The resonant [20,30] proposes
and pulse frequency
high step-down a resonant AHB
converter modulation flyback,
[31], shown (PFM), which
in Figure provides
which a ZVS with
1, isisproposed
verified witha
function
wide range on its switches.
of ZVS However,
operations. the
In this efficiency at light
paper, amodulation load
resonant AHB and dynamic
flyback response
converter are
with COT
constant off-time (COT) and pulse frequency (PFM), which is verified with a
not mentioned.
control
wide range is proposed
of ZVS high as shown
operations. in Figure
In this 2 to improve
paper,[31],
a resonant the ZVS
AHB operation.
flyback A prototype
converterwith with COT with
The resonant step-down converter shown in Figure 1, is proposed
aconstant
specification
control off-time (COT) and pulse frequency modulation (PFM), which is verified with a iswith
is proposed inputas of 48
shown V to
in output
Figure 2.5
2 to V/8 A
improve is made
the to
ZVS verify that
operation. the
A concept
prototype fea-
sible.
a wide
specification
range of ZVS input of 48 V toInoutput
operations. 2.5 V/8
this paper, A is made
a resonant AHB to verify
flyback that thewith
converter concept
COT is fea-
sible.
control is proposed as shown in Figure 2 to improve the ZVS operation. A prototype with a
specification input of 48 V to output 2.5 V/8 A is made to verify that the concept is feasible.
Vin
Vin
(D) Coss1
(D) Q1 ids1 Coss1
iLr
Q1 vCr iCr iN2 VO
ids1 +vCr - iCr iLr
ids2 + iN2 VO
+ Cr- Lr
+
N1 iN1 ids3 N2
ids2 +
Cr Lr
+
Ni1LmiN1 ids3 N2
(1-D) Coss2 CO
Coss3
(1-D) Q2 Coss2
i(1-D)’
Lm
Q3 CO
Q2 Coss3
(1-D)’Q3

Figure 1. The previous high step-down converter with COT control.

Theprevious
Figure1.1.The
Figure previous high
highstep-down
step-downconverter with
converter COT
with control.
COT control.

Vin
Vin
(D) Coss1
(D) Q1 ids1 Coss1
iLr
Q1 vCr iCr iN2 VO
ids1 + - iCr iLr iN2
ids2 vCr + +
VO
+ Cr- Lr N1 iN1 ids3 +
N2
ids2 +
N1iLmiN1 Q N
CCross2 Lr ids3 3 2
(1-D) CO
Q3
(1-D) Q2 Coss2 iLm
Coss3 (1-D)’CO
Q2 Coss3 (1-D)’
Figure2.
Figure The proposed
2. The proposed resonant
resonantAHB
AHBflyback converter.
flyback converter.
Figure 2. The proposed
2. Proposed resonant AHB flyback converter.
Circuit Configuration
2. Proposed Circuit Configuration
As shown in Figure 2, the proposed circuit consists of half-bridge switches Q1 and
2.QProposed
As shownCircuit Configuration
in Figure 2, the proposed circuit consists of half-bridge switches Q1 and
2 , a SR switch Q3 , resonant capacitor Cr , and coupling inductor L with magnetizing
Qinductance
2, aAsSRshown
switch Q ,
in Figure
Lm , leakage
3 resonant
2, the
inductor capacitor
Lproposed Cr,circuit
r , and windingsandNcoupling
and N2 . inductor
1 consists L with
of half-bridge
The proposed magnetizing
switches
circuit adoptsQ1 andin-
Qductance
the Lm, leakage
2, a combinational
SR switch Q3,controlinductor
method
resonant Lr,ofand
capacitorQR Cwindings
and COT
r, and N1 and
[31],
couplingwhich N2is. The proposed
suitable
inductor circuit adopts
for amagnetizing
L with converter in-
with
the low voltage
combinational gain and
control high
methodoutputof current.
QR and Figure
COT 3 shows
[31], which
ductance Lm, leakage inductor Lr, and windings N1 and N2. The proposed circuit adopts the waveforms
is suitable of
for each
a converter
point
with
the of the
low
combinationalcircuit.gain
voltage The proposed
control highcircuit
andmethod hascurrent.
output
of QR 8 states,
and COTas shown
Figure
[31], 3 in Figure
shows
which 4. waveforms
the
is suitable of each
for a converter
pointlow
with of the circuit.
voltage gain Theandproposed circuitcurrent.
high output has 8 states,
Figureas shown
3 showsinthe Figure 4.
waveforms of each
point of the circuit. The proposed circuit has 8 states, as shown in Figure 4.
 Before entering the following behavior description, the definitions of the resonance
tanks are listed as (1) to (8). In addition, the iN2(0) and the ids2(0) are both supposed as 0 A
Appl. Sci. 2022, 12, 6685 at t0, respectively. The inductance of Lm is assumed to be much higher than the inductance
3 of 23
of Lr, so iLm can be considered a constant current source.

vgs1
0

ids1 0

vds1
0

vgs2
0

ids2 0

vds2
0

vgs3
0

vds3
0

0
ids3

iN2
0

vCr
0

iCr 0

iLm
0

t0 t1 t2 t3 t4 t5 t6 t7 t0+Ts
Figure 3. Operation waveforms of the proposed circuit.
 Appl. Sci. 2022, 12, x FOR PEER REVIEW 4 of 24

Appl. Sci. 2022, 12, 6685 4 of 23

Figure 3. Operation waveforms of the proposed circuit.

Vin Vin
State 1: t0~t1 State 2: t1~t2
ON OFF
Q1 Q1
vCr Lr VO vCr Lr VO
＋ − + ＋ − +
Cr
+ N1 N2 Cr
+
N1 N2
Lm Q3 Lm Q3
OFF CO OFF CO
Q2 OFF Q2 OFF

(a) (b)
Vin Vin
State 3: t2~t3 State 4: t3~t4
OFF OFF
Q1 Q1
vCr Lr VO vCr Lr VO
＋ − + ＋ − +
Cr
+
N1 N2 Cr
+
N1 N2
Lm Q3 Lm Q3
CO CO
ON Q2 OFF ON Q2 ON

(c) (d)
Vin Vin
State 6: t5~t6
State 5: t4~t5
OFF OFF
Q1 Q1
vCr Lr vCr Lr VO
＋ − VO ＋ −
+ +
Cr
+
N1 N2 Cr
+
N1 N2
Lm Q3 OFF Lm Q3
ON Q2 CO CO
ON Q2 ON

(e) (f)
Vin Vin
State 7: t6~t7 State 8: t7~t0+Ts
ON ON
Q1 Q1
vCr Lr VO vCr Lr VO
＋ − +
＋ − +
Cr
+
N1 N2 Cr
+
N1 N2
Lm Q3 Lm Q3
OFF CO OFF CO
Q2 ON Q2 OFF

(g) (h)
Figure 4. Operation states of the proposed circuit: (a) state 1; (b) state 2; (c) state 3; (d) state 4; (e)
Figure Operation
state 5;4.(f) states
state 6; (g) stateof7;the
andproposed
(h) statecircuit:
8. (a) state 1; (b) state 2; (c) state 3; (d) state 4; (e) state
5; (f) state 6; (g) state 7; and (h) state 8.

Before entering the following behavior description, Lm + Lr the definitions of the resonance
Z1 = ,
tanks are listed as (1) to (8). In addition, the iN2 (0)C and the ids2 (0) are both supposed as 0 (1)
A
r
at t0 , respectively. The inductance of Lm is assumed to be much higher than the inductance
of Lr , so iLm can be considered a constant current1source.
r1 =s , (2)
Cr ( Lm + Lr )
L m + Lr
Z1 = , (1)
Cr
Lm + Lr Lm + Lr
Z2 = = , (3)
Cr + ( Coss1 + Coss 12) Cr +2  Coss 2
ωr1 = p , (2)
Cr ( Lm + Lr )
1 1
r 2 = =s ,
( Cr + ( Coss1 +LCmoss+2 )L) r( Lm + Lr ) ( CLr +2  )( + ) (4)
s
m + CL r
oss 2 Lm Lr
Z2 = = , (3)
Cr + (Coss1 + Coss2 ) Cr + 2 · Coss2
1 1
ωr2 = p = p , (4)
(Cr + (Coss1 + Coss2 ))( Lm + Lr ) (Cr + 2 · Coss2 )( Lm + Lr )
Appl. Sci. 2022, 12, 6685 5 of 23

s
Lr
Z3 = , (5)
Cr
1
ωr3 = √ , (6)
Cr · Lr
s
Lr
Z4 = n2 · , (7)
Coss3
1
ωr4 = √ , (8)
Coss3 · Lr

2.1. State 1 (t0 − t1 )

During this interval, Q1 is turned on, and Q2 and Q3 are turned off. Vin charges Cr
and magnetizes Lm to make iLm (iLm = iLr = iCr ) rise. When Q1 is turned off, it enters state 2.

di Lr
( L m + Lr ) · = Vin − vCr , (9)
dt
dvCr
Cr · = i Lr = i Lm , (10)
dt
Vin − vCr (t0 )
i Lr (t) = · sin(ωr1 (t − t0 )) + i Lr (t0 ) · cos(ωr1 (t − t0 )), (11)
Z1
vCr (t) = Vin − (Vin − vCr (t0 )) · cos(ωr1 (t − t0 )) + i Lr (t0 ) · Z1 · sin(ωr1 (t − t0 )), (12)

2.2. State 2 (t1 − t2 )

During this interval, Q1 is turned off, and Q2 and Q3 are turned off. The freewheeling
current iLr of Lr charges Cr . Therefore, iLr is demagnetized to decrease. iLm is more than iLr .
The partial iLm flows through winding N1 and releases energy to winding N2 to the output
terminal with transformer behavior. iLr charges Coss1 and discharges Coss2 , so vds1 rises and
vds2 falls. At the same time, iN2 discharges Coss3 to make vds3 drop. The iN2 flows through
the body diode of Q3 , so vds3 is zero. iLm releases energy from winding N1 to winding N2 to
the output terminal. When vds2 falls to zero, it enters state 3.

di Lr
( L m + Lr ) · = vds2 − vCr , (13)
dt
dvCr
Cr · = i Lr = i Lm , (14)
dt
d(Vin − vds1 ) dv
Coss1 · + Coss2 · ds2 = i Lm = i Lr , (15)
dt dt
dv
2 · Coss2 · ds2 = i Lm = i Lr , (16)
dt
N2
i Lr = i Lm + i N1 = i Lm + i N2 · , (17)
N1
Vin − vCr (t1 )
i Lr (t) = · sin(ωr2 (t − t1 )) + i Lr (t1 ) · cos(ωr2 (t − t1 )), (18)
Z2
 
Cr + 2Coss2 i Lr (t1 )
vCr (t) = (Vin − vCr (t1 )) · [1 − cos(ωr2 (t − t1 ))] + · sin(ωr2 (t − t1 )) + vCr (t1 ), (19)
Cr ωr2 · 2Cr
 
Cr + 2Coss2 i Lr (t1 )
vds1 (t) = (Vin − vCr (t1 )) · [1 − cos(ωr2 (t − t1 ))] + · sin(ωr2 (t − t1 )) , (20)
Cr ωr2 · 2Coss2
vds2 (t) = Vin − vds1 (t1 ), (21)
Appl. Sci. 2022, 12, 6685 6 of 23

2.3. State 3 (t2 − t3 )

During this interval, Q1 and Q3 remain off, and Q2 is turned on. The freewheeling
current iLr charges Cr . iLr is demagnetized and drops. iLr charges Coss1 to Vin , while Coss2 is
discharged to zero. iLr and iN2 flow through the body diodes of Q2 and Q3 , so vds2 and vds3
are 0, respectively. At this time, Q2 and Q3 are turned on with the ZVS function. However,
in order to avoid triggering Q3 by mistake, the SR control IC turns on Q3 after a short
time delay. iLm transmits energy through the winding N1 to the winding N2 to the output
terminal. When vds3 falls to zero, it enters state 4.

di Lr
( L m + Lr ) · = −vCr , (22)
dt
di Lm
Lm · = −n · VO , (23)
dt
di Lr
Lr · = n · VO − vCr , (24)
dt
dv
Cr · Cr = i Lr , (25)
dt
n · VO − vCr (t2 )
i Lr (t) = · sin(ωr3 (t − t2 )) + i Lr (t2 ) · cos(ωr3 (t − t2 )), (26)
Z3
vCr (t) = n · VO − (n · VO − vCr (t2 )) · cos(ωr3 (t − t2 )) + i Lr (t2 ) · Z3 · cos(ωr3 (t − t2 )), (27)

2.4. State 4 (t3 –t4 )

During this interval, Q2 and Q3 remain on, and Q1 is turned off. After the default
delay time, the SR control IC turns Q3 with ZVS turned on. iLr still is demagnetized and
drops when the freewheeling current iLr charges Cr . The stored energy of Lm is released
from the winding N1 to the winding N2 to the output terminal. When the polarity of iCr is
changed from positive to negative, it enters state 5.

N1 N
i N2 = · i = 1 · (i Lr − i Lm ), (28)
N2 N1 N2

di Lr
( L m + Lr ) · = −vCr , (29)
dt
di Lm
Lm · = −n · VO , (30)
dt
di Lr
Lr · = n · VO − vCr , (31)
dt
dv
Cr · Cr = i Lr , (32)
dt
n · VO − vCr (t3 )
i Lr (t) = · sin(ωr3 (t − t3 )) + i Lr (t3 ) · cos(ωr3 (t − t3 )), (33)
Z3
vCr (t) = n · VO − (n · VO − vCr (t3 )) · cos(ωr3 (t − t3 )) + i Lr (t3 ) · Z3 · cos(ωr3 (t − t3 )), (34)

2.5. State 5 (t4 − t5 )

During this interval, Q1 remains on, and Q2 and Q3 remain off. Lr is demagnetized to
reduce iLr to zero gradually. Cr magnetizes Lr reversely in the third quadrant to increase iLr
and releases energy to output terminal via winding N2 . Additionally, vCr discharges and
falls. When Q2 is turned off, it enters state 6.

N1 N
i N2 = · i N1 = 1 · (i Lr − i Lm ), (35)
N2 N2
Appl. Sci. 2022, 12, 6685 7 of 23

di Lr
( L m + Lr ) · = −vCr (36)
dt
di Lm
Lm · = −n · VO , (37)
dt
di Lr
Lr · = n · VO − vCr , (38)
dt
dv
Cr · Cr = i Lr , (39)
dt
n · VO − vCr (t4 )
i Lr (t) = · sin(ωr3 (t − t4 )) + i Lr (t4 ) · cos(ωr3 (t − t4 )), (40)
Z3
vCr (t) = n · VO − (n · VO − vCr (t4 )) · cos(ωr3 (t − t4 )) + i Lr (t4 ) · Z4 · cos(ωr3 (t − t4 )), (41)

2.6. State 6 (t5 − t6 )

During this interval, Q1 remains off. Q3 remains on. Q2 is turned off. After Q2 is
turned off, the freewheeling current iLr charges Cr , then iLr is demagnetized and reduced.
iLr discharges Coss1 to decrease vds1 , and iLr charges Coss2 to raise vds2 gradually. During
this interval, Cr discharges, so vCr falls.

di Lm
Lm · = −n · VO , (42)
dt
di Lr
Lr · = n · VO − vCr − (−n · VO ) − vds1 , (43)
dt
dv
Cr · Cr = i Lr , (44)
dt
dvds2 d(Vin − vds1 )
Coss2 · + Coss1 · = i Lr , (45)
dt dt
dv
2 · Coss2 · ds2 = i Lr , (46)
dt
 
Cr + 2Coss2 i Lr (t5 )
vCr (t) = (n · Vin − vCr (t5 )) · [1 − cos(ωr2 (t − t5 ))] + · sin(ωr2 (t − t5 )) + vCr (t5 ), (47)
Cr ωr2 · 2Cr
 
Cr + 2Coss2 i Lr (t5 )
vds1 (t) = (n · Vin − vCr (t5 )) · [1 − cos(ωr2 (t − t5 ))] + · sin(ωr2 (t − t5 )) , (48)
Coss2 ωr2 · 2Coss2
n · VO
i Lm (t) = i Lm (t5 ) − ( t − t5 ), (49)
Lm
n · Vin − vCr (t5 )
i Lr (t) = · sin(ωr2 (t − t5 )) + i Lr (t5 ) · cos(ωr2 (t − t5 )), (50)
Z2

2.7. State 7 (t6 − t7 )

During this interval, Q1 is turned on. Q3 remains on. Q2 remains off. iLr discharges
Coss1 to reduce vds1 to zero. Thus, Coss2 is charged and vds2 gradually rises to Vin . During
this state, Q1 is turned on with the ZVS function. When vds1 falls to zero, it enters state 8.

di Lm
Lm · = −n · VO , (51)
dt
di Lr
Lr · = Vin − vCr − (−n · VO ), (52)
dt
dv
Cr · Cr = i Lr , (53)
dt
Appl. Sci. 2022, 12, 6685 8 of 23

n · VO
i Lm (t) = i Lm (t6 ) − ( t − t6 ), (54)
Lm
n · Vin − vCr (t6 ) + n · VO
i Lr (t) = · sin(ωr2 (t − t6 )) + i Lr (t6 ) · cos(ωr2 (t − t6 )), (55)
Z2

vCr (t) = (Vin − vCr (t6 ) + n · VO )[1 − cos(ωr2 (t − t6 ))] + [i Lr (t6 ) · Z2 · cos(ωr2 (t − t6 ))] + vCr (t6 ), (56)

2.8. State 8 (t7 − t0 − Ts )

During this interval, Q1 and Q3 remain on. Q2 is turned off. When iLr is demagnetized
to zero, Vin magnetizes Lr to increase iLr positively. Cr is also charged to raise vCr . Since
iLr is the sum of iLm and iN1 , both vN1 and vN2 are higher than zero when iLr is higher than
iLm . Coss3 is charged to increase vds3 from zero. Once vds3 is positive and detected by the SR
control IC, which turns Q3 off immediately. Due to Lm >> Lr and Cr >> Coss3 , Lm and Cr do
not resonate with Lm and Cr . Therefore, it only needs to consider the resonant operations
of Lr and Coss3 . Lr and Coss3 resonate for half a cycle to raise vds3 . When vds3 is charged to
(vN2 + VO ), it returns to state 1.

di Lr
( L m + Lr ) · = Vin − vCr , (57)
dt
dvCr
Cr · = i Lr = i Lm , (58)
dt
di Lr
Lr · = Vin − vCr − (−n · VO ), (59)
dt
n · VO
i Lm (t) = i Lm (t7 ) − ( t − t7 ), (60)
Lm
Vin − vCr (t7 ) + n · VO
i Lr (t) = · sin(ωr4 (t − t7 )) + i Lr (t7 ) · cos(ωr4 (t − t7 )), (61)
Z4
vds3 (t) = i N2 (t) · Z4 = n · (i Lr (t) − i Lm (t7 )) · Z4 , (62)

vCr (t) = (Vin − vCr (t7 ) + n · VO )[1 − cos(ωr4 (t − t7 ))] + [i Lr (t7 ) · Z4 · cos(ωr4 (t − t7 ))], (63)
The formulas for Q1 and Q2 to achieve ZVS turn-on are shown as (64):

1 1 1
Lr · i Lr (t5 )2 ≥ (Coss1 + Coss2 )Vin
2
= (2Coss2 )Vin2 = 2Coss2 · Vin2 , (64)
2 2 2
The calculation of output current can be expressed as (68).

i N2 = n · i N1 , (65)

i N1 = i Lr − i Lm , (66)
Z t
1
i N2(To f f ) = n · (i Lr − i Lm ) · dt, (67)
t6
Z t
n 1
IO = i N2(avg) = · (i Lr − i Lm ) · dt, (68)
TSw t6

3. Design Considerations
Figure 5 shows the structure of the prototype circuit, where the feedback compensator
is the digital PID-based controller [31–33] with the peak current mode. The digital com-
pensator is implemented with the field programmable gate array (FPGA) chip. Table 1
shows the system specifications and the component list. The design procedure is shown in
Figure 6.

Appl. Sci. 2022, 12, 6685
3. Design Considerations
Figure 5 shows the structure of the prototype circuit, where the feedback compensa-
tor is the digital PID-based controller [31–33] with the peak current mode. The digital
compensator is implemented with the field programmable gate array (FPGA) chip. Table
1 shows the system specifications and the component list. The design procedure is shown
9 of 23
in Figure 6.

Vin

Q1
vCr VO
Driver + - +
Cr Lr
+
N1 N2
Lm SR IC CO
Q2 Q3
Current

iCr
sensor Vref
Gain
Constant verr
Ton 10 bit Voltage loop digital

+
Toff PFM

-
DAC PI compensator
modulater comparator
iref

Figure
Figure5.5.Circuit
Circuitstructure
structureofofthe
theprototype
prototypecircuit.
circuit.

Table
Table1.1.Specification
Specificationof
ofthe
theprototype
prototypecircuit.
circuit.

Symbol Symbol Definition Definition

Vin Vin 24 V~48 V 24 V~48 V
VO VO
2.5 V 2.5 V
IO Rated 8 A
IO Rated 8 A
Appl. Sci. 2022, 12, x FOR PEER REVIEW fsw 120 kHz~180 kHz 10 of 24
fsw 120 kHz~180 kHz

Definition of system Calculation of actual

specifications D, Ton and Toff

Design of ideal D Calculation of

and Ton Tr, Cr and fsw

Design of Lm of Determination of
coupled inductor Q3

Measurement Determination of
of Lm and Lr Q1 and Q2

Figure
Figure 6.
6. Design
Design flow
flow chart.
chart.

3.1. Design
3.1. Design of of Ideal
Ideal DD and
and TTonon
First, the
First, the ideal
ideal duty
duty cycle
cycle is
is obtained
obtained asas (69)
(69)and
and(70)
(70)without
withoutconsidering
considering the
the leakage
leakage
inductance L . Then, the ideal V and V can be obtained as (71) and
inductance Lr. Then, the ideal VCr(24V) and VCr(48V) can be obtained as (71) and (72). The ideal
r Cr(24V) Cr(48V) (72). The
ideal values of T are shown in
values of Ton are shown in (73) and (74).
on (73) and (74).

T Ton V VO
DD== on = =O , N , (69)
+ T+
TonTon T f NV2in · 2 (69)
in 
off o f V N1
N1
2.5 V 2.5 V
D(24V) = 2.5 V N = 20.8%, D(48V) = 2.5 V = 10.4%, (70)
D(24V) = 24 V · N1=20.8%, D(48V) =
2
· N2
48 V =10.4%,
N2 N 2 N1 (70)
24 V  48 V 
N1 vCr = D · Vin , N1 (71)
VCr(24V) = D(24V) · Vvin ==5V, , (48V) = D(48V) · Vin = 5V,
D VVCr (72)
(71)
Cr in

VCr (24V) = D(24V)  Vin =5V, VCr (48V) = D(48V) Vin =5V, (72)
VO
Ton =
N  (73)
f sw  Vin   2 
Appl. Sci. 2022, 12, 6685 10 of 23

VO
Ton =   (73)
N2
f sw · Vin · N1

VO VO
Ton(24V) =   = 1.736 µs, Ton(48V) =   = 0.579 µs, (74)
N2 N2
120 kHz · 24 V · N1 180 kHz · 48V · N1

3.2. Design of Ideal Lm of the Coupled Inductor

The turns ratio of the coupled inductor L and the maximum flux density Bmax are
defined to be 2:1 and 0.1 T, respectively. Then, the turns of L can be designed according to the
given information of Bmax and core material. Then, the ideal windings of L are calculated as
(75) to (77). The ideal magnetizing inductance Lm is calculated in (78). However, the leakage
inductance Lr is highly relative to its geometry structure. The value of Lr is measured after
the coupled inductor L of the prototype is made.

Ton
N = (VLm ) · , (75)
Bmax · Ae
  T
on(24V)
N(24V) = V(24V) − VCr(24V) · = 14.93, (76)
Bmax · Ae
  T
on(24V)
N(48V) = V(48V) − VCr(48V) · = 11.26, (77)
Bmax · Ae
Lm = 142 · A L = 18.82 µH, (78)

3.3. Measurement of Lm and Lr

The coupled inductor L of the prototype is measured with an LCR meter, and the
values of Lm and Lr are obtained as 18.2 µH and 1.9 µH, respectively. The values of D, Ton ,
and Toff can be recalculated according to [22] as (79) to (82).

3.4. Calculation of Actual D, Ton and Toff

The Ton , Toff , D, and the voltage gain can be reprensented as (79), (76), (81), and (82),
respectively.
  
L m + Lr
VO Ton + To f f Lm VO ( TS )

L m + Lr

VO

L m + Lr

Ton = N2
= = = 1.547 µs, (79)
Vin · N1 Vin · N
N1
2 Lm N2
f sw · Vin · N Lm
1
 
1 VO L m + Lr
To f f = − = 5.12 µs, (80)
f sw f sw · Vin · N
N1
2 Lm
 
L m + Lr
Ton V O Lm
D= = , (81)
Ton + To f f Vin · NN1
2

 
VO Lm N
= D· · 2, (82)
Vin L m + Lr N1

3.5. Determination of Tr , Cr and fsw

The current iLr can discharge and charge Coss1 and Coss2 , respectively. To extend the
effect of ZVS turn-on to light load as much as possible, it is better to design Toff to be Tr /4
so as to obtain iLr at its maximum point. The maximum frequency designed at 180 kHz
with Cr as 4.45 µF and 5.06 µF for input voltages of 48 V and 24 V, respectively.

1
Tr = √ , (83)
2π Cr · Lr
Appl. Sci. 2022, 12, 6685 11 of 23

1
Cr = , (84)
Lr (2π · Tr )2
Tr = 4 · To f f = 20.48 µs, (85)
1
Cr =  2 = 5.059 µF, (86)
Lr · 2π T1r

Finally, Cr is chosen to be a 4.7 µF MLCC. Then, fsw is recalculated to obtain 179 kHz
and 155 kHz at input voltages of 24 V and 48 V, respectively.
 
VO LmL+mLr
D(24V) = = 23.2%, (87)
Vin · N
N
2
1

D(48V) = 11.6%, (88)

 
VO LmL+mLr
Ton(24V) = = 1.491 µs, (89)
f sw · Vin N
N
2
1

Ton(48V) = 0.648 µs, (90)

1
f sw(24V) = = 155.63 kHz, (91)
Ton(24V) + To f f (24V)
f sw(48V) = 179.1 kHz, (92)

3.6. Determination of Q3
Q3 is a synchronous rectifier, which always has a ZVS turn-on function without
considering switching loss. The minimum rated voltage of Q3 can be expressed as (94). To
reduce conduction loss, the AON6500 is adopted with drain-source resistance of 0.95 mΩ
and a rated voltage of 30 V.
  
Lr N1
VCr = 1 + VO ≈ 5.5V, (93)
Lm N2
  
Lm N2
vds3 = (Vin − VCr ) + VO ≈ 21.6V, (94)
L m + Lr N1

3.7. ZVS Operation of Q1 and Q2

The ZVS operation of Q1 and Q2 is needed to satisfy the condition in (95) when in state
5. From (96), it can be seen that more iLr can result in ZVS turn-on. However, the output
capacitance of a MOSFET is nonlinear and varies with vds . Consequently, it is not easy to
obtain an accurate result from calculations in (96) and (97).
 2
Lr i Lr(pk) (Coss1 + Coss2 )(Vin )2
≥ (95)
2 2
s
(Coss1 + Coss2 )(Vin )2
i Lr(pk) ≥ , (96)
Lr
i Lr(pk) 2
 
Lr ≥ (Coss1 + Coss2 ), (97)
Vin
Table 2 is the list of the key components in the prototype circuit.
mber Component Information
2 AON7246, 60 V, 15 mΩ (Alpha & Omega Semiconductor, Sunnyvale, CA,
AON6500, 30 V, 0.95 mΩ (Alpha & Omega Semiconductor, Sunnyvale,
Appl. Sci. 2022, 12, 6685 12 of 23
CA
4.7 μF/50 V/1206(Murata)
Table 2. Key components information of the prototype
N1:N2 = 14:7; AL = 96 nH/N2; Acircuit. e = 22.1 mm2; Le = 50.9 mm
Part Number Component Information
C055200A2 (Magnetics Inc., Pittsburgh, PA, USA)
L AON7246, 60 V, 15 mΩ (Alpha & Omega Semiconductor,
Q1 , Q2 18.25 μH@100 kHz
Sunnyvale, CA, USA)

Q3 18.15 μH@150
AON6500, 30 V, 0.95 mΩ kHz
(Alpha & Omega Semiconductor,
Sunnyvale, CA, USA)
Cr 1.854 μH@100 4.7 µF/50kHz
V/1206(Murata)
L
N1.954 μH@150
1 :N 2 = 14:7; AL = 96 nH/NkHz
2 ; A = 22.1 mm2 ; L = 50.9 mm
e e
C055200A2 (Magnetics Inc., Pittsburgh, PA, USA)
Lm of L
driver HIP2101(Renesas, 18.25 Tokyo,
µH@100Japan)
kHz
18.15 µH@150 kHz
470 μF/16 V FPCAP(Nichicon, Kyoto, Japan)
1.854 µH@100 kHz
Lr of L
1.954 µH@150 kHz
390 μF/63 V(Chemicon, Tokyo, Japan)
Half bridge driver HIP2101(Renesas, Tokyo, Japan)
ver MP6905(Monolithic
CO
Power Systems, Kirkland, WA, USA)
470 µF/16 V FPCAP(Nichicon, Kyoto, Japan)
ler EP3C5
Cin FPGA (Intel/Altera, 390 µF/63 Santa Clara,
V(Chemicon, Tokyo, CA,
Japan) USA)
SR driver MP6905(Monolithic Power Systems, Kirkland, WA, USA)
TLV5637 (Texas Instruments, Dallas, TX, USA)
Controller EP3C5 FPGA (Intel/Altera, Santa Clara, CA, USA)
DAC TLV5637 (Texas Instruments, Dallas, TX, USA)
4. Experimental Results
4. Experimental Results
Figure 7 shows the experimental setup blocks of the system test.
Figure 7 shows the experimental setup blocks of the system test.

Agilent
Fluke 45 Fluke 45
34410A
Voltage Voltage Device Voltage
Takasago meter under test meter BK precision
EX750L2 meter 8500B
DC Current shunt AHB DC electrical load
power Vin Flyback Vo (with current
supply converter meter)

Figure 7. Measurement
Figure 7. Measurement setup of setup
theof the system test.
system test.
Figure 8a shows the measured result of the conversion efficiency. The prototype can
achieve better efficiency at lower input voltages and more load currents. This prototype
Figure 8a shows the measured result of the conversion efficiency. The pro
circuit is based on COT control, so the controller increases Ton and reduces fsw as the
achieve betterload
efficiency at lower
increases. When the inputinput
voltagevoltages
decreases, Tonand
also more load
increases. Figurecurrents.
8b shows This
the frequency curve with variation of load current and input voltage. Since the previous
circuit is based on COT control, so the controller increases Ton and reduces fsw
calculation does not take the parasitic effect of individual components into consideration,
increases. When theswitching
the actual input frequency
voltageis decreases, Ton alsocalculation
lower than the theoretical increases.result.Figure 8b sho
The results
of fsw at high input voltage and low input voltage at light load are 148 kHz and 129 kHz,
quency curverespectively.
with variation
Finally, theof loadrange
variation current
∆fsw of and
fsw caninput voltage.
be calculated Since
as ±16.7%, the
which is prev
lation does not
much take thetheparasitic
less than effect
results of ±95.4% ofand
in [1] individual
±100% in [2],components
respectively. into conside
actual switching frequency is lower
∆ f sw = ±
f max − f minthan
=±
thekHz
148 theoretical
− 110 kHz calculation result.
= ±16.7%, (98)
Th
2 · f min 2 · 110 kHz
fsw at high input voltage and low input voltage at light load are 148 kHz and
respectively. Finally, the variation range Δfsw of fsw can be calculated as ±16.7%
much less than the results of ±95.4% in [1] and ±100% in [2], respectively.
Appl. Sci.
Appl. Sci. 2022, 12, x6685
2022, 12, FOR PEER REVIEW 1413ofof 24
23

95% 150

90% 140

85%

Frequency (kHz)
Efficiency

130
80%
24V 120 24V
75%
36V 36V
48V 110 48V
70%

65% 1000
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Load current (A) Load current (A)
(a) (b)
Figure
Figure 8. Measured curves
8. Measured curvesofofconversion
conversion efficiency
efficiency andand switching
switching frequency:
frequency: (a) conversion
(a) conversion effi-
efficiency;
ciency; (b) switching frequency.
(b) switching frequency.

Figures 9 and 10 show thef measured − f min waveforms

148 kHz − 110 of vgs1kHz , vds1 , vgs2 , and vds2 for different
input voltages of 24 Vand f sw =48 Vmaxat 10%,
2  f min
=50%,
 and 100% load, =
2 110 kHz
16.7%,
respectively. They show (98) that
higher input voltage induces more parasitic capacitance energy of the switch and lower iLr
under Figures
the same 9 and 10 show
load, so it isthe notmeasured waveforms
easy to achieve of vgs1, vds1
the complete , vgs2turn-on.
ZVS , and vds2However,
for differentthe
input
switchesvoltages of 24 V
turned-on at and 48 V atv10%,
the lowest ds 50%,
still and
reduce 100%
the load,
switching respectively.
loss. As theThey
load show that
increases,
iLr risesinput
higher to expand
voltage theinduces
voltagemore rangeparasitic
of ZVS turn-on.
capacitance When the output
energy load is and
of the switch morelower
than
i40% of the
Lr under therated
same load,
load, ZVS turn-on
so it is not iseasyalsotoachieved
achieve the at the high voltage
complete input. However,
ZVS turn-on.
Figures 11
the switches and 12 show
turned-on at thethelowest
measured waveforms
vds still reduce the of vgs1 , vgs2 , vCrloss.
switching , andAs iLr the
for different
load in-
input voltages
creases, iLr risesofto24 V and the
expand 48 Vvoltage
at 10%,range
20%, 50%,
of ZVS and 100% load,
turn-on. When respectively.
the outputThe loadvariation
is more
of iLr40%
than andof vCrthe
atrated
different
load,inputZVS voltages
turn-on isisalso not achieved
significant. However,
at the high voltageiLr andinput.
vCr increase
significantly
Figures 11 with
and the12rising
showload. the measured waveforms of vgs1, vgs2, vCr, and iLr for different
Figures 13 and
input voltages of 24 V and 14 show 48 the
V atwaveforms
10%, 20%, 50%, of vgs1and
, vgs2 , vds3load,
100% iN2 for different
, andrespectively. The input
vari-
voltages of 24 V and 48 V at 10%, 20%, 50%, and 100% load, respectively.
ation of iLr and vCr at different input voltages is not significant. However, iLr and vCr increase The more iN2 is,
the higher vds3
significantly becomes.
with the rising This is the driving mechanism of MP6905 SR IC, which controls
load.
the conduction
Figures 13 resistance
and 14 show of MOSFET Q3 at a fixed
the waveforms interval,
of vgs1 , vgs2, vso andvids3
ds3, that remains
N2 for at −32
different mV.
input
Figure 15 shows the measurement results of the phase
voltages of 24 V and 48 V at 10%, 20%, 50%, and 100% load, respectively. The more iN2 is, margin (PM) and gain margin
(GM)
the undervds3
higher different
becomes. loadThis andisdifferent
the drivinginputmechanism
voltage conditions,of MP6905 andSR theIC,
effect of increasing
which controls
load on PM and GM is not significant under the same input
the conduction resistance of MOSFET Q3 at a fixed interval, so that vds3 remains at voltage. Under the same
−32 load,
mV.
the change
Figure of 15 input
showsvoltage can cause the
the measurement PM and
results GM
of the to deteriorate.
phase margin (PM) Theanddetailed results
gain margin
are shown
(GM) underasdifferent
Table 3. load
According to [34,35],
and different thevoltage
input experimental
conditions, resultsand of the
GMeffect
of 6 dB and PM
of increas-
of 45 ◦ can
ing load onmake
PM and sureGM the is closed-loop
not significant system is stable.
under the same input voltage. Under the same
load, the change of input voltage can cause the of
Figure 16 shows the experimental results PM the andloadGM transient response.
to deteriorate. Thevdetailed
CF is the
reference of the inner current-loop controller. V
results are shown as Table 3. According to [34,35], the experimental results of GMcoupled
current o (AC) and vCr(AC) are the ac of 6 dB
signals from Vo and vCr to enlarge the ripple waveforms, respectively. Due to the weak
and PM of 45° can make sure the closed-loop system is stable.
sampling rate and the memory depth of the oscilloscope, the waveforms are measured with
Figure 16 shows the experimental results of the load transient response. vCF is the
significant glitch. The measured results show the close loop response is stable under load
current reference of the inner current-loop controller. Vo(AC) and vCr(AC) are the ac coupled
transient at different input voltages.
signals from Vo and vCr to enlarge the ripple waveforms, respectively. Due to the weak
Table 4 shows the comparison of the proposed and other topologies. Figure 17 shows
sampling rate and the memory depth of the oscilloscope, the waveforms are measured
the photographs of the power stage of the proposed prototype, not showing the part of the
with significant glitch. The measured results show the close loop response is stable under
controller. Q1 ~Q3 and SR IC are soldered to the PCB in an upside-down placement, and
load transient at different input voltages.
only the bottom of the components can be seen externally. There is a buck module to power
Table control
the FPGA 4 showsboard.the comparison of the proposed and other topologies. Figure 17 shows
the photographs of the power stage of the proposed prototype, not showing the part of
the controller. Q1~Q3 and SR IC are soldered to the PCB in an upside-down placement,
and only the bottom of the components can be seen externally. There is a buck module to
power the FPGA control board.
 Appl. Sci. 2022, 12, 6685 14 of 23
Appl. Sci. 2022, 12, x FOR PEER REVIEW 15 of 24

vds1:CH2(20V/div) vds1:CH2(20V/div)
vgs1:CH1(10V/div) vgs1:CH1(10V/div)

vds2:CH4(20V/div) vgs2:CH3(10V/div) vds2:CH4(20V/div) vgs2:CH3(10V/div)

100ns 100ns
(a) (b)

vgs1:CH1(10V/div)

vds1:CH2(20V/div)
vds1:CH2(20V/div) vgs1:CH1(10V/div)

vgs2:CH3(10V/div)

vds2:CH4(20V/div) vds2:CH4(20V/div) vgs2:CH3(10V/div)

100ns 100ns
(c) (d)

vds1:CH2(20V/div)
vds1:CH2(20V/div) vgs1:CH1(10V/div) vgs1:CH1(10V/div)

vgs2:CH3(10V/div) vds2:CH4(20V/div)

vds2:CH4(20V/div) vgs2:CH3(10V/div)

100ns 100ns
(e) (f)
Figure
Figure9.9.Measured
Measuredwaveforms
waveformsof ofvvgs1, vds1, vgs2, and vds2 at input 24 V under (a) Q1 turned-on at 10%
gs1 , vds1 , vgs2 , and vds2 at input 24 V under (a) Q1 turned-on at
load; (b) Q1 turned-off at 10% load; (c) Q1 turned-on at half load; (d) Q1 turned-off at half load; (e)
10% load; (b) Q1 turned-off at 10% load; (c) Q1 turned-on at half load; (d) Q1 turned-off at half load;
Q1 turned-on at full load; and (f) Q1 turned-off at full load.
(e) Q1 turned-on at full load; and (f) Q1 turned-off at full load.
 Appl.
Appl. Sci. Sci.
2022, 12, 12,
2022, 6685PEER REVIEW
x FOR 1516
of 23
of 24

vds1:CH2(20V/div) vgs1:CH1(10V/div)

vds1:CH2(20V/div)
vgs1:CH1(10V/div)

vgs2:CH3(10V/div)

vds2:CH4(20V/div) vds2:CH4(20V/div) vgs2:CH3(10V/div)

100ns 100ns
(a) (b)

vds1:CH2(20V/div)

vds1:CH2(20V/div)
vgs1:CH1(10V/div) vgs1:CH1(10V/div)

vgs2:CH3(10V/div)

vds2:CH4(20V/div) vds2:CH4(20V/div) vgs2:CH3(10V/div)

100ns 100ns
(c) (d)

vgs1:CH1(10V/div)
vds1:CH2(20V/div)
vds1:CH2(20V/div)
vgs1:CH1(10V/div)

vgs2:CH3(10V/div)
vds2:CH4(20V/div)
vds2:CH4(20V/div) vgs2:CH3(10V/div)

100ns 100ns
(e) (f)
Figure
Figure10.10.Measured
Measuredwaveforms
waveformsof ofvvgs1, vds1, vgs2, and vds2 at input 48 V under (a) Q1 turned-on at 10%
gs1 , vds1 , vgs2 , and vds2 at input 48 V under (a) Q1 turned-on at
load; (b) Q 1 turned-off at 10% load; (c) Q1 turned-on at half load; (d) Q1 turned-off at half load; (e)
10% load; (b) Q1 turned-off at 10% load; (c) Q1 turned-on at half load; (d) Q1 turned-off at half load;
Q(e)
1 turned-on at full load; and (f) Q1 turned-off at full load.
Q turned-on at full load; and (f) Q turned-off at full load.
1 1
Appl. Sci. 2022, 12, x FOR PEER REVIEW 17 of 24
Appl.
Appl. Sci. 2022, 12,
Sci. 2022, 12, 6685
x FOR PEER REVIEW 16 of
17 of 23
24

vgs1:CH1(20V/div) vgs1:CH1(20V/div)
vgs1:CH1(20V/div) vgs1:CH1(20V/div)

vgs2:CH2(10V/div) vgs2:CH2(10V/div)
vgs2:CH2(10V/div) vgs2:CH2(10V/div)

vCr:CH3(5V/div) vCr:CH3(5V/div)
vCr:CH3(5V/div) vCr:CH3(5V/div)

iCr:CH4(1A/div) iCr:CH4(1A/div)
iCr:CH4(1A/div) iCr:CH4(1A/div)

2.5μs
2.5μs 2.5μs
2.5μs
(a)
(a) (b)
(b)

vgs1v:CH1(20V/div)
gs1:CH1(20V/div) vv :CH1(20V/div)
:CH1(20V/div)
gs1
gs1

vvgs2:CH2(10V/div)
gs2:CH2(10V/div)
vgs2v:CH2(10V/div)
gs2:CH2(10V/div)

vvCrCr:CH3(5V/div)
:CH3(5V/div)
vCrv:CH3(5V/div)
Cr:CH3(5V/div)

iCr:CH4(1A/div)
iCr:CH4(1A/div)
iCr:CH4(1A/div)
iCr:CH4(1A/div)

2.5μs 2.5μs
2.5μs 2.5μs
(c) (d)
(c) (d)
Figure 11. Measured waveforms of vgs1, vgs2, vCr, and iCr at input 24 V under (a) 10% load; (b) 20%
Figure11.
Figure Measured waveforms
11.Measured
load; (c) half
waveforms of ofvvgs1
load; and (d) full load.
, v gs2,, v
gs1, vgs2
vCr , and i Cr at
Cr, and iCr
at input
input 24
24VVunder
under(a)(a)10% load;
10% (b)(b)
load; 20%20%
load;(c)
load; (c)half
halfload;
load;and
and (d)
(d) full
full load.
load.

vgs1:CH1(20V/div) vgs1:CH1(20V/div)
vgs1:CH1(20V/div) vgs1:CH1(20V/div)

vgs2:CH2(10V/div) vgs2:CH2(10V/div)
vgs2:CH2(10V/div) vgs2:CH2(10V/div)
vCr:CH3(5V/div) vCr:CH3(5V/div)
vCr:CH3(5V/div) vCr:CH3(5V/div)

iCr:CH4(1A/div) iCr:CH4(1A/div)

iCr:CH4(1A/div) iCr:CH4(1A/div)

2.5μs 2.5μs
(a) 2.5μs
(b) 2.5μs
(a) (b)

Figure 12. Cont.

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vgs1:CH1(20V/div) vgs1:CH1(20V/div)
vgs1:CH1(20V/div) vgs1:CH1(20V/div)

vgs2:CH2(10V/div)
vgs2:CH2(10V/div) vgs2:CH2(10V/div)
vgs2:CH2(10V/div)

vCr:CH3(5V/div)
vCr:CH3(5V/div) vCr:CH3(5V/div)
vCr:CH3(5V/div)

iCr:CH4(1A/div)
iCr:CH4(1A/div) iCr:CH4(1A/div)
iCr:CH4(1A/div)

2.5μs 2.5μs
2.5μs 2.5μs
(c) (d)
(c) (d)
Figure 12. Measured waveforms of vgs1, vgs2, vCr, and iCr at input 48 V under (a) 10% load; (b) 20%
Figure 12. Measured
Figure 12. Measuredwaveforms
waveformsof ofvvgs1
gs1,, v
vgs2 vCrCr, ,and
gs2,, v andiiCrCratatinput
input48
48VV under
under (a)
(a) 10%
10% load;
load; (b)
(b) 20%
20%
load; (c) half load; and (d) full load.
load;
load; (c)
(c) half
half load;
load; and
and (d)
(d) full
full load.
load.

vgs1:CH1(20V/div) vgs1:CH1(20V/div)
vgs1:CH1(20V/div) vgs1:CH1(20V/div)

vgs3:CH2(10V/div)
vgs3:CH2(10V/div) vgs3:CH2(10V/div)
vgs3:CH2(10V/div)

vds3:CH3(20V/div) vds3:CH3(20V/div)
vds3:CH3(20V/div) vds3:CH3(20V/div)

iN2:CH4(10A/div) iN2:CH4(10A/div)
iN2:CH4(10A/div) iN2:CH4(10A/div)

2.5μs 2.5μs
2.5μs 2.5μs
(a) (b)
(a) (b)

vgs1:CH1(20V/div) vgs1:CH1(20V/div)
vgs1:CH1(20V/div) vgs1:CH1(20V/div)

vgs3:CH2(10V/div) vgs3:CH2(10V/div)
vgs3:CH2(10V/div) vgs3:CH2(10V/div)

vds3:CH3(20V/div) vds3:CH3(20V/div)
vds3:CH3(20V/div) vds3:CH3(20V/div)

iN2:CH4(10A/div) iN2:CH4(10A/div)
iN2:CH4(10A/div) iN2:CH4(10A/div)
2.5μs 2.5μs
2.5μs 2.5μs
(c) (d)
(c) (d)
Figure 13. Measured waveforms of vgs1, vgs2, vds3, and iN2 at input 24 V under (a) 10% load; (b) 20%
Figure 13. Measured
Measuredwaveforms
waveformsofofvvgs1,, vvgs2,, vvds3, ,and iN2 at input 24 V under (a) 10% load; (b) 20%
Figure
load; (c)13.
50% load; and gs1 gs2 ds3 and iN2 at input 24 V under (a) 10% load; (b) 20%
(d) 100% load.
load; (c) 50% load; and (d) 100% load.
load; (c) 50% load; and (d) 100% load.
Appl. Sci. 2022, 12, x FOR PEER REVIEW 19 of 24
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vgs1:CH1(20V/div) vgs1:CH1(20V/div)
vgs1:CH1(20V/div) vgs1:CH1(20V/div)

vgs3:CH2(10V/div) vgs3:CH2(10V/div)
vgs3:CH2(10V/div) vgs3:CH2(10V/div)

vds3:CH3(20V/div) vds3:CH3(20V/div)
vds3:CH3(20V/div)
vds3:CH3(20V/div)

iN2iN2
:CH4(10A/div)
:CH4(10A/div) iiN2
N2:CH4(10A/div)
:CH4(10A/div)

2.5μs
2.5μs 2.5μs
2.5μs
(a)
(a) (b)
(b)

vgs1
vgs1
:CH1(20V/div)
:CH1(20V/div) vgs1 :CH1(20V/div)
gs1:CH1(20V/div)

vgs3
vgs3
:CH2(10V/div)
:CH2(10V/div) vgs3 :CH2(10V/div)
gs3:CH2(10V/div)

vvds3
ds3:CH3(20V/div)
:CH3(20V/div)
vds3
vds3 :CH3(20V/div)
:CH3(20V/div)

iN2iN2 :CH4(10A/div)
:CH4(10A/div) iiN2
N2:CH4(10A/div)
:CH4(10A/div)

2.5μs
2.5μs 2.5μs
2.5μs
(c)
(c) (d)
(d)
Figure 14. Measured waveformsof ofvvvgs1
gs1, vgs2, vds3, and iN2 at input 48 V under (a) 10% load; (b) 20%
Figure
Figure Measuredwaveforms
14.Measured
14. waveforms of gs1 ,, vvgs2
gs2, v
vds3 and iiN2
ds3, and N2 at
at input
input4848VVunder
under(a)(a)
10%10%
load; (b) 20%
load; (b) 20%
load;
load; (c) 50%
(c)(c)
load; 50% load;
50%load; and
load;and (d)
and(d) 100%
(d) 100% load.
load.
100% load.
+30 180 +30 180
+30 180 +30 180
+20 135 +20 135
+20 135 +20 135
+10 90 +10 90
+10 90 +10 90
GM= –15.5 dB
Phase(deg)

Phase(deg)

0 GM= –15.5 dB 45 0 45
Gain(dB)

Gain(dB)

PM=74.4°
Phase(deg)

Phase(deg)

0 PM=74.2° 45 0 45
Gain(dB)

Gain(dB)

PM=74.2° PM=74.4° GM= –16.8 dB

−10 0 −10 0
GM= –16.8 dB
−10 fc=3.01 kHz 0 −10 fc=2.59 kHz 0
−20 fc=3.01 kHz −45 −20
fc=2.59 kHz −45
−20 −45 −20 −45
−30 −90 −30 −90
−30 −90 −30 −90
−40 −135 −40 −135
−40 −135 −40 −135
−50 −180 −50 −180
500 1k 2k 3k 5k 10k 20k 30k 40k
−180 500 1k 2k 3k 5k 10k 20k 30k 40k −180
−50 −50
500 1k 2k Frequency(Hz)
3k 5k 10k 20k 30k 40k 500 1k 2k Frequency(Hz)
3k 5k 10k 20k 30k 40k
Frequency(Hz) Frequency(Hz)
(a) (b)
(a) (b)

Figure 15. Cont.

Appl. Sci. 2022,
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+30 180 +40 180

+30 180 +40 180

+20 135 +30 135

+20 135 +30 135

+10 90 +20 90
+10 90 +20 PM=73.5° 90
PM=73.5°

Phase(deg)

Phase(deg)
0 45 +10 45
Gain(dB)

Gain(dB)
Phase(deg)

Phase(deg)
0 45 +10 45
Gain(dB)

Gain(dB)
PM=47.2° GM= –10.3 dB
PM=47.2° GM= –10.3 dB
−10 0 0 0
−10 0 0 fc=3.28 kHz 0
fc=4.38 kHz fc=3.28 kHz
−20
fc=4.38 kHz −45 −10 −45
−20 −45 −10 −45

−30 −90 −20 GM= –13.6 dB −90

−30 −90 −20 GM= –13.6 dB −90

−40 −135 −30 −135

−40 −135 −30 −135

−50 −180 −40 −180

−50 500 1k 2k 3k 5k 10k 20k 30k 40k−180 −40 500 1k 2k 3k 5k 10k 20k 30k 40k−180
500 1k 2k 3k 5k
Frequency(Hz)10k 20k 30k 40k 500 1k 2k 3k 5k
Frequency(Hz)10k 20k 30k 40k
Frequency(Hz) Frequency(Hz)
(c)
(c) (d)
(d)
Figure 15.
Figure
Figure Measured
15.15. Measured
Measured curves
curvesof
curves ofofgain
gainmargin
gain marginand
margin and phase
and phase margin
phase margin under
marginunder
under(a)(a) 10%
(a)10% load
loadatat
10%load input
input
at 2424
input V;V;
24 V; (b)
(b)
full load
full(b) at
fullat
load input
load 24 V;
at input
input (c)
24 V;24(c) 10%
V;10% load
(c) 10% at
load
load input
at at 48
input
input V; and
4848V;V;and (d)
and(d) full load
(d) full load at input
loadatatinput 48 V.
input4848V.V.

V
VO(ac) :CH1(1V/div) V
VO(ac) :CH1(1V/div)
O(ac):CH1(1V/div) O(ac):CH1(1V/div)

vvCr(ac):CH2(2V/div) vvCr(ac):CH2(2V/div)
Cr(ac):CH2(2V/div) Cr(ac):CH2(2V/div)

vCF:CH3(5V/div) vCF:CH3(5V/div)
vCF:CH3(5V/div) vCF:CH3(5V/div)

iiCr:CH4(1A/div) iiCr:CH4(1A/div)
Cr:CH4(1A/div) Cr:CH4(1A/div)

250 μs 250 μs
250 μs 250 μs
(a)
(a) (b)
(b)
V
VO(ac):CH1(1V/div) V
:CH1(1V/div)
O(ac) VO(ac):CH1(1V/div)
:CH1(1V/div)
O(ac)

vvCr(ac):CH2(2V/div) vvCr(ac):CH2(2V/div)
Cr(ac):CH2(2V/div) Cr(ac):CH2(2V/div)

vCF:CH3(5V/div) vCF:CH3(5V/div)
vCF:CH3(5V/div) vCF:CH3(5V/div)

iiCr:CH4(1A/div) iiCr:CH4(1A/div)
Cr:CH4(1A/div) Cr:CH4(1A/div)

250 μs 250 μs
250 μs 250 μs
(c)
(c) (d)
(d)

Figure 16. Cont.

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VO(ac):CH1(1V/div) VO(ac):CH1(1V/div)

vCr(ac):CH2(2V/div) vCr(ac):CH2(2V/div)

vCF:CH3(5V/div) vCF:CH3(5V/div)

iCr:CH4(1A/div) iCr:CH4(1A/div)

250 μs 250 μs
(e) (f)
Figure 16.
Figure 16. Measured
Measured transient
transient waveforms
waveformsofofVVo
o ripple, vCr ripple, vCF, and iCr: (a) from 50% to 100%
ripple, vCr ripple, vCF, and iCr: (a) from 50% to
load at 24 V input; (b) from 100% to 50% load at 24 V input; (c) from 50% to 100% load at 36 V input;
100% load at 24 V input; (b) from 100% to 50% load at 24 V input; (c) from 50% to 100% load at 36 V
(d) from 100% to 50% load at 36 V input; (e) from 50 to 100% load at 48 V input; and (f) From 100%
input; (d) from 100% to 50% load at 36 V input; (e) from 50 to 100% load at 48 V input; and (f) From
to 50% load at 48 V input.
100% to 50% load at 48 V input.

Table 3. Measured results of phase margin

Inputand gain margin.
Test Condition Phase Margin Gain Margin Crossover Frequency
L
10% load at input 24 V 74.2◦ 15.5 dB 3.01 kHz
Full load at input 24 V 74.4◦ 16.8 dB 2.59 kHz
10% load at input 48 V Cin 47.2◦ 10.3 dB
Co 4.38 kHz
SR IC Q3
Full load at input 48 V 73.5◦ 13.6 dB Output 3.28 kHz

Table 4. Comparison of the proposedTo

method
FPGA and other topologies.

Proposed AHB (a)

Conventional AHB
Item LLC ACF
Flyback Flyback
Active switch Output
2/1 2/1 HB 2/2 2/1
Primary side/secondary side driver
frequency
Modulation PFM PWM Q2 PWM
modulation
Voltage stress on switches medium
FPGA medium medium high
power
Input voltage range medium Q1
narrow narrow medium
ZVS range at light load Input Cr medium
good medium medium
(without burst mode)
(b)
Frequency variation range medium constant high constant
Figure 17. Photographs of the proposed prototype (a) view of top side; and (b) view of bottom
Output ripple current high high medium high
side.

Table 3. Measured results of phase margin and gain margin.

Test Condition Phase Margin Gain Margin Crossover Frequency

10% load at input 24 V 74.2° 15.5 dB 3.01 kHz
Full load at input 24 V 74.4° 16.8 dB 2.59 kHz
10% load at input 48 V 47.2° 10.3 dB 4.38 kHz
Full load at input 48 V 73.5° 13.6 dB 3.28 kHz
 250 μs 250 μs
(e) (f)
Figure 16. Measured transient waveforms of Vo ripple, vCr ripple, vCF, and iCr: (a) from 50% to 100%
load
Appl. Sci. 2022, 12, at 24 V input; (b) from 100% to 50% load at 24 V input; (c) from 50% to 100% load at 36 V input;
6685 21 of 23
(d) from 100% to 50% load at 36 V input; (e) from 50 to 100% load at 48 V input; and (f) From 100%
to 50% load at 48 V input.

Input

Cin Co
SR IC Q3
Output

To FPGA
(a)

HB
Output
driver

Q2

FPGA
power
Q1

Input Cr
(b)
Figure 17. Photographs
Figureof17.
thePhotographs
proposed prototype (a) viewprototype
of the proposed of top side;
(a)and (b)ofview
view of bottom
top side; and (b) view of bottom side.
side.
5. Conclusions
Table 3. Measured results
Thisof phase
papermargin and an
proposes gainAHB
margin.
flyback converter derived from a resonant high step-
Test Condition down
Phase converter. For applications
Margin with wide input
Gain Margin voltage Frequency
Crossover range, this circuit features the
same low stress on all active switches as an LLC converter with fewer components and less
10% load at input 24 V 74.2° 15.5 dB 3.01 kHz
frequency variation than an LLC converter. Compared to the ACF converter, the proposed
Full load at input 24 V 74.4° 16.8 dB 2.59 kHz
AHB flyback has a similar wide input voltage range with ZVS turn-on, but lower voltage
10% load at input 48 V 47.2°on all active switches.10.3
stress dB the system performance
Finally, 4.38 kHz
and stability are verified with
Full load at input 48 V 73.5°
the prototype circuit. 13.6 dB 3.28 kHz

Funding: This research was supported by the Ministry of Science and Technology, Taiwan, under the
Grant Number: MOST 109-2222-E-167-003-MY3.
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: No new data were created or analyzed in this study. Data sharing is
not applicable to this article.
Conflicts of Interest: The author declares no conflict of interest.

Abbreviations
Symbol and Variable Definition
Vin Input voltage
VO Output voltage
L Main coupled inductor
Lm Magnetizing inductor of main coupled inductor
Q1 , Q2 Main switch
Q3 Synchronous Rectifier switch
CO Output capacitor
Coss1 , Coss2 , Coss3 Output capacitance of Q1 , Q2 , and Q3 , respectively
Qrr3 Reverse recovery charge of Q3
Lr Resonance inductor
Appl. Sci. 2022, 12, 6685 22 of 23

Cr Input capacitor
fsw Switching frequency
Ts Switching period
fsw (24V) , fsw (48V) Switching frequency at input voltages of 24 V and 48 V, respectively
D Duty cycle
D(24V) , D(48V) Duty cycle at input voltages of 24 V and 48 V, respectively
Ton Conduction time of Q1
Ton (24V) , Ton (48V) Conduction time of Q1 at input voltages of 24 V and 48 V, respectively
Toff Disconduction time of Q1
iLm Current of Lm
iN1 , iN2 Current of N1 and N2 , respectively
iLr Current of Lr
iLr(pk) Peak current of Lr
ids1 , ids2 , ids3 Drain-source current of Q1 , Q2 , and Q3 , respectively
vds1 , vds2 , vds3 Drain-source voltage of Q1 , Q2 , and Q3 , respectively
iCr Current of Cr
vCr Voltage across Cr
Z1 Impedance of resonant tank of Cr , Lm , and Lr
Z2 Impedance of resonant tank of Cr , Coss1 , Coss2 , Lm , and Lr
Z3 Impedance of resonant tank of Cr and Lr
Z4 Impedance of resonant tank of Lr and Cds3
ω r1 Angular frequency of resonant tank of Cr , Lm , and Lr
ω r2 Angular frequency of resonant tank of Cr , Coss1 , Coss2 , Lm , and Lr
ω r3 Angular frequency of resonant tank of Cr and Lr
ω r4 Angular frequency of resonant tank of Lr and Cds3
Tr Resonant period of Cr and Lr
fmax , fmin Maximum and minimum of fsw , respectively
∆fsw Variation rang of fsw
Ae Magnetic cross sectional area of L
Le Mean magnetic path length of L
Bmax Maximum flux density of Lm
VCr Average value of vCr
VCr(24V) , VCr(48V) Average value of vCr at input voltage 24 V and 48 V, respectively
vCF Current reference of the inner current-loop controller
Vo (AC) AC coupled signals of Vo
vCr(AC) AC coupled signals of vCr
Vref, iref Reference of the voltage loop compensator and the current loop, respectively
verr Feedback error of the voltage loop

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