NATIONAL UNIVERSITY OF TECHNOLOGY (NUTECH)

DEPARTMENT OF ELECTRICAL ENGINEERING

EE-1002: Digital Logic Design Lab

Batch: 2021-2025 Semester: III Session: Fall-2022

EXPERIMENT NO 12
To Verify Different types of Flip Flops

Student Name & Reg No: ________________________________________________________

Date of Experiment: ________________________________________________________

Affective Domain Rubric Based Assessment

Levels of Achievement
Unacceptable Just acceptable Basic Good Excellent Marks
(1) (2) (3) (4) (5)
I. Adherence to Safety
Procedures
II. Attitude and Goal Setting
III. Individual & Group
Engagement
Psychomotor Domain Rubric Based Assessment

Levels of Achievement
Unacceptable Just acceptable Basic Good Excellent Marks
(1) (2) (3) (4) (5)
1. Ability to conduct an experiment
II. Implementation and Results

Lab Report Rubric Based Assessment

Levels of Achievement
Unacceptable Just acceptable Basic Good Excellent Marks
(1) (2) (3) (4) (5)
I. Data Analysis and Calculations
II. Results and Conclusion

Submitted to: ________________________________________________________

Instructor’s Signature: ________________________________________________________

 NATIONAL UNIVERSITY OF TECHNOLOGY (NUTECH)
DEPARTMENT OF ELECTRICAL ENGINEERING

EXPERIMENT# 12. To Verify Different types of Flip Flops

Objective:
 To study R-S, J-K, D and T flip-flops using IC 7476.

Components

 Bread Board  Leads  Digital Trainer

1. LS7402 2. LS7400 3. LS7476

Theory
Flip-flops are the basic building blocks of sequential circuits. The clocked FFs change their o/p state depending
upon i/p's at certain interval of time synchronized with the clock pulse applied to it.
Different types of FFs are S-R, J-K, D& T. Their operations are described by the respective truth tables. MSI
chip 7476 incorporates two negative edge triggered Master–Slave JK flip- flops. The J-K flip-flop can be
converted to D & T flip-flop.

Clocked SR Flip-Flop

The clocked RS flip-flop is like an SR flip-flop but with an extra third input of a standard clock pulseCLK.

Truth Table

Clk S R Q
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
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DEPARTMENT OF ELECTRICAL ENGINEERING

JK Flip-Flop

The JK flip-flop is an SRFF with some additional gating logic on the inputs which serve to overcomethe
SR=11 prohibited state in the SRFF. A simple JKFF is illustrated below

The block symbol for a J-K flip-flop is a whole lot less frightening than its internal circuitry, and justlike
the S-R and D flip-flops, J-K flip-flops come in two clock varieties (negative and positive edge-triggered)

Truth Table
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DEPARTMENT OF ELECTRICAL ENGINEERING

T Flip-Flop Using JK Flip-Flop

In case of T flip flop, if the T input is high, the T flip-flop changes state ("toggles") whenever the clockinput
is strobed. If the T input is low, the flip-flop holds the previous value.
T Flip flop can be constructed using JK flip flop as shown in diagram below.

Truth Table

D Flip-Flop Using JK Flip-Flop

The delay flip-flop (DFF) is unique in that it only has one external input along with a clock input.The
logic symbol for this flip-flip is given below
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DEPARTMENT OF ELECTRICAL ENGINEERING

D Flip flop can be constructed using JK flip flop as shown in diagram below.

Truth Table

Pin Configuration of 7476

 NATIONAL UNIVERSITY OF TECHNOLOGY (NUTECH)
DEPARTMENT OF ELECTRICAL ENGINEERING

Q. List the differences between a latch and a flip flop?

Q. Define truth table and excitation table of a flip flop?

Q. State the types of triggering used in a flip flop?

 NATIONAL UNIVERSITY OF TECHNOLOGY (NUTECH)
DEPARTMENT OF ELECTRICAL ENGINEERING

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