Chapter-16 Memory Organization

B.
Tech 5th SEMESTER – CSE 2

COMPUTER ORGANIZATION &
ARCHITECTURE
CHAPTER – 16
Memory organization
(Refer Chapter-12 Memory Organization From The Book M. Morris Mano)
Prepared By:
Prof. Smita Dash ( Asst. Professor, Dept. of CSE)
PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 1

WHAT IS A MEMORY?
• A memory unit is the collection of storage units
or devices together. The memory unit stores the
binary information in the form of bits.
2 categories:
• Volatile Memory: This loses its data, when power
is switched off.
• Non-Volatile Memory: This is a permanent

storage and does not lose any data when power
is switched off.
CRITERIA TAKEN INTO
CONSIDERATION WHILE DECIDING
WHICH MEMORY IS TO BE USED:
• Cost
• Speed
• Memory access time
• Data transfer rate
• Reliability
PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)
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MEMORY HIERARCHY

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MEMORY HIERARCHY PROPERTIES
• Coherence Property
• The coherence property requires that copies

of the same information item at successive
memory levels be consistent. If a word is
modified in the cache, copies of that must be
updated immediately or eventually at all
higher levels.
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• locality of reference, also known as
the principle of locality, is the tendency of a
processor to access the same set of memory
locations repetitively over a short period of
time.

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Types of Locality
• Temporal locality
If at one point a particular memory location is
referenced, then it is likely that the same location
will be referenced again in the near future.
• Spatial locality
If a particular storage location is referenced at a
particular time, then it is likely that nearby
memory locations will be referenced in the near
future.
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• Sequential locality
✓ In a program, the execution of instructions
normally follows a sequential order (in-order
execution) unless branch instructions cause the
control to go out- of order (out-of order
execution).
✓ These sequential instructions reside normally in a

cluster of memory close to one another.
✓ This cluster is accessed again and again due to in-

order execution of the sequential instructions in
the program giving rise to sequential locality.
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MAIN MEMORY & TYPES

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RAM

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Types Of RAM

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ROM

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RAM & ROM CHIPS
Fig:1 Block Diagram of RAM Chip & Fig:2 Function Table

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SRAM CHIP vs DRAM CHIP

WORKING OF AN SRAM CELL

• To generate stable logic state, four transistors (T1, T2,
T3, T4) are organized in a cross-connected way. For
generating logic state 1, node C1 is high, and C2 is low;
in this state, T1 and T4 are off, and T2 and T3 are on.
For logic state 0, junction C1 is low, and C2 is high; in
the given state T1 and T4 are on, and T2 and T3 are off.
Both states are stable until the direct current (dc)
voltage is applied.
• The SRAM address line is operated for opening and

closing the switch and to control the T5 and T6
transistors permitting to read and write. For read
operation the signal is applied to these address line
then T5 and T6 gets on, and the bit value is read from
line B. For the write operation, the signal is employed
to B bit line, and its complement is applied to B’.

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WORKING OF A DRAM CELL

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• At the time of reading and writing the bit value from the cell, the
address line is activated. The transistor present in the circuitry
behaves as a switch that is closed(allowing current to flow) if a
voltage is applied to the address line and open (no current flows) if
no voltage is applied to the address line. For the write operation, a
voltage signal is employed to the bit line where high voltage shows
1, and low voltage indicates 0. A signal is then used to the address
line which enables transferring of the charge to the capacitor.
• When the address line is chosen for executing read operation, the
transistor turns on and the charge stored on the capacitor is
supplied out onto a bit line and to a sense amplifier.
• The sense amplifier specifies whether the cell contains a logic 1 or

logic 2 by comparing the capacitor voltage to a reference value. The
reading of the cell results in discharging of the capacitor, which
must be restored to complete the operation. Even though a DRAM
is basically an analog device and used to store the single bit (i.e.,
0,1).

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ASSOCIATIVE MEMORY

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Hardware Organization

CACHE MEMORY

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Cache Operation- Overview
• CPU requests contents of memory location
• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main
memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of
main memory is in each cache slot
Performance of a Cache
• The performance of cache memory is frequently
measured in terms of quantity called hit ratio.
• When the CPU refers to the memory and finds
the word in the cache, it is said to produce a hit.
• If the word is not found in the cache , it is in main
memory and it counts a miss.
• The ratio of the number of hits divided by the
total CPU references to the memory (hits plus
misses) is the hit ratio.
Hit Ratio

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Cache Read Operation- Flowchart

CACHE MAPPING
• WHAT IS MAPPING?
The basic characteristics of a cache memory is
its fast access time. Therefore, very little or no
time must be wasted when searching the
word from cache. The transformation of data
from main memory to cache memory is
referred to as memory mapping process.

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Types of Mapping
– Associative Mapping
– Direct Mapping
– Set- Associative mapping

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1. ASSOCIATIVE MAPPING

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2. DIRECT MAPPING

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3. SET-ASSOCIATIVE MAPPING
PROF. SMITA DASH (ASST. PROFESSOR.,

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DEPT. OF CSE)
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DEPT. OF CSE)
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DEPT. OF CSE)
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DEPT. OF CSE)
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DEPT. OF CSE)
Replacement Algorithms in Cache
Memory
• Replacement algorithms are used when there
are no available space in the cache in which to
place the data.

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DEPT. OF CSE)
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Interleaved Memory
• Abstraction is one the most important aspect of

computing. It is widely implemented Practice in
the Computational field.
• Memory Interleaving is less or More an
Abstraction technique. Though its a bit different
from Abstraction. It is a Technique which divides
memory into a number of modules such that
Successive words in the address space are placed
in the Different module.
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DEPT. OF CSE)
Interleaved Memory (contd..)
• Consecutive Word in a Module:

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DEPT. OF CSE)
• Let us assume 16 Data’s to be Transferred to the
Four Module. Where Module 00 be Module 1,
Module 01 be Module 2, Module 10 be Module 3
& Module 11 be Module 4. Also 10, 20, 30….130
are the data to be transferred.
• From the figure above in Module 1, 10 [Data] is
transferred then 20, 30 & finally, 40 which are the
Data. That means the data are added
consecutively in the Module till its max capacity.
• Most significant bit (MSB) provides the Address
of the Module & least significant bit (LSB)
provides the address of the data in the module.
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Consecutive Word in Consecutive Module

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VIRTUAL MEMORY

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ADRESS SPACE & MEMORY SPACE

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THANK YOU

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B.

Tech 5th SEMESTER – CSE 2

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 1

• Non-Volatile Memory: This is a permanent

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 4

• The coherence property requires that copies

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

✓ These sequential instructions reside normally in a

✓ This cluster is accessed again and again due to in-

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 16

Fig:1 Block Diagram of RAM Chip & Fig:2 Function Table

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 21

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 22

• The SRAM address line is operated for opening and

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

• The sense amplifier specifies whether the cell contains a logic 1 or

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 28

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 29

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE) 36

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR., DEPT. OF CSE)

PROF. SMITA DASH (ASST. PROFESSOR.,

PROF. SMITA DASH (ASST. PROFESSOR.,

• Abstraction is one the most important aspect of

PROF. SMITA DASH (ASST. PROFESSOR.,

PROF. SMITA DASH (ASST. PROFESSOR.,

PROF. SMITA DASH (ASST. PROFESSOR.,

PROF. SMITA DASH (ASST. PROFESSOR.,

PROF. SMITA DASH (ASST. PROFESSOR.,

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