Bi-directional CLLC Converter with Synchronous
Rectification for Plug-in Electric Vehicles
Shenli Zou, Student Member, IEEE, Jiangheng Lu, Student Member, IEEE, Ayan Mallik, Student Member,
IEEE and Alireza Khaligh, Senior Member, IEEE
Maryland Power Electronics Laboratory (MPEL), Electrical and Computer Engineering Department;
Institute for Systems Research; University of Maryland, College Park;
Email: khaligh@ece.umd.edu; URL: http://khaligh.umd.edu/
Abstract–– This paper presents an innovative technique for
synchronous rectification in a bi-directional CLLC converter
with an integrated transformer for plug-in electric vehicle (EV)
applications. To improve the efficiency and power density, the
integrated transformer is introduced and simulated using
Finite Element Analysis (FEA). In addition, synchronous
rectification is implemented by controlling the turn-on and
turn-off timings based on the phase difference between
primary gate pulse and secondary resonant current.
Furthermore, a simplified closed loop design is discussed and
implemented on a digital signal processor (TMS320F28335).
The effectiveness of the control loop is verified through a
3.3kW proof-of-concept prototype with a peak efficiency of
97.5%.
Index Terms–– Bi-directional converter, electric vehicles (EVs),
integrated transformer, phase control.
I. INTRODUCTION
In selection of the DC/DC stage topology for traditional
onboard chargers, LLC resonant converter is a suitable
candidate for unidirectional grid-to-vehicle (G2V) chargers
due to its high efficiency and wide output range [1-2].
Moreover, vehicle-to-grid (V2G) has drawn significant
attention due to the flexibility for feeding electricity back
into the grid for load leveling purposes [3]. Thus, CLLC and
Dual Active Bridge (DAB) are examined as two most
commonly used DC/DC converter topologies for
bidirectional EV charger applications [4-8]. However, the
soft switching region of a conventional DAB converter is
only limited to a narrow output voltage range [9]. Therefore,
researchers have proposed an improved DAB control
strategy in [10] to improve efficiency, through implementing
a modified modulation index in one of the two bridge legs
and a phase shift between the primary and secondary
voltages. In comparison to the DAB, a bi-directional CLLC
converter can be operated in a wide output range [11]. Many
recent studies have been conducted towards this topology.
Research in [12] proposes a maximum efficiency tracking
methodology for a CLLC converter; however, it does not
present any experimental results to solidify its claim. In [13],
the design criteria are presented for a CLLC converter to get
an optimized solution. However, the lack of synchronous
rectification in secondary side results in high conduction loss.
In [14], coupling capacitors are implemented to eliminate the
Digital ObMect Identi¿er 10.1109/TIA.201.23430
0093-9994 ‹ 201 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
circulating loss in the resonant tank for wireless charging
applications. Nevertheless, none of the aforementioned
studies provides any details on the closed-loop design and
system stability analyses.
To overcome the aforementioned considerations, this
paper introduces an innovative technique for achieving
synchronous rectification in a bi-directional 3.3kW CLLC
converter for onboard charger applications. In addition, the
paper presents the detailed design and analyses to meet the
requirement of wide range output voltage and to ensure soft-
switching for efficiency improvement. Moreover, to achieve
the constant voltage (CV) and constant current (CC)
charging for battery, a PI-based control strategy is
implemented in digital domain. This manuscript is
organized as follows: The CLLC topology and its voltage
gain characteristics are analyzed in Section II. Design
methodology of the power stage is discussed in Section III.
Section IV presents the design methodology of control stage
including frequency modulation and the proposed
synchronous rectification approach. The simulation and
experimental results are presented in Section V. Section VI
puts forward the conclusions with relevant discussions.
II. DC CHARACTERISTICS OF CLLC CONVERTER
Fig. 1 shows the topology of a bi-directional half-bridge
CLLC resonant converter and the power flow directions of
charging mode (G2V) and discharging mode (V2G). The
topology utilizes an integrated transformer for offering
galvanic isolation between the primary and secondary sides.
‫ܮ‬௠ , ‫ܮ‬௥ଵ and ‫ܮ‬௥ଶ are the magnetizing inductance, primary
side leakage inductance and secondary side leakage
inductance of the transformer, respectively. ‫ܥ‬ଵ and ‫ܥ‬ଶ play
the role of the half bridge DC capacitors and the resonant
capacitors, simultaneously.
Fig. 1. Topology of half-bridge CLLC converter.
A. Gain Analysis The gain function of CLLC converter ‫ீܩ‬ଶ௏ ሺ߱ሻ can be
derived from Eq. (6) as follows.
Equivalent circuit of a half-bridge CLLC converter in
‫ீܩ‬ଶ௏ ሺ߱ሻ ൌ ȁ‫ܪ‬ሺ݆߱ሻȁ ൌ
charging mode is shown in Fig. 2. Assume that ‘n’ denotes ଵ ଵ
the turns ratio of the transformer. Using First Harmonic మ
(8)
௡
ටሺభି భ ାଵሻమ ାቂ భ ቀೌା భ ାభ ାଵቁொ೎ ିఠቀೌା௔ାଵቁொ೎ ିೂ೎ భ ቃ
Approximation (FHA), equivalent load resistance (Re,c) can ೖ ೖഘమ ഘ ೖ ೖ್ ್ య
ೖ ೖ್ ഘ
௅೘ ௡మ ௅ ஼మ
be expressed as follows [11]. where, ݇ ൌ ǡܽ ൌ ೝమ
ǡ ܾൌ (9)
ଶ௡మ ௅ೝభ ௅ೝభ ௡మ ஼భ
ܴ௘ǡ௖ ൌ మ ܴ௢ (1) There are minor differences between the gain
గ
where, ܴ௢ is the load resistance in G2V mode. expression in G2V and V2G modes. For V2G mode, the
general transfer function ‫ܪ‬௥ ሺ݆߱ሻ can be determined using
superposition and expressed as follows.
ೕഘಽ೘
௡௏೚ೠ೟ ሺ௝ఠሻ ோ೐ǡೝ ோయ ȀȀ
೙మ
‫ܪ‬௥ ሺ݆߱ሻ ൌ ൌ భ ೕഘಽ (10)
௏೔೙ሺ௝ఠሻ ோయ  ௝ఠ௅ೝమ ା ାோయ ȀȀ మ೘
ೕഘమ಴మ ೙
௅ೝభ ଵ
Fig. 2. Equivalent circuit of the CLLC converter in charging mode. where, ܴଷ ൌ ܴ௘ǡ௥ ൅ ݆߱ ൅ (11)
௡మ ௝ఠ௡మ ଶ஼భ
All the equivalent resonant parameters in charging
mode can be referred to the primary side as follows. The gain function of CLLC converter ‫ܩ‬௏ଶீ ሺ߱ሻ can be
ଶ஼ derived from Eq. (6) as follows.
‫ܮ‬ᇱ௥ଶ ൌ ݊ଶ ‫ܮ‬௥ଶ ǡ ‫ܥ‬௥ଵ ൌ ʹ‫ܥ‬ଵ ǡ ‫ܥ‬௥ଶ ൌ  మమ  (2) ‫ܩ‬௏ଶீ ሺ߱ሻ ൌ ȁ‫ܪ‬௥ ሺ݆߱ሻȁ ൌ
௡
In addition, the normalized frequency and quality factor ଵ
(12)
మ
are defined as follows. ටሺభି భ ାଵሻమ ାቂ భ ቀೌା భ ା భାଵቁொೝ ିఠቀೌା௔ାଵቁொೝ ିೂೝ భ ቃ
మ
ೖ ೖഘ ഘ ೖ ೖ್ ್ య
ೖ ೖ್ ഘ
ಽ
ට಴ೝభ ௅೘ ௅ೝభ ௡మ ஼భ
߱ൌ
ఠೞ
ǡ ܳ௖ ൌ  ೝభ
ǡ ߱௥ ൌ 
ଵ
(3) where, ݇ ൌ ǡܽ ൌ ǡ ܾൌ (13)
ఠೝ ோ೐ǡ೎ ௡మ ௅ೝమ ௡మ ௅ೝమ ஼మ
ඥ௅ೝభ ஼ೝభ
where, ߱௥ and ߱௦ denote the resonant frequency and the
switching frequency, respectively. ߱ is the normalized III. DESIGN METHODOLOGY OF THE POWER STAGE
frequency and ܳ௖ is the quality factor in charging mode. A. Design Considerations of Parameters
Equivalent circuit of the half-bridge CLLC converter in
the discharging mode is shown in Fig. 3. Similar to Eq. (1), Resonant frequency ݂௥ is selected 130kHz for G2V
equivalent load resistance (Re,r) in the discharging mode can mode and 100kHz for V2G mode considering the trade-offs
be modeled as Eq. (4). between EMI, efficiency, power density and control
ଶ complexity. Reducing resonant frequency would improve
ܴ௘ǡ௥ ൌ మ మ ܴ௢ᇱ (4)
గ ௡ efficiency due to the reduced copper and iron losses in the
where, ܴ௢ᇱ is the load resistance in V2G mode. transformer. However, it may potentially cause severe EMI
issues and result in degradation of the power density [15].
The nominal input voltage of CLLC converter is 600V
and the nominal load is 52ȍ in G2V. Turns ratio of the
transformer, n, is designed as 20:15 considering 600V input
Fig. 3. Equivalent circuit of CLLC in discharging mode. and 400V output under resonant operation with unity gain.
Similarly, all the equivalent resonant parameters in ‫ீܩ‬ଶ௏ can be designed following the turns ratio and the input
discharging mode are derived as Eq. (5). voltage range, as shown in Eq. (14).
௏ ଵ
௅ ଶ஼
‫ܮ‬ᇱ௥ଵ ൌ ೝభమ ǡ ‫ܥ‬௥ଵ ൌ మభ ǡ ‫ܥ‬௥ଶ ൌ ʹ‫ܥ‬ଶ  ೚ೠ೟ ൌ ൈ ‫ீܩ‬ଶ௏ (14)
௡ ௡ ௏೔೙ ௡
൞ ಽ (5) Therefore, based on the turns ratio, gain range is
ට಴ೝమ
ଵ ೝమ ௅೘ designed to be 0.8 ~ 1.1 and 0.52 ~ 0.98 in charging and
߱௥ ൌ  ǡ ܳ௥ ൌ  ǡ‫ܮ‬ᇱ௠ ൌ
ඥ௅ೝమ ஼ೝమ ோ೐ǡೝ ௡మ discharging modes, respectively, which satisfy the wide
where, ܳ௥ is the quality factor in the discharging mode. range output requirement. To enhance the efficiency over
B. Gain Curves the entire load range, variable DC-link voltage strategy is
adopted instead of fixed DC-link voltage [5, 16]. As shown
The gain of the equivalent circuit using FHA is defined by Fig. 4, by operating the converter at the resonant
as nVo/Vin, which is the gain of the resonant tank without frequency in G2V mode, the HV battery side voltage varies
multiplying the turns ratio of the transformer. For G2V between 300 – 450V with the variable DC-link voltage of
mode, the general transfer function ‫ܪ‬ሺ݆߱ሻ can be 400 – 600V. To satisfy the voltage range requirement, pulse
determined by analyzing Fig. 2 and expressed as follows. frequency modulation (PFM) is implemented to extend the
௡௏ ሺ௝ఠሻ ோ ோమ ȀȀ௝ఠ௅೘
‫ܪ‬ሺ݆߱ሻ ൌ ೚ೠ೟ ൌ ೐ǡ೎ భ (6) gain range. Meanwhile, with the maximum attainable gain
௏೔೙ሺ௝ఠሻ ோమ  ௝ఠ௅ೝభ ା ାோమ ȀȀ௝ఠ௅೘
ೕഘమ಴భ of 0.98 under full load condition, V2G operation is only
ଶ ଵ
where, ܴଶ ൌ ܴ௘ǡ௖ ൅ ݆߱݊ ‫ܮ‬௥ଶ ൅ మ಴ () available when HV battery voltage is greater than 305V to
௝ఠ మమ
೙ meet the minimum DC link voltage requirement. However,
it is worthy to mention that higher maximum gain can be transformer with a singular arrangement of primary side and
obtained by limiting the power when HV battery voltage secondary side. As shown in Fig. 6, the trajectory of the
drops towards lower end (250V). This can ensure the V2G leakage flux path substantially contributes to the leakage
operation is achievable across the entire HV battery voltage inductance. In fact, the air gap between the central legs of
range. two E cores and the gaps among three windings can be
DC link
voltage
Battery Gain
420V 0.93
Battery DC link voltage Gain
550V 0.98 adjusted to precisely set the leakage and magnetizing
inductances. It is important to mention that the distance of
600V 360V 0.8 420V gap between two E cores has less influence on the leakage
inductance in comparison to the gaps between windings. In
330V 1.1 addition, the air gap between the central legs significantly
400V 305V reduces the risk of saturation while the gaps among
250V 0.83 400V 0.98 windings help enhance the insulation safety.
(a) (b) Considering the power rating and the flexibility to
Fig. 4. Mappings for gain range and variable DC-link voltage in (a) G2V
manage the leakage air gap, E65 core with 3F3 material
mode; (b) V2G mode.
In order to reduce the size and weight of magnetic from Ferroxcube is selected. By increasing the number of
components, leakage inductances of the transformer winding turns, flux density is reduced, resulting in less core
windings are utilized as resonant inductors, which loss. Thus, the number of turns in the primary and secondary
physically eliminates the resonant inductors. A list of key sides are designed as 20 and 15, respectively, considering
design parameters for both the charging and discharging the trade-offs among window area, turns ratio, power rating
modes is summarized in Table I. and magnetic inductance requirements. Table II summarizes
Table I. Key design parameters for and their specifications. several key parameter specifications of the integrated
transformer.
Parameters G2V V2G Primary winding
Leakage
Resonant frequency݂௥ (kHz) 130 100 flux path
Gain range 0.8 ~ 1.1 0.52 ~ 0.98 Air
Output voltage range (V) 250 ~ 420 400 ~ 550 gap
Primary resonant capacitance ‫ܥ‬ଵ (݊‫)ܨ‬ 33 Magnetic
Secondary resonant capacitance ‫ܥ‬ଶ (݊‫)ܨ‬  flux path
Primary resonant inductance ‫ܮ‬௥ଵ (ߤ‫)ܪ‬ 21 Secondary winding
Secondary resonant inductance ‫ܮ‬௥ଶ (ߤ‫)ܪ‬ 19 Fig. 6. The winding arrangements of an integrated transformer.
Magnetizing inductance ‫ܮ‬௠ (ߤ‫)ܪ‬ 340 Table II. Parameters of the integrated transformer.
Turns ratio n (Np:Ns) 20:15
Parameters Value
Switch C2M0040120D SiC MOSFET
Turns ratio n (Np:Ns) 20:15
Switch ܴௗ௦ሺ௢௡ሻ (݉ߗ) 40
Core size E65
Body diode forward voltage (V) 3.2
Core material 3F3
Switch reverse recovery time (ns) 54
Leakage air gap (mm) 12
Fig. 5 shows the gain curves in both G2V and V2G Core air gap (mm) 2
modes. To ensure gain requirements at different operating Fig.  shows the results obtained in finite element
points confirming ZVS, the range of switching frequency is analysis (FEA) simulations of the designed integrated
selected from 100kHz to 200kHz. transformer under heavy load and light load. According to
the simulation, maximum magnetic flux Bmax is directed
along the middle column of the core with a magnitude
below saturation flux density level (0.4T [1]). As observed
from the thermal monitoring, the air-gap proximity becomes
one of the major hotspots due to the highest magnetic flux
passing through it. Fig. 8 shows the core loss distributions of
the integrated transformer. From the simulation, the core
Fig. 5. Designed gain curves versus frequency in G2V and V2G modes.
loss is measured as 16W at full power.

B. Design of Electromagnetic Integrated Transformer

In order to minimize the core and winding losses and to
improve power density, an electromagnetic integrated
transformer, shown in Fig. 6 is designed and an airgap is
provided to avoid the flux saturation. In this design, the
primary winding is located on one side of the E cores while
the secondary winding is placed on the other side. The (a) under heavy load (3.3kW). (b) under light load (1kW).
resonant inductances are integrated into a gapped Fig. . Simulated magnetic field of the integrated transformer.

(a) under heavy load (3.3kW). (b) under light load (1kW).
Fig. 8. Simulated core loss distribution of the integrated transformer.
Apart from the magnetic field simulations, the current
density of windings is investigated to obtain the winding
loss considering the eddy effect. The simulated current
density reflects the AC resistance using frequency sweep
mode at 100kHz. Therefore, winding loss can be expressed
as,
ఘ ூ
ܲ௪௜௡ௗ௜௡௚Ǥ௧௢௧௔௟ ൌ ‫ܨ‬ோ ܲ௪௜௡ௗ௜௡௚Ǥ஽஼ ǡ ‫ܨ‬ோ ൌ ೞ೔ ǡ ߩ௖௔௟ ൌ (15)
ఘ೎ೌ೗ ஺೐೑೑
where, ߩ௦௜ is the simulated current density and ‫ܣ‬௘௙௙ is the
As can be seen from Fig. 9, the voltage PI controller
output is multiplied by a sensitive factor to obtain the
required change in the switching frequency. At an instant
when the output voltage is less than the reference value, the
effective switching frequency becomes less than the center
frequency to increase the overall gain and vice-versa
happens. It is noteworthy to mention that the sensitive factor
acts as a common factor to both the proportional and
integral gains, which keeps the controller zero location
intact. However, the equivalent proportional parameter (kp)
increases with a higher sensitivity factor, which in turn
increases the gain-crossover frequency. This helps in
achieving a faster dynamic response upon any load/line
disturbance at the cost of reduced noise susceptibility, which
can be resolved by an appropriate zero selection of the
controller.
From FHA, the output voltage ܸ௢ ሺ‫ݏ‬ሻ is derived as,
ଶ௡మ ோ ௏೔೙
ܸ௢ ሺ‫ݏ‬ሻ ൌ మ ೚ భ ೙మ మ೙మ భ భ
(1)
గ మ ቀ ା௦௅ೝభ ቁାቀ௡ ௦௅ೝమ ା ା ோ೚ቁቂଵା ቀ ା௦௅ೝభ ቁቃ
మೞ಴భ మೞ಴మ ഏమ ೞಽ೘ మೞ಴భ

effective area of Litz wire. ‫ܨ‬ோ is the ratio between AC and Then, the plant transfer function ܶ௣ ሺ‫ݏ‬ሻ can be
DC loss. ߩ௦௜ is simulated current density. Table III represented in Eq. (18).
డ௏೚ ሺ௦ሻ
summarizes the simulated transformer losses and related ܶ௣ ሺ‫ݏ‬ሻ ൌ
డ௦
ൌ
specifications. ೙మ ಽೝమష మ
೙మ
భ మೞ ಴మ
Table III. Simulated transformer losses and related specifications. ଶ௡మ ோ೚ ௏೔೙ మೞమ ಴భ
ି௅ ೝభ ା
ೞయ ಽ೘ ಴భ
గమ ೙మ మ೙మ
మ (18)
Parameters Heavy load Light load ቄቀ
భ
ା௦௅ೝభ ቁାቀ௡మ ௦௅ೝమ ା ା మ ோ೚ ቁቂଵା
భ
ቀ
భ
ା௦௅ೝభ ቁቃቅ
మೞ಴భ మೞ಴మ ഏ ೞಽ೘ మೞ಴భ
Primary ‫ܨ‬ோ 3.04 1.9
As indicated in Fig. 10, system loop gain is defined as,
Secondary ‫ܨ‬ோ 3.22 2.13
Core loss (W) 16 8.1
‫ ܩܮ‬ൌ ‫ܥ‬ሺ‫ݏ‬ሻܶ௣ ሺ‫ݏ‬ሻ (19)
Winding loss (W) 15.1 5.2 Therefore, the closed loop transfer function ݃ሺ‫ݏ‬ሻ of the
PI control system is obtained.
஼ሺ௦ሻ்೛ ሺ௦ሻ
IV. DESIGN METHODOLOGY OF THE CONTROL STAGE ݃ሺ‫ ݏ‬ሻ ൌ ൌ
ଵା஼ሺ௦ሻ்೛ ሺ௦ሻ
ೖ೔
௞೛ ା
A. Closed Loop Control Strategy ೞ
మ (20)
భ ೙మ మ೙మ భ భ
ഏమ ቊ൬మೞ಴ శೞಽೝభ ൰శቆ೙మೞಽೝమశ శ ೃ ቇ൤భశೞಽ ൬ శೞಽೝభ ൰൨ቋ
ೖ೔ భ మೞ಴మ ഏమ ೚ ೘ మೞ಴భ
Frequency modulation [18] as a part of closed loop ௞೛ ା ା
ೞ ೙మ
೙మ ಽೝమష మ
control is implemented to achieve the CV charging of the ‫ ۇ‬భ
మ೙మ ೃ೚ ೇ೔೙ ‫ ۈ‬మ షಽೝభ శ
మೞ ಴మ‫ۊ‬
మೞ ಴భ ೞయ ಽ೘ ಴భ ‫ۋ‬
battery, which is demonstrated in the Fig. 9. Voltage control ‫ۉ‬ ‫ی‬
loop is implemented to regulate the output voltage. As In order to guarantee the system stability using the
indicated by Fig. 9, a general PI compensator is small signal model, all the poles of the closed loop gain
implemented in the feedback loop and the transfer function ݃ሺ‫ݏ‬ሻ should be located in the left-half-plane. Thus, bode
for a PI compensator is given as Eq. (16). plot of this system has been investigated, as shown in Fig.
௞ ௦ା௭ 10. It is clear from the bode plot that the PI controller offers
‫ܥ‬ሺ‫ݏ‬ሻ ൌ ݇௣ ൅ ೔ ൌ ݇௣ ቀ ቁ (16)
௦ ௦
a high attenuation to the higher frequency (>switching
where, ‫ ݖ‬is the zero of controller.
frequency) components by maintaining enough phase
With the increase of ݇௣ , the magnitude response gets a
margin (~166o) simultaneously. This helps the system act as
gain offset resulting the zero crossing to be happening at a more robust to any high frequency disturbances.
farther frequency, which increases the bandwidth. This
results in a faster dynamic response but may jeopardize
Magnitude (dB)

stability of the system if the net phase margin degrades.

Phase (deg)

Phase margin: 166o

Frequency (kHz)
Fig. 9. Voltage control loop structure of the CLLC converter. Fig. 10. Bode plot system response with PI controller.
 Similarly, this closed loop control strategy can be Considering the phase angle, turn-on of the secondary
implemented to achieve the constant current (CC) charging side switches should be strictly synchronized with the
of the battery. In the closed current loop, output current is polarity of the secondary resonant current. If the SR timing
sensed and employed as feedback signal. During the period is not properly set, there will be a circulating current in the
of CC charging of the battery, the regulated charging current secondary resonant tank to cause additional conduction loss.
is required. By means of frequency modulation, the output To minimize the circulating current in secondary resonant
current is regulated and raises the battery terminal voltage tank, Eq. (29) must be satisfied, which will prohibit the
until the upper charge voltage limit is reached, when the conduction through the undesired path.
current drops due to saturation. Thus, CC charging can be ‫ݐ‬ௗ௕̴௥௜௦௘ ൅ ‫ݐ‬ௗ௘௟௔௬ ൒ ߜ௠௔௫ (29)
achieved by using this control loop strategy. where, ‫ݐ‬ௗ௕̴௥௜௦௘ denotes the dead-time during turn-on of a
B. Proposed Synchronous Rectification Method secondary MOSFET and ‫ݐ‬ௗ௘௟௔௬ is the settling phase delay
time, which is the phase difference between primary and
Due to the characteristics of resonant tank, there exists secondary PWM in the digital signal processor. Fig. 12
a phase shift between primary MOSFET gate pulse and shows the scenario of dead time and phase delay.
secondary resonant current, which is defined as į and Vgs, pri Vgs, sec Vgs, pri Vgs, sec
determined by the resonant network and operating
frequency. A systematic modeling is given below to conduct tdelay
the phase lag estimation without the help of sensors. tdb_rise t
From FHA, the input impedance ܼ௜௡ of the equivalent
Ir2
circuit in Fig. 2 can be obtained as follows.
ଵା௧ ା௧ ା௝ሺ௧ ା௧ ሻ t
ܼ௜௡ ൌ షഘమ಴భమ಴మೃ೐ǡ೎ య భ ర మ ಽ (21)
ା௝ఠ஼భ ൬ଵିఠమ ଶ஼మ ቀ ೘
మ ା௅మ ቁ൰
Zero crossing happens
೙మ ೙
Fig. 12. Theoretical waveforms and phase delay.
where,
௅೘ ௅భ Fig. 13 shows the conducting path of circulating current
‫ݐ‬ଵ ൌ ߱ସ ‫ܥ‬ଵ ʹ‫ܥ‬ଶ ቀ‫ܮ‬௠ ‫ܮ‬ଶ ൅ ൅ ‫ܮ‬ଵ ‫ܮ‬ଶ ቁ (22) in the secondary side. If the gate pulse of high MOSFET
௡మ
ఠయ ோ೐ǡ೎ ஼భ ଶ஼మ ሺ௅೘ ା௅భ ሻ
‫ݐ‬ଶ ൌ (23) comes earlier than zero crossing of the resonant current, the
௡మ
௅೘ ଶ஼మ secondary side resonant current partially circulates through
‫ݐ‬ଷ ൌ െ߱ଶ ቀ‫ܮ‬௠ ‫ܥ‬ଵ ൅ ൅ ‫ܮ‬ଵ ‫ܥ‬ଵ ൅ ‫ܮ‬ଶ ʹ‫ܥ‬ଶ ቁ (24)
௡మ the high-side MOSFET and resonant capacitor (Cr3). In
ఠோ೐ǡ೎ ଶ஼మ
‫ݐ‬ସ ൌ
௡మ
(25) addition, a considerable portion of the resonant current takes
Thus, ߜ is obtained as, the path of discharging the battery. This circulation results
ߜ ൌ ߮ூ೛ ିூೞ ൅ ߮௏೛ ିூ೛ ൌ ݈ܽ݊݃݁ ቀ ቁ ൅ ݈ܽ݊݃݁ሺܼ݅݊ሻ
ூ೛
(26) in additional conduction losses in the secondary MOSFET
ூೞ and transformer winding, which potentially degrades the
ூ೛
where, ݈ܽ݊݃݁ ቀ ቁ represents the phase difference between conversion efficiency. To minimize circulating current in
ூೞ
primary and secondary resonant current, which can be the secondary side, dead band control is introduced so that
derived from FHA model. zero crossing of resonant current occurs within the dead
௦ሺ௅೘ ା௡మ ௅మ ሻା
೙మ
ାோ೐ǡ೎
time.
௜೛ ೞమ಴మ ൫௡మ ିఠమ ଶ஼మ ሺ௅೘ ା௡మ ௅మ ሻ൯ା௝ఠோ೐ǡ೎ ଶ஼మ
௜ೞ
ൌ
௦௅೘
ൌ
ିఠమ ௅೘ ଶ஼మ
(2)
௜೛ ௡మ ିఠమ ଶ஼మ ሺ௅೘ ା௡మ ௅మ ሻ
݈ܽ݊݃݁ ቀ ቁ ൌ െƒ”…–ƒሺ
௜ೞ ఠோ೐ǡ೎ ଶ஼మ
ሻ (28)
The plot of phase angle ߜ versus frequency is shown in
Fig. 11. Note that the zero-crossing frequency is around
109kHz, where the primary gate pulse has the same phase
angle with the secondary current. Within the operating
frequency range, it can be observed that the phase angle has Fig. 13. Circulating current path in the secondary side if (a) gate pulse is
the lagging and leading behaviors with respect to different appropriately engaged; (b) gate pulse is not appropriately engaged.
frequencies.
To implement this methodology, additional margins
90
need to be added to withstand the quantization error, as
45 Phase leading shown in Eq. (30),
Phase (deg)

ଵ ଵ
0 Frequency (kHz): 109.55 ‫ݐ‬ௗ௕̴௥௜௦௘ ൅ ‫ݐ‬௢௡ ൅ ‫ݐ‬ௗ௕̴௙௔௟௟ ൅ ‫ݐ‬௔௟௟௢௪௔௡௖௘ ൒  (30)
Phase lagging Phase (deg): 0 ଶ ௙ೝ
-45
where, ‫ݐ‬௢௡ and ‫ݐ‬ௗ௕̴௙௔௟௟ denote the turn-on time and dead
-90 Operating range time during turn-off of the secondary MOSFETs,
-135 1 2 3 respectively. ‫ݐ‬௔௟௟௢௪௔௡௖௘ is the additional margin, which is
10 10 10
Frequency (kHz) kept at 20ns.
Fig. 11. Phase angles between primary PWM and secondary resonant Moreover, another trade-off should be taken into
current in frequency-domain. consideration that the dead time needs to be long enough for
handling the worst case within the given frequency range.
On the other hand, it is noteworthy to mention that the
increase of the dead time degrades the power conversion
efficiency and the regulation in CV mode control.
To verify this methodology, a laboratory experiment
with the developed prototype are conducted. Fig. 14 shows
the experimental waveforms of dead band control,
respectively. Drain-to-source voltage ሺܸௗ௦ ሻ during the dead
time is higher than that during the conduction period due to
the differences in voltage drops between the body diode and
MOSFET.
V. EXPERIMENTAL RESULTS
As verification to the proof-of-concept, the bi-
directional CLLC converter is designed and tested up to
3.3kW. Photographs of the prototype is shown in Fig. 15.
Fig. 15. CLLC converter prototype.
Fig. 16 shows the steady state waveforms of the CLLC
converter operating at 3.3kW with 110kHz switching
frequency. The output voltage and output current are
regulated at 400V and .54A, respectively at an input of
600V.
Iout
Vds

Ires,2
Vout
Fig. 14. Verification to SR operations.
For a fair comparison, the SiC Schottky diode (a) (b)
SCS120AGC is added to be another candidate for the Fig. 16. Experiment results at full power: (a) steady state waveforms in CV
comparison objective. The key parameters of the selected mode. (b) Thermal image of the transformer.
diode and the MOSFET (C2M0040120D) are summarized In order to verify the effectiveness of voltage loop and
in Table IV. current loop design, both step-up and step-down load
Table IV. Key parameters of the selected diode and the MOSFET. transients are conducted in the experiment. Fig. 1 (a) and
SiC diode SiC MOSFET
Fig. 1 (b) show the closed voltage loop transients from
ܴௗ௦Ǥ௢௡ - 40݉ȳ 2kW to 1.5kW and 1.5kW to 2kW, respectively. Output
Forward voltage ܸ௙ 1.V 3.3V voltage is settled at its reference level i.e. 400V within 30ms
Reverse recovery charge ܳ௥௥ - 283nC for both the cases.
Reverse recovery time ‫ݐ‬௥௥ 0ns 54nS
Blocking voltage 600V 1200V
Continuous forward current 20A 60A

The estimated losses are provided in Table V. The

estimation is conducted assuming the output power of
1.5ܹ݇ with ݂௦ ൌ ͳͲͲ݇‫ ݖܪ‬as the full power operation with
the body diode is not feasible due to considerably higher (a) (b)
power loss and the thermal limitation. Moreover, for the Fig. 1. Waveforms obtained using CLLC voltage loop control (a) step-
simplicity, the switching loss of the MOSFET is assumed to down from 2kW to 1.5kW (b) step-up from 1.5kW to 2kW.
be zero and the reverse recovery is calculated using Eq. (31) The load transient from 1.5kW to 1kW using closed
[19]. This is a valid assumption as long as the switching current loop is achieved. With a settling time of 20ms, as
frequency of the resonant converter is lower than the natural shown in Fig. 18 (a) Similarly, the waveform of load step-up
frequency of the tank. Even under the scenario that the transient from 1kW to 1.5kW is shown in Fig. 18 (b), which
switching frequency is higher than the natural frequency; the implies a settling time of ms.
switching current is small compared to the secondary side
resonant RMS current.
ଵ
ܲ௥௥ ൌ ܳ௥௥ ܸௗ௦ ݂௦
ସ
(31)
Table V. Loss estimation for each device.
SiC SiC MOSFET SR
diode body diode operation
Conduction loss 8.59W 16.66W 1.02W (a) (b)
Reverse recovery loss 0W 2.9W 2.9W Fig. 18. CLLC closed current loop load step for the output current ripple
Total loss 8.59W 19.63W 3.99W observation: (a) step-down from 1.5kW to 1kW; (b) step-up from 1kW to
1.5kW.
 Fig. 19 shows the variation of the measured conversion
efficiencies with load power in both cases with and without
employing SR at a switching frequency of 150kHz and input
voltage of 600V. As indicated by the figure, the efficiency is
improved by up to 1. by incorporating the proposed SR
implementation technique on the secondary side.
Fig. 19. Efficiency comparison between the CLLC converter with SR and
without SR.
Fig. 20 shows the efficiency curves of the CLLC G2V
and V2G modes at resonant frequency across a wide load
range. The peak efficiency of G2V mode is 9.5 at 1.6kW
while the peak efficiency of V2G mode is 9.3 at 650W.
As can be seen in Fig. 20, the peak efficiency points of G2V
and V2G modes are achieved at different output power. Due
to higher input current in V2G mode compared to G2V, the
efficiency curves of G2V and V2G modes are not identical
despite the symmetric topology. In addition, in this design,
the gain curves of G2V and V2G modes in Fig. 5 are
different, resulting in different operating frequencies, which
further varies the efficiency performance.
1 [8]
G2V
V2G
0.98
Efficiency
0.96
0.94
0.92
0 1000 2000 3000
Output power (W)
Fig. 20. Efficiency comparison between the G2V and V2G modes.
VI. CONCLUSIONS
In this paper, an innovative SR implementation
technique in a bi-directional CLLC converter is introduced
and analyzed. As a part of the design, resonant parameters
are optimized to improve efficiency as well as power
density. A closed loop compensation technique utilizing the
proposed SR control logic is implemented to realize CV and
CC charging and to further improve the conversion
efficiency. Experimental results are presented to verify the
effectiveness of the control methodology. According to the
experimental results, implementation of SR improves the
efficiency up to 1.. Thus, the peak efficiencies of G2V
and V2G modes reach 9.5 at 1.6kW and 9.3 at 650W,
respectively.
VII. ACKNOWLEDGEMENT
This work has been sponsored partly by the National
Science Foundation Grant Number 1602012, which is
gratefully acknowledged.
VIII. REFERENCES
[1] H. Wang, S. Dusmez and A. Khaligh, "Maximum Efficiency Point
Tracking Technique for LLC -Based PEV Chargers Through Variable
DC Link Control," in IEEE Transactions on Industrial Electronics,
vol. 61, no. 11, pp. 6041-6049, Nov. 2014.
[2] C. Shi, H. Wang, S. Dusmez and A. Khaligh, "A SiC-Based High-
Efficiency Isolated Onboard PEV Charger With Ultrawide DC-Link
Voltage Range," in IEEE Transactions on Industry Applications, vol.
53, no. 1, pp. 501-511, Jan.-Feb. 201.
[3] J. A. P. Lopes, F. J. Soares and P. M. R. Almeida, "Integration of
Electric Vehicles in the Electric Power System," in Proceedings of the
IEEE, vol. 99, no. 1, pp. 168-183, Jan. 2011.
[4] Z. U. Zahid, Z. M. Dalala, R. Chen, B. Chen and J. S. Lai, "Design of
Bidirectional DC–DC Resonant Converter for Vehicle-to-Grid (V2G)
Applications," in IEEE Transactions on Transportation
Electrification, vol. 1, no. 3, pp. 232-244, Oct. 2015.
[5] Y. Tang, J. Lu, B. Wu, S. Zou, W. Ding and A. Khaligh, "An
Integrated Dual-Output Isolated Converter for Plug-In Electric
Vehicles," in IEEE Transactions on Vehicular Technology, vol. PP,
no. 99, pp. 1-1.
[6] P. He, A. Khaligh, "Comprehensive Analyses and Comparison of
1kW Isolated DC-DC Converters for Bidirectional EV Charging
Systems," in IEEE Transactions on Transportation Electrification,
vol. 3, no. 1, pp. 14-156, March 201.
[] Peiwen He and A. Khaligh, "Design of 1 kW bidirectional half-bridge
CLLC converter for electric vehicle charging systems," 2016 IEEE
International Conference on Power Electronics, Drives and Energy
Systems (PEDES), Trivandrum, 2016, pp. 1-6.
S. Zou, J. Lu, A. Mallik, and A. Khaligh, "3.3kW CLLC converter
with synchronous rectification for plug-in electric vehicles," IEEE
Industry Applications Society (IAS) Annual Meeting, Cincinnati, OH,
Oct. 201, pp. 1-6.
[9] F. Krismer and J. W. Kolar, "Accurate Power Loss Model Derivation
of a High-Current Dual Active Bridge Converter for an Automotive
Application," in IEEE Transactions on Industrial Electronics, vol. 5,
no. 3, pp. 881-891, March 2010.
[10] G. Oggier, G. O. García and A. R. Oliva, "Modulation strategy to
operate the dual active bridge DC-DC converter under soft switching
in the whole operating range," in IEEE Transactions on Power
Electronics, vol. 26, no. 4, pp. 1228-1236, April 2011.
[11] J. H. Jung, H. S. Kim, M. H. Ryu and J. W. Baek, "Design
Methodology of Bidirectional CLLC Resonant Converter for High-
Frequency Isolation of DC Distribution Systems," in IEEE
Transactions on Power Electronics, vol. 28, no. 4, pp. 141-155,
April 2013.
[12] C. Liu, J. Wang, K. Colombage, C. Gould and B. Sen, "A CLLC
resonant converter based bidirectional EV charger with maximum
efficiency tracking," 8th IET International Conference on Power
Electronics, Machines and Drives (PEMD 2016), Glasgow, 2016, pp.
1-6.
[13] Z. Lv, X. Yan, Y. Fang and L. Sun, "Mode analysis and optimum
design of bidirectional CLLC resonant converter for high-frequency
isolation of DC distribution systems," 2015 IEEE Energy Conversion
Congress and Exposition (ECCE), Montreal, QC, 2015, pp. 1513-
1520.
[14] F. Lu, H. Zhang, H. Hofmann and C. Mi, "A CLLC-compensated
high power and large air-gap capacitive power transfer system for
electric vehicle charging applications," 2016 IEEE Applied Power
Electronics Conference and Exposition (APEC), Long Beach, CA,
2016, pp. 121-125.
[15] D. Fu, P. Kong, S. Wang, F. C. Lee and M. Xu, "Analysis and
suppression of conducted EMI emissions for front-end LLC resonant
 DC/DC converters," 2008 IEEE Power Electronics Specialists
Conference, Rhodes, 2008, pp. 1144-1150.
[16] J. Lu, A. Mallik, S. Zou and A. Khaligh, "Variable DC Link Control
Loop Design for an Integrated Two-Stage AC/DC Converter,"
in IEEE Transactions on Transportation Electrification, vol. PP, no.
99, pp. 1-1.
[1] Http://www.ferroxcube.com/FerroxcubeCorporateReception/datashee
t/FXC_HB2013.pdf
[18] A. Mallik and A. Khaligh, "Variable-Switching-Frequency State-
Feedback Control of a Phase-Shifted Full-Bridge DC/DC Converter,"
in IEEE Transactions on Power Electronics, vol. 32, no. 8, pp. 6523-
6531, Aug. 201.
[19] Dusan Graovac, et.al ‘MOSFET Power Losses Calculation Using the
Data- Sheet Parameters’. Available online: http://application-
notes.digchip.com/00/0-41484.pdf
Shenli Zou (S’16) received his Bachelor’s degree
in Electrical Engineering and Automation from
Xi’an Jiaotong University (XJTU), Xi’an, China,
in 2015. He is currently working towards the Ph.D.
degree at the Department of Electrical and
Computer Engineering in the University of
Maryland, College Park, USA. His current
research interests include design, control,
modelling and system communication of power
electronics converters for plug-in electric vehicle applications, as well as
thermal management and magnetics analysis. He was the recipient for 2015
A. James Clark School of Engineering Distinguished Graduate Fellowship
and 2015 Jimmy H.C. Lin Graduate Scholarship.
Emerging and Selected Topics in Power Electronics, and an Associate
Editor of IEEE Transactions on Transportation Electrification.
Dr. Khaligh is the recipient of various awards and recognitions
including 201 Outstanding Young Alumnus Award from Illinois Institute
of Technology, the 2016 E. Robert Kent Junior Faculty Teaching Award
from Clark School of Engineering at UMD, the 2016 Junior Faculty
Outstanding Research Award from Clark School of Engineering at UMD,
the 2015 Junior Faculty Fellowship from the Institute for Systems Research
at UMD, 2013 George Corcoran Memorial Award from the ECE
Department at UMD, three Best Vehicular Electronics Awards from IEEE
Vehicular Electronics Society (VTS), and 2010 Ralph R. Teetor
Educational Award from Society of Automotive Engineers. Dr. Khaligh
was the General Chair of the 2016 IEEE Applied Power Electronic
Conference and Expo (APEC), Long Beach, CA, the General Chair of the
2013 IEEE Transportation Electrification Conference and Expo (ITEC),
Dearborn, MI, and the Program Chair of the 2011 IEEE Vehicle Power and
Propulsion Conference (VPPC), Chicago, IL. He is a Distinguished
Lecturer of the IEEE Vehicular Technology Society and also a
Distinguished Lecturer of the IEEE Industry Applications Society.

Jiangheng Lu (S’16) received his Bachelor’s

degree in electrical engineering from Huazhong
University of Science and Technology, Wuhan,
China, in 2014. He is currently working toward
the Ph.D degree in the Electrical and Computer
Engineering Department at the University of
Maryland, College Park, MD, USA. His current
research interests include modeling, analysis,
design and development of On-board Charger and High step-down
auxiliary power module for electric vehicles (EVs). His work involves
hardware and control development, thermal management and EMI filter
design.

Ayan Mallik (S’14) received his B.Tech and

M.Tech degrees (under 5 years Dual Degree
Program) in Electrical Engineering from Indian
Institute of Technology (IIT), Kharagpur, India in
2014. He is currently working toward the PhD
degree in the Electrical and Computer Engineering
Department at the University of Maryland, College
Park. His present work broadly focuses on the
design, modelling, control and optimization of power electronic converters,
highly efficient & high power density solutions for power conversions in
the applications of more-electric-airplanes, electric vehicles and data
centers.

Alireza Khaligh (S’04–M’06–SM’09) is an

Associate Professor at the Department of Electrical
and Computer Engineering (ECE) and the Institute for
Systems Research (ISR) in the University of Maryland
at College Park (UMD). His major research interests
include modeling, analysis, design, and control of
power electronic converters for transportation
electrification, renewable energies, energy harvesting,
and microrobotics. He is an author/coauthor of over
160 journal and conference papers. Dr. Khaligh is the Area Editor for
“Vehicular Electronics and Systems Area” of IEEE Transactions on
Vehicular Technology (TVT). He is an Associate Editor of IEEE
Transactions on Power Electronics, an Associate Editor of IEEE Journal of