FAKULTI KEJURUTERAAN ELEKTRONIK DAN

KEJURUTERAAN KOMPUTER

SHORT REPORT

Code of Subject BENR 3241

Name of Subject COMPUTER ENGINEERING LAB 4
Title Combinational Circuit Design with Xilinx Vivado
Lab Session 2
Date 25/04/2023
Year 2 Semester: 2
Course BENR
Section / Group 2/L
In-lab Assessment
Name of Student: Matrix: Tools Proc Data Dress Ethic
1. AMAREEN A/L SUTHIB B022110091
2. MUHAMMAD AFNAN BIN
B022110183
AMRAN
3. MUHAMMAD FIRDAUS BIN
B022110072
ABDUL

MAJED
4.

Lecturer /
Instructor’s 1. Dr. Anis Suhaila Binti Mohd Zain
Engineer / Tutor

Short Report Result [PO5] Disc [PO4]

Marks (5) (4)
1.0 OBJECTIVES

Upon completion of this laboratory session, the student should be able to:

1. Write a Verilog code for a combinational logic design using Xilinx Vivado.

2. Creating test benches for simulation and verification of combinational logic design.

3. Present a given task findings in the form of standard technical report.

4. Work effectively in given task as individual or group.

2.0 EQUIPMENT

i) Personal computer running Windows 7.0 (or above) with Xilinx Vivado Webpack installed

ii) Zedboard with Zynq-7000 SoC family

iii) 12V power adaptor (comes with the Zedboard)

iv) USB-A to micro-USB-B cable (comes with the Zedboard)

3.0 INTRODUCTION

This laboratory presents the Verilog constructs for developing structural models of combinational
logic. An electronic circuit may be synchronous or asynchronous, and it may be digital or analog. In
digital systems, all inputs, outputs and internal signals can only take digital values, and in
synchronous digital hardware all changes are controlled by one or multiple clocks.

4.0.RESULT

PART A CODING:
module eor(y0,a,b);
output y0;
input a,b;
wire y1,y2,y3,y4;
not NOT1(y3,b);
not NOT2(y4,a);
and AND1(y1,a,y3);
and AND2(y2,b,y4);
or (y0,y1,y2);
endmodule

TESTBENCH:
`timescale 10ns/1ns
//testbench module
module t;
//inputs to DUT as reg
//output as wires
wire y0;//1-bit output
reg a,b;//1-bit input
reg clk;
eor m(y0,a,b);
//initialize inputs & set simulation end time
initial begin

clk=1;a=0;b=0;
#70 $finish;
End

parameter clk_high=1;
//clock generator
always #clk_high clk=~clk;
//input signals generation
reg [1:0] cnt;//2-bit counter
initial cnt=0;
always @(posedge clk)
begin
cnt<=cnt+1;
a<=cnt[1];
b<=cnt[0];
end
endmodule

OUTPUT:
TRUTH TABLE OUTPUT:

PART B:
module adder1(cout,sum,cin,a,b);
output cout,sum;
input a,b,cin;
wire y1,y2,y3;
xor XOR1(y1,a,b);
xor XOR2(sum,y1,cin);
and AND1(y2,cin,y1);
and AND2(y3,b,a);
or (cout,y2,y3);
endmodule

PART B: TESTBENCH:
`timescale 10ns/1ns
module t;
wire sum,cout;
reg a,b,cin;
reg clk;
adder1 m(sum,cout, cin,a,b);
initial begin
clk=1;
a=0;
b=0;
cin=0;
#70$finish; end

parameter clk_high=1;
always #clk_high clk=~clk;
reg[2:0]cnt;
initial cnt=0;
always @ (posedge clk)
begin
cnt<=cnt+1;
a<=cnt[1];
b<=cnt[0];
cin<=cnt[2];
end
endmodule
Truth table output:

6.0 Conclusion

Xilinx Vivado is to design and implementing digital circuit on FPGA (Field- Programmable Gate Array)
devices. To create a combinational circuit using logic gates to create circuits that carry out Boolean
logic operations. Because these circuits don't have feedback loops, the output depends only on the
current input values and not on any previous input or output values. Combinational circuits are often
used in digital electronics for calculation, data encoding, and data decoding tasks. They are a key
concept in the study of digital electronics and computer engineering and act as the basic building
block for ever-more complex digital systems.