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Saritha - Resume - Memory Layout
Saritha - Resume - Memory Layout
SARITHA RAYUDU
Email:
rayudusaritha10@gmail.com
Mobile: +91- 7981499947
CARRIER OBJECTIVES
I am a sincere, loyal and dedicated individual who has a great deal of ambition. I
love to learn, and am always up to a challenge. I get along well with others, while
also working efficiently on my own. I am seeking a position where I can develop and
excel while giving my best as an employee.
PROJECT DETAILS
Project 2: S1DU( SRAM based Single port ultra low leakage Memory)
Technology : TSMC:16nm -finfet
Environment : Cadence Virtuoso Layout Editor.
Role-played:
• Drawn Layout for standard cells (Decoders, encoders, inverters, nand,
flipflops , Multiplexers)
• Cleared DRC, LVS at Instance level.
Project 3: STANDARD CELLS(AND,OR,NOR,NAND,EX-OR,EX-NOR)
Technology : TSMC:16nm-finfet
Environment : Cadence Virtuoso Layout Editor
Role-played:
• Drawn Layout for standard cells
• Cleared DRC, LVS at Instance level.
TECHNICAL SKILLS
EXPERIENCE
QUALIFICATION
PERSONAL DETAILS
DECLARATION
I hereby state that all the above furnished information is true and correct to the best of my
knowledge.
R.SARITHA