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  • Fdlca 1

    Uploaded by

    Ankit Bhardwaj
    13 views7 pages
    The document contains VHDL code for implementing basic logic gates including AND, OR, NOT, NAND, NOR, XOR and XNOR gates. For each gate, the code defines the entity with inputs and output ports, and the architecture that specifies the logic operation to assign to the output using the inputs.

    Original Description:

    fdlc

    Original Title

    fdlca 1

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    The document contains VHDL code for implementing basic logic gates including AND, OR, NOT, NAND, NOR, XOR and XNOR gates. For each gate, the code defines the entity with inputs and output ports, and the architecture that specifies the logic operation to assign to the output using the inputs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    13 views7 pages

    Fdlca 1

    Uploaded by

    Ankit Bhardwaj
    The document contains VHDL code for implementing basic logic gates including AND, OR, NOT, NAND, NOR, XOR and XNOR gates. For each gate, the code defines the entity with inputs and output ports, and the architecture that specifies the logic operation to assign to the output using the inputs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 7

    AND GATE

    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity andgate is
    port(
    A,B: in bit;
    Y: out bit);
    end andgate;
    architecture dataflow of andgate is
    begin
    Y <= A and B;
    end dataflow;

    Output:-
    OR GATE
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity orgate is
    port(
    A,B: in bit;
    Y: out bit);
    end orgate;
    architecture dataflow of orgate is
    begin
    Y <= A or B;
    end dataflow;

    Output:-
    NOT GATE
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity notgate is
    port(
    A: in bit;
    Y: out bit);
    end notgate;
    architecture dataflow of notgate is
    begin
    Y <= not A;
    end dataflow;

    Output:-
    NAND GATE
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity nandgate is
    port(
    A,B: in bit;
    Y: out bit);
    end nandgate;
    architecture dataflow of nandgate is
    begin
    Y <= not(A and B);
    end dataflow;

    Output:-
    NOR GATE
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity norgate is
    port(
    A,B: in bit;
    Y: out bit);
    end norgate;
    architecture dataflow of norgate is
    begin
    Y <= not(A or B);
    end dataflow;

    Output:-
    XOR GATE
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity xorgate is
    port(
    A,B: in bit;
    Y: out bit);
    end xorgate;
    architecture dataflow of xorgate is
    begin
    Y <= ((not A)and B)or(A and (not B)) ;
    end dataflow;

    Output:-
    XNOR GATE
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity xnorgate is
    port(
    A,B: in bit;
    Y: out bit);
    end xnorgate;
    architecture dataflow of xnorgate is
    begin
    Y <= (A and B)or((not A) and (not B));
    end dataflow;

    Output:-

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