Scribd Logo
Upload

Welcome to Scribd!

  • Fdlca 2

    Uploaded by

    Ankit Bhardwaj
    9 views4 pages
    This document contains code examples for implementing basic logic gates using only NAND gates. It includes code to create a NOT gate using one NAND gate, an AND gate using two NAND gates, an OR gate using two NAND gates, and a NOR gate using four NAND gates. The code defines the port inputs and outputs for each gate and specifies the NAND logic to be performed to achieve the gate's function.

    Original Description:

    fdlc

    Original Title

    fdlca 2

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document contains code examples for implementing basic logic gates using only NAND gates. It includes code to create a NOT gate using one NAND gate, an AND gate using two NAND gates, an OR gate using two NAND gates, and a NOR gate using four NAND gates. The code defines the port inputs and outputs for each gate and specifies the NAND logic to be performed to achieve the gate's function.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    9 views4 pages

    Fdlca 2

    Uploaded by

    Ankit Bhardwaj
    This document contains code examples for implementing basic logic gates using only NAND gates. It includes code to create a NOT gate using one NAND gate, an AND gate using two NAND gates, an OR gate using two NAND gates, and a NOR gate using four NAND gates. The code defines the port inputs and outputs for each gate and specifies the NAND logic to be performed to achieve the gate's function.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    NOT using NAND gate

    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity notnand is
    port(
    A: in bit;
    Y: out bit);
    end notnand;
    architecture dataflow of notnand is
    begin
    Y <= A nand A;
    end dataflow;

    Output:-
    AND using NAND gate
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity andnand is
    port(
    A,B: in bit;
    Y: out bit);
    end andnand;
    architecture dataflow of andnand is
    begin
    Y <= (A nand B)nand(A nand B);
    end dataflow;

    Output:-
    OR using NAND gate
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity ornand is
    port(
    A,B: in bit;
    Y: out bit);
    end ornand;
    architecture dataflow of ornand is
    begin
    Y <= (A nand A)nand(B nand B);
    end dataflow;

    Output:-
    NOR using NAND gate
    Code:-
    library ieee;
    use ieee.std_logic_1164.all;
    entity nornand is
    port(
    A,B: in bit;
    Y: out bit);
    end nornand;
    architecture dataflow of nornand is
    begin
    Y <= ((A nand A)nand(B nand B))nand((A nand A)nand(B nand B));
    end dataflow;

    Output:-

    You might also like