Chapter 1

Analog-to-Digital Converters for Wireless Receivers

Wireless receivers need to process small desired input signals corrupted by large out-of-
band interferers. For example, in Bluetooth, an interferer at a 1 MHz frequency offset
can be 30 dB higher than the desired signal. In LTE5/10/20, the interferers can be 48 dB
higher at a 15 MHz offset from the desired band.

The block diagram of a typical direct-conversion RF receiver is shown in Fig.1.1.

The input signal, received by an antenna is amplified by a low-noise amplifier (LNA).
The mixer then demodulates the LNA output signal from RF frequency (LO) to base-
band. The low pass filter, then attenuates the out-of-band signals, and the resulting
filtered signal is digitized by the ADC and post-processed digitally.

LO (0o) Baseband filter

Mixer I
ADC
LNA
Interferers Filter Filtered
Interferers DSP
Desired

ADC
Q
o
LO (90 )
Figure 1.1: Block schematic of a wireless IQ receiver system

The baseband filter needs to have a high adjacent channel rejection - hence its order
is typically high. Besides, it also needs to have low noise as it is precedes the ADC.
Thus, it consumes a lot of power as shown in Section - 1.2. One way to get around
the problem is to remove the filter altogether. Now the dynamic range of the ADC
has to be very high to handle the interferer signals as well, which means high power
dissipation in the ADC. Nyquist rate ADCs with large dynamic range are difficult to
design. Besides, they sample the input up front and hence an anti-alias filter should
be used. A continuous-time delta-sigma modulator (CT∆ΣM) is an attractive choice
for implementing the ADC, as they are easier to drive thanks to their resistive input
impedance and implicit anti-aliasing properties. Let us now take a look at the behaviour
of a CT∆ΣM in the presence of out-of-band interferers in detail.

1.1 Continuous-Time Delta Sigma ADC

clk q[n]
u(t) v[n] u(t) v[n]
Loop filter ADC L(s)

DAC p(t)
(a) (b)

Figure 1.2: (a) Block diagram of a CT∆ΣM. (b) CT∆ΣM with the ADC modelled as a
sampler and additive quantization noise q[n]. L(s) is the loop filter transfer
function. The feedback DAC pulse shape is denoted by p(t).

Fig.1.2(a) shows the block diagram of a CT∆ΣM. It consists of a loop filter im-
plemented in continuous-time (CT), a coarse ADC and feedback DAC. Intuitively, the
quantization noise of the coarse ADC is divided down by the loop filter gain. Thus, if a
large gain is used in the loop filter, a higher signal-to-quantization noise ratio (SQNR)
can be achieved. Having a large loop filter gain at all frequencies will render the loop
unstable [1]. Typically, the loop filter is realized as a low-pass transfer function with
high gain in the frequency of interest (signal band, fBW ). The ADC is clocked at a
higher sampling rate (fs ) compared to fBW , so as to have a reasonable order for the
loop filter. The ratio fs /(2fBW ) is called the oversampling ratio (OSR).

Let us understand the behaviour of a CT∆ΣM to in-band and out-of-band signals.

Fig.1.2(b) shows a CT∆ΣM, where the coarse ADC in the loop is replaced by a sampler
and an additive quantization noise q[n]. The DAC pulse shape is denoted by p(t). The
transfer function of the loop filter is L(s). L(s) and the sampler in Fig.1.2(b), can be
moved to the left of the summing block. This results in the modified block diagram
shown in Fig.1.3(a). Note that the summer inputs and output are in discrete time (DT).

The DT transfer function from v[n] to the summer input is denoted by L1 (z). The
Noise Transfer Function (NTF) of the CT∆ΣM, which represents the gain from q[n] to
the output v[n] is shown in Fig.1.3(b). The design of NTF to achieve a specific SQNR
for a given fBW /fs and finding the equivalent L1 (s) is discussed at length in [1]. Let us

2
 clk q[n] clk q[n]
u(t) v[n] u(t) v[n]
L0(s) L0(s) NTF(z)

clk L1(z) 1
NTF(z) =
L✶(s) p(t) 1 + L1(z)

(a) (b)

Figure 1.3: (a) L(s) and the sampler of Fig.1.2(b) are moved to the left of the summer.
(b) Equivalent block diagram of the CT∆ΣM showing STF/NTF.

focus on the signal transfer function (STF) of the CT∆ΣM. From Fig.1.3(b), the input
signal passes through L0 (s) before being sampled. It is then filtered by the NTF to reach
the modulator output. To understand this better, let us look at an example. Consider a
fourth order CT∆ΣM with an OSR of 64 and out-of-band gain (OBG) of 1.5.

1.5

ban ❇ s)

0 1
Frequen s)
Figure 1.4: NTF of a fourth order modulator with OSR of 64 and OBG of 1.5.

The magnitude of the NTF is shown in Fig.1.4. From NTF(z), L1 (z) can be de-
termined. The equivalent L1 (s) can then be obtained by equating the sampled pulse
response of L1 (s) with the impulse response of L1 (z) [1, 2]. The equivalent L1 (s)
(normalized to a sampling rate of 1 Hz) in our example turns out to be

0.6703 0.2495 0.0555 0.0061

L1 (s) = + + + (1.1)
s s2 s3 s4

L1 (s) can be implemented in multiple ways as shown in Fig.1.5. Here, a1 = 0.6703,

a2 = 0.2495, a3 = 0.0555 and a4 = 0.0061. The key point to note here is that L1 (s) is
fixed by the NTF. DAC4 ’s gain is one in all the architectures so that |STF(0)| = 1. The
first architecture is the cascade of integrators with feedback (CIFB) paths at the input
of each integrator. The number of feedback DACs can be reduced to one, as shown
in the next architecture in Fig.1.5(b), where the paths of L1 (s) are implemented using
feed-forward from each integrator (CIFF). The third architecture shown in Fig.1.5(c) is

3
implemented using a combination of feedback and feed-forward (CIFF-B) paths.
✉✝✞✟ ω4 a✹ ω✆ ω✄ ω1 v[n]
☎ ☎ ☎ ☎

✸ ✷

1
4
✂ ✂ ✂ ✂
✁ ☛ ✁ a✆ ✁ a✄ ✁ a✡ clk
❉ ❉ ❉ ❉

(a)

a✄

✉✝✞✟ ω4 ω✆ ω✄ ω1 a4 v[n]
☎ ☎ ☎ ☎

a✆
4

✂
✁ ☛ clk
❉ a1
(b)

a✆✴✠4

✉✝✞✟ ω4 a✹ ω✆ ω✄ ω1 v[n]
☎ ☎ ☎ ☎

✷
1
4

✂ ✂ ✂
✁ ☛ ✁ a✄ ✁ a✡ clk
❉ ❉ ❉

(c)

Figure 1.5: Different architectures of the loop filter to implement a given NTF. ω1 , ω2 ,
ω3 , ω4 = 1. (a) Cascade of Integrators with Feedback (CIFB), (b) Cascade
of Integrators with Feed-forward (CIFF) summation, (c) Cascade of Inte-
grators with a combination of Feed-forward and Feedback (CIFF-B) paths.

The STF of each of these architectures are shown in Fig.1.6. Although they have
the same L1 (s), their STF’s are different, as the transfer function from the modula-
tor input (u(t)) to the input of the sampler − L0 (s), is different for each of the three
topologies. The CIFB architecture has no out-of-band peaking and has the highest
(-80 dB/dec) high-frequency roll-off, as the input signal u(t) is filtered by four integra-
tors before reaching the quantizer. However, if the interferers are just outside the signal
band, as shown in Fig.1.6, the CIFB topology cannot attenuate them.

As seen from Fig.1.5(a), the output signal is fed-back to the input of every inte-
grator. The input swing of every ωx /s (x = 1,2,3,4) stage, needs to be small for a finite
output swing, due to its high gain. So the preceding integrator output should cancel the
fed-back signal. Thus there is significant swing at the output of the preceding integrator.
This puts a limit on the amount of node-scaling that can be done in the integrators. This
directly affects the power consumption of the subsequent stages, as it limits the amount
by which the noise/distortion of the succeeding stages is suppressed. Thus, the CIFB

4
 0 -20dB/dec

| STF | (dB)
Close-in
interferers -60dB/dec
CIFB
CIFF
CIFF-B -80dB/dec

BW 10fBW
Frequency

Figure 1.6: STF of CIFB/CIFF/CIFF-B CT∆ΣM with an OSR of 64 and OBG of 1.5.
The high frequency roll-off is also shown. The CT∆ΣM will be exposed to
out-of-band interferers as shown.

has the highest power consumption among the three topologies.

The CIFF has the highest peaking and lowest high-frequency (-20 dB/dec) roll-off
among the three architectures. This is because of the presence of a feed-forward path
from the output of the first integrator (ω4 /s) to the quantizer. The presence of large gain
(cascade of three integrators) after the first integrator makes the signal swing at the input
of the first integrator very small. Thus its gain can be increased significantly, thereby
suppressing the noise/distortion of the succeeding stages. This makes the CIFF the
most power efficient architecture. However, due to the peaking in the STF, the dynamic
range of the ADC will be severely reduced in the presence of out-of-band interferers.
The CIFF-B is a compromise between the number of feedback DACs required and high
frequency roll-off (-60 dB/dec). However due to the presence of the feed-forward path
from the first integrator output to the third integrator input, we still see a significant
peaking in the out-of-band STF similar to the CIFF.

We thus see that although the CT∆ΣM itself is a low pass filter, the signal trans-
fer function (STF) is simply a by-product of the noise transfer function (NTF) and we
cannot design the STF independently to suit a given requirement. Therefore, new tech-
niques are needed to handle these "close-in" interferers, which are discussed in the next
section.

5
 0

Nearb
Close-in
-20

STF (dB)
interferers

-60

-80
fBW BW s
t frequency

Figure 1.7: STF of a fourth order CIFB CT∆ΣM with an OSR of 64. fBW represents
the signal bandwidth and fs is the sampling frequency.

1.2 Introduction to filtering CT∆ΣMs and prior art

The STF of our example CIFB CT∆ΣM is shown in Fig.1.7. The f−3dB of the STF is
greater than 5fBW and hence any interferer upto that frequency can potentially saturate
the modulator. As discussed earlier, this is because the STF cannot be independently
designed to attenuate these close-in interferer signals without altering the NTF.

The out-of-band interferer signals less than 5fBW can be filtered out by using an
up-front low pass filter. Consider the Tow-Thomas biquad - CT∆ΣM cascade shown in
Fig.1.8. The filter has a 3-dB cut-off frequency of twice the signal bandwidth (2fBW )
and a quality factor (Q) of 0.707. Since the filter attenuates out-of-band interferers
anyway, we can use a CIFF loopfilter in the CT∆ΣM to reduce power. The order, OSR
and OBG of the modulator is chosen based on the overall receiver specifications. The
first integrator of the CT∆ΣM is implemented using active-RC techniques for good
linearity.

u
1(s)

Figure 1.8: Filtering ADC : Active-RC biquad in cascade with a CIFF CT∆ΣM.

Let us look at the overall noise of this "filtering" CT∆ΣM. The thermal noise of

6
the CIFF CT∆ΣM is dominated by the input and DAC feedback resistors together with
the first integrator’s OTA. The rest of the integrators are impedance scaled to reduced
power. Therefore, the input referred inband resistor noise spectral density of the CIFF
ADC is 8kT R. Let the filter’s resistors be the same as that of the CT∆ΣM. Simple
algebra shows that the low-frequency resistor noise spectral density of the filter is also
8kT R. Thus the total noise spectral density of the overall filtering ADC is 16kT R,
which is twice that of the CIFF ADC.

The first integrator’s OTA can be reused for the filter as it needs to sink/source the
same current. So the filter power is twice as that of the CIFF ADC. The distortion per-
formance of the filter - CT∆ΣM cascade will be poor compared to the standalone ADC,
since the filter’s OTAs will also distort the input signal. To achieve out-of-band inter-
ferer suppression, we thus need to use twice the power of a standalone ADC. Moreover,
we still end up with twice the noise in the signal band. This represents a 9 dB reduction
in the overall Schreier FoM for the filter - CT∆ΣM cascade compared to the conven-
tional CIFF ADC.

1.2.1 CT∆ΣM with embedded filtering

The first filtering CT∆ΣM, reported in [3], suggests to move the filter after the first
integrator as shown in Fig.1.9. H1 (s) is the filter which is embedded after the first
integrator, ωo /s. The rest of the loop filter is lumped into L1 (s). Now the filter’s noise
and distortion are suppressed by the first integrator. This allows us to impedance scale
the filter, thereby saving power and area compared to a filter-CT∆ΣM cascade.

o
Filter
u s v
H1(s) 1(s)
o
s
1-H1(s) clk

Compensation path

Figure 1.9: Basic idea of embedding a filter inside the CT∆ΣM.

The introduction of the filter introduces delay into the loop, and would render it
unstable if the modulator was not compensated. This is done by introducing an extra

7
feedback path shown in Fig.1.9. [3] used a first order RC filter for H1 (s). The disadvan-
tage of this approach is that an extra integrator and a compensation filter implementing


1 − H1 (s) is required which increases design complexity and power dissipation.

R3

R✌

u R R1 R✍ v
1 ☞ 3 L1(s)

clk
R Rc

Figure 1.10: CT∆ΣM with an embedded Tow Thomas filter [4].

The issue with the increased circuit complexity was solved in [4], where a second
order Butterworth filter was used in H1 (s). The transfer function of the second order
filter is given below.
1
H1 (s) = s2 s
(1.2)
ωp 2
+ ωp Q
+1

where, ωp and Q are the cut-off frequency and quality factor of the filter respectively.
The compensation path transfer function then becomes,

ωo s ωo
ωo  
ωp
+ Qω p
1 − H1 (s) = s2 s
(1.3)
s ωp 2
+ ωp Q
+ 1

Since the compensation path transfer function has the same poles as the filter, [4] used
an additional feedback path through Rc as shown in Fig.1.10 to restore the NTF. This
method completely eliminates the extra integrator and compensates for the NTF with-
out any extra circuitry. So power and area is saved compared to the filter-CT∆ΣM
cascade. In the next section, we will look at the performance trade-offs associated with
embedding a filter inside the CT∆ΣM.

1.2.2 Power dissipation versus out-of-band interferer rejection

The introduction of the extra feedback path for NTF compensation increases the signal
swing at the output of the first integrator similar to the CIFB case. Let us now look at
this in more detail.

8
 u HH(s)
1 v
ωo a Rest o
s -(1-H(s))ω
1 o loop
s
clk

Figure 1.11: Filtering ADC : Second order filter embedded after the first integrator of a
CT∆ΣM

Consider the simplified schematic of a CIFF-B CT∆ΣM with the filter H1 (s),
embedded after the first integrator as shown in Fig.1.11. ωo is the unity gain frequency
of the integrator. ωp is the 3-dB cut-off frequency of the filter and Q is the quality factor.
The NTF is compensated by the additional feedback path - from b to x. The dc gain of
this path is ωo /ωp Q.

The signal swing at x is zero by virtue of the CIFF-B architecture. Since the dc
gain of the path from a to x is one, the low frequency signal swing at the output of the
first integrator must be ωo u/ωp Q (STF = 1). Then, there will be quantization noise on
top of this signal swing. Thus ωo cannot be arbitrarily made larger (like in the CIFF
design) to attenuate the noise and distortion of the succeeding filter. Consequently the
filter cannot be impedance scaled by a large factor. [4] showed that the Tow-Thomas
filter can be impedance scaled only by a factor of 3 compared to the first integrator
without taking a significant hit in the low frequency noise PSD.

It is also easy to see that ωp should be low to suppress out-of-band low frequency
interferers. A smaller ωp increases the gain of the feedback path, ωo /ωp Q, thereby
increasing the signal swing at the first integrator output. To maintain the same signal
swing, ωo will have to be reduced further. This in turn increases the power consumption
in the filter and the succeeding stages, as their impedance scaling factor reduces for a
given noise requirement. Also, embedding a low-Q filter, such as a passive RC filter
will once again reduce ωo . From this discussion, it is clear that achieving out-of-band
STF filtering comes with increased power dissipation and design complexity compared
to conventional state-of-the-art standalone CT∆ΣMs . Thus embedding an inherently
more linear and power efficient filter into the CT∆ΣM loop is imperative to improving
the overall filtering ADC’s performance.

9
 Another method to implement a filtering ADC is to embed a CT∆ΣM into the fil-
ter loop [18]. This choice puts some constraints on the STF of the embedded CT∆ΣM.
From a designer’s perspective, therefore the optimum architecture for the filtering CT∆ΣM
is not immediately clear. In this thesis, we analyze possible architectures in detail and
conclude that embedding a multiple feedback (Rauch) filter inside a CIFF-B CT∆ΣM
is the most power efficient filtering CT∆ΣM architecture. A 1 MHz CT∆ΣM with an
embedded second order filter (with 2 MHz bandwidth) is designed as a proof of concept,
and measurement results that verify our theory are given.

1.3 Continuous time pipelined ADC (CT-pipe)

1.3.1 Motivation

Wideband analog-to-digital converters are key components of digital wireless systems

such as WLAN/LTE etc. Typical resolutions of these ADCs are 10-12 bits in a signal
bandwidth ranging up to 100 MHz. In such cases, using a CT∆ΣM also becomes diffi-
cult as the sampling rates required are high. This leads to a problem due to technological
limitations, which is discussed below.
Ts
u(t) v[n]
Loop filter
clk

clk
clk_d
vdac(t)

vdac(t)
clk_d
TELD
Figure 1.12: Block schematic of CT∆ΣM illustrating excess loop delay (TELD ).

Fig.1.12 shows the block diagram of a CT∆ΣM operating with a sampling period
Ts . The ADC samples the loop filter output at the rising edge of the clock. The sampled
data is then converted to full scale using a regenerative latch. The DAC is clocked using
a delayed version of the ADC clock (clk_d) as shown in Fig.1.12. Then there is a small
delay before the DAC produces it output. The time between the instant where the loop
filter output is sampled by the ADC to the instant where the DAC produces its output is
called excess loop delay (ELD) of a CT∆ΣM. This is marked as TELD in Fig.1.12.

10
 If we use the fourth order single-bit CT∆ΣM (OSR = 64) discussed in the previous
section to digitize a signal bandwidth of 100 MHz, the sampling rate required would be
12.8 GHz (Ts = 78ps) ! Such speeds are impractical in a 65 nm CMOS process as TELD
would be much higher than Ts , rendering the loop unstable. Another option would be
to reduce the OSR to 16 (fs = 3.2 GHz) and use a 3-bit quantizer in the loop. However,
the implementation of a multi-bit DAC is challenging, as its linearity is limited by
process mismatch of its unit elements. Dynamic element matching techiques such as
data weighted averaging (DWA) need to be used, which are power hungry. Also, the
DWA block increases TELD further, which would result in instability as in the single-bit
case.
2◆✔✕
Vin Vr✒✓

V✎✏✑

Figure 1.13: Block diagram of a DT-pipe input stage.

In pipelined architectures, the input is digitized over multiple clock cycles and
hence, can operate with a lower sampling frequency. The block diagram of the input
stage of a discrete-time pipeline ADC (DT-pipe) is shown in Fig.1.13. The input is
sampled up front by a sample and hold block (S/H). The sub-ADC digitizes the stage
output into N bits. The stage residue Vres is calculated by subtracting the DAC output
VDAC from the sampled value of the input signal. Vres is then amplified by an interstage
amplifier (ISA) and processed by the next stage of the pipe.

As the input is sampled up front, an anti-alias filter is required, which consumes

more power than the ADC itself, due to its noise requirements. Also, the capacitive
input impedance of the DT-pipe makes it difficult to drive. Discrete-time SAR ADCs
also have the same issues. Ideally, we would like an ADC which has a resistive input
impedance, has inherent out-of-band filtering and can operate with low sampling rates.
The continuous time pipelined ADC (CT-pipe) is a compelling choice which satisfies
these requirements. The principle is described below.

11
1.3.2 CT-Pipe : Architecture and Signal reconstruction

The simplified block diagram of an example one stage CT-pipe is shown in Fig.1.14.
The up front sample and hold of a DT pipe (in Fig.1.13) is removed. The input is
sampled by a 3-bit ADC0 and its output is D0 . The stage residue Vres is generated by
subtracting the delayed input from the DAC output VDAC . Vres is then processed by the
interstage amplifier (ISA). The output of the ISA is sampled by another 3-bit ADC1 ,
which yields the sequence D1 .
✦✧★✩✪
V■✖ V✛✜✢
✣✤✥

V✗✘✙
✭ ✭ ✮
✬ ✬ ✬
✫ ❆ ✫
❆ ✫ ❆
✲ ✲
D✵ D✚
❋✯✰✱ ❨

Figure 1.14: Block diagram of a one stage CT-pipe.

The feed-forward (ADC0 -DAC0 ) path has a delay which comprises of the regener-
ation time of the ADC and the delay through DAC. If the input path is not delayed, this
leads to timing mismatch between the input and the feed-forward path. To correct this,
a delay is added to the input path as shown in Fig.1.14. The stage outputs D0 and D1
are combined using a filter F (z) to give the overall CT-pipe output, Y .
Latt⑦⑧⑨ Iin ❳❝❞ ❫❡❴❵❛❜ IDAC Iin ❳❩❬❭❪ ❫❡❴❵❛❜
⑩⑨❶❷❸ C
Iin I❊●❍
◗
❁❘
▼❖P
①②
)

❑
IDAC ✇✈ ▼
Vin ✈t
❥ ❙▼❖P
q Ts
▲ ♣❣
❢❧ ❙◗
♥
❘❀❁ ❘❀❂ ❘❀❁ ♠ I❯❱❲ ❳❝❞ ❫❡❴❵❛❜ I❯❱❲ ❳❩❬❭❪ ❫❡❴❵❛❜
nal a

❅ ❅ ❈ ◗
IDAC

ADC

❧✐
ADC

G✽ ❃ ❄❀❘ ❦ ▼❖P
❥
✐
❏ ❤❣ ▼
❢
❏ ♦
❙▼❖P
V

D✽ D✾
✿ ❙◗
✳✺✻✼
▼ P▼ ◗▼▼ ◗P▼ ❚▼▼
T❬③❡ ❳❭④⑤s)
(a) ✺⑥✼

Figure 1.15: (a) Simplified schematic of a one stage CT-pipe. (b) Current waveforms of
the input (Iin ), DAC (IDAC ) and residue signals (Ires ).

The simplified schematic of the CT-pipe (described in Fig.1.14) is shown in Fig.1.15(a).

The sub-ADCs are clocked at a sampling rate fs , which is 8× the signal bandwidth.

12
DAC0 is implemented as a current DAC (IDAC0 ). The residue is calculated in the cur-
rent domain (Ires ) and passes through an interstage amplifier (ISA) formed by the re-
sistor, 4R and the capacitor C. A first order lattice all-pass filter, which exactly mimics
the feed-forward path delay is added to the input path as shown in Fig.1.15(a).

Iin Idac

I/IFS
❺

+
DAC images at fs - fin

2 2
(a) Frequency (f/fs) (b) Frequency (f/fs)
0.02
Ires
I/IFS

0.01

0 1 2
(c) Frequency (f/fs)
Figure 1.16: Input, DAC and residue signals in the frequency domain.

Fig.1.15(b) plots the residue current as a function of time. The CT-pipe is excited
with a full scale (1 V) sinusoidal input at fs /8. We see that, even after adding the lattice
delay in the input path, the residue current (in green) is still higher than the expected
value of 1/23 (3-bit quantizer). The reason for this can be understood from Fig.1.16.
The input current Iin is a single tone sinusoid at the signal band-edge (fs /8). IDAC
contains a filtered version of the input signal along with the image signals at fs ± fin .
The third sub-plot of Fig.1.16 shows the spectrum of residue signal Ires .

The input signal component at fs /8 is well suppressed in the residue waveform.

However, the DAC image signals remain without cancellation and dominate the residue
amplitude of Fig.1.15(b). To filter these, the ISA is modified to have a filtering transfer
function, which is in stark contrast to a DT-pipe (which has only a gain stage). In
Fig.1.15(a), a capacitor C is added to implement this filtering. This results in a reduced
residue amplitude at the output of the ISA.

Due to the filtering effect of the ISA, the digital reconstruction of the pipe output,
Y , from the individual stage outputs D0 and D1 becomes complex in a CT-pipe. For
example, in a DT-pipe, F (z) is a gain of 4, which is a simple shift operation. In a
CT-pipe, however, F (z) is a multi-tap filter. To summarize, the CT-pipe has a resistive

13
input impedance (R) as there is no sample and hold up front. The ISA acts a filter which
attenuates the out-of-band interferers and DAC image signals. Hence it can operate with
lower sampling rates. Thus a CT-pipe is an ideal candidate for wideband ADCs.

1.4 Objective and organization of the thesis

The first part of thesis is focussed on designing a filtering CT∆ΣM targeting 13-bit
resolution in a signal bandwidth of 1 MHz. The STF of this CT∆ΣM has a second
order low-pass response with a bandwidth of 2 MHz. The STF high frequency roll-
off is -100 dB/dec. We have made a thorough study of various architectural choices in
Chapter 2 and concluded that embedding a multiple feedback (Rauch) filter inside a
CIFF-B CT∆ΣM is the most power efficient architecture. Measurement results of the
CT∆ΣM showed a 76.7 dB peak SNDR and 41.8 dBFS out-of-band IIP3 .

The measured alias rejection of our filtering ADC was around 70 dB. This was
orders of magnitude worse compared to the ideal value (≈ 160 dB). We discovered a
hitherto unknown effect where the non-linearity of the first OTA, together with its par-
asitic capacitance, conspired to degrade the alias rejection of our CT∆ΣM. The theory
behind this intriguing effect is discussed in Chapter 3. We then extended this theory to
bandpass CT∆ΣMs in Chapter 4.

Next, we investigated wideband filtering ADCs where the CT∆ΣM is no longer

feasible. We designed a CT-pipeline ADC to digitize a signal bandwidth of 100 MHz
with a 12-bit resolution. The ADC is power-efficient, thanks to the Rauch architecture
which achieves second-order filtering with one OTA, and the use of resistive DACs.
The back-end is also power efficient thanks to the asynchronous SAR architecture. The
architectural choices, circuit design details and measurement results are discussed in
Chapter 5.

Chapter 6 concludes the thesis and gives suggestions for future work.

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