CHAPTER 2

AN INTERFERENCE-INSENSITIVE SWITCHED-
CAPACITOR CAPACITANCE-TO-DIGITAL CONVERTER

2.1 INTRODUCTION

One of the main challenges encountered while designing a capacitance-to-digital

converter (CDC) is its limited capacity to reject interference signals. The issue of

interference sensitivity, especially to power-line interference (both 50 Hz and 60 Hz),

is a particularly serious one when the sensors of interest have unshielded or partially

shielded sensing electrodes. Take for instance, the example of a touch sensor. One or

more of the sensor electrodes that facilitate touch detection could be exposed to the

interference signal because, in order to perform their designated function, their sensing

area needs to remain unshielded. In achieving interference rejection at a circuit level,

the approaches adopted so far predominantly include filtering techniques and

synchronous demodulation [29]. Although the synchronous demodulation method

achieves very low sensitivity to interference frequency, it requires a separate analog-to-

digital converter (ADC) to obtain a digital output. It is a relatively complex system and

needs a stable and accurate ac voltage reference signal. Also, the output of the

switching-type demodulator is sensitive to the interference signal if it happens to be an

odd harmonic of the reference frequency [29]. Another approach is to use a Sigma-

Delta based CDC [47], which achieves high resolution but has the extent of interference

rejection depend upon the selection/design of the filter. CDCs based on the dual-slope

integrating technique are expected to have very high interference rejection, but it has

been observed that such converters have their limitations [31]. This is because the value
of the de-integration time period is proportional to the measurand and need not be an

integral multiple of interference time period [32]. A previously reported CDC [48] does

achieve high interference rejection but at the cost of complexity and limited accuracy

as it requires a sinusoidal excitation source. Also, the scheme is not ideal for IC

realization since large value resistors are used in the design.

In this chapter, a new switched capacitor (SC) - CDC that has negligible sensitivity to

interference, by virtue of design, is presented. The scheme combines a SC relaxation

oscillator and an integrating type ADC. The use of the switched-capacitor topology

makes the proposed circuit suitable for fabrication as an IC [49]. Moreover, the

excitation is from a dc reference source, which is simple, and aids in improving the

accuracy of the final output. The design and operation of the new interference

insensitive SC-CDC, its error analysis, and its evaluation based on a hardware

prototype, are presented in the subsequent sections.

2.2 SWITCHED-CAPACITOR CAPACITANCE-TO-DIGITAL CONVERTER

A functional block diagram of the proposed SC-CDC is shown in Fig. 2.1. Here, the

sensor capacitor 𝐶𝑥 , the known (reference) capacitor 𝐶𝑅 , the feedback capacitor 𝐶𝐹 , the

operational amplifier 𝑂𝐴, along with single-pole double-throw (SPDT) switches 𝑆1, 𝑆2 ,

𝑆3 , 𝑆4 , constitute a SC integrator. It has two modes of operation – mode - 𝐶𝑥 , in which

𝐶𝑥 and 𝐶𝐹 form the integrator with 𝑂𝐴, and mode - 𝐶𝑅 , in which 𝐶𝑅 and 𝐶𝐹 form the

integrator with 𝑂𝐴. The mode is selected using the control signal 𝑣𝑠𝑒𝑙 .. The integrator

output 𝑣𝑜𝑖 is fed into the non-inverting terminal of the comparator 𝑂𝐶. The inverting

terminal of 𝑂𝐶 is connected to the pole of the SPDT switch 𝑆8 . Switch position marked

‘0’ of 𝑆8 is connected to a dc reference voltage 𝑉𝑅1, while the other contact is connected

to ground. Two capacitors, 𝐶𝐹1 and 𝐶𝐹2 , of value 2𝐶𝐹 , are connected to node n at the
19
output of 𝑂𝐴 via SPDT switches 𝑆5 (position ‘0’) and 𝑆7 (position ‘1’), respectively.

The other end of 𝐶𝐹1 and 𝐶𝐹2 are connected to switch 𝑆6 and ground, respectively.

Switch position marked ‘0’ of 𝑆6 is connected to 𝑉𝑅1 and that marked ‘1’ is connected

to ground. The comparator output is connected to the input of a D-flip flop, 𝐷𝐹𝐹, whose

operation is synchronized by a clock signal 𝑣𝑐𝑙 . The 𝐷𝐹𝐹 output, 𝑄, is used to control

the operation of switches 𝑆5 , 𝑆6 , 𝑆7 , directly, and 𝑆1, 𝑆4 through the digital logic

indicated in Fig. 2.1. 𝑆8 is directly controlled by the comparator output 𝑣𝑐 . 𝑄 is also an

input to the Control and Logic Unit (CLU). The CLU comprises of a timer and a counter.

The CLU counts the number of transitions (i.e. rising and falling edges) in 𝑄, for a given

time interval 𝑁𝑇𝐶 , where 𝑇𝐶 is the clock period and 𝑁 is a positive integer. In order to

achieve a high rejection to interference, the value of 𝑁𝑇𝐶 is set such that 𝑁𝑇𝐶 = 𝑛𝑇𝑖𝑛𝑡𝑟 ,

where 𝑇𝑖𝑛𝑡𝑟 is the period of the interference signal and 𝑛 is a positive integer. The CLU

outputs the control signal 𝑣𝑠𝑒𝑙 .

2.2.1 Operation of the CDC without Compensation Network

Let us assume that the initial voltage across 𝐶𝐹 be 0 V and the interference signal,

𝑣𝑖𝑛𝑡𝑟 = 0 V. When 𝑣𝑠𝑒𝑙 is high, the switched capacitor scheme is in mode - 𝐶𝑥 . When 𝑄

is low and 𝑣𝑐𝑙 is high, the switching signals 1 and 2 are high. Thus, 𝐶𝑥 charges to a dc

reference voltage 𝑉𝑅 via 𝑆1 while 𝑆2 is connected to ground. When both 𝑄 and 𝑣𝑐𝑙 are

low, 1 and 2 are low. Then, 𝑆1 is connected to ground, while 𝑆2 connects 𝐶𝑥 to 𝐶𝐹 .

𝐶𝑥 discharges, charging 𝐶𝐹 , in steps of 𝑉𝑅 (𝐶𝑥 /𝐶𝐹 ), for every clock cycle, until the

voltage 𝑣𝑜𝑖 reaches 𝑉𝑅1 . Then, 𝑣𝑐 flips from low to high and the inverting terminal of

𝑂𝐶 is connected to ground. At the end of that clock cycle, 𝑄 becomes high. From now

on, when 𝑣𝑐𝑙 is high, 1 is low and 2 is high. Therefore, 𝐶𝑥 has both its ends connected

to ground and hence discharges fully. However, when 𝑣𝑐𝑙 is low, 1 is high and 2 is
20
low. 𝐶𝐹 now discharges in steps (per clock) of 𝑉𝑅 (𝐶𝑥 /𝐶𝐹 ) due to the charge 𝑉𝑅 𝐶𝑥

supplied by 𝐶𝑥 , causing 𝑣𝑜𝑖 to gradually descend to 0 V which flips 𝑣𝑐 from high to

low. At the end of that clock cycle, 𝑄 becomes high. From now on, when 𝑣𝑐𝑙 is high, 1

is low and 2 is high. Therefore, 𝐶𝑥 has both its ends connected to ground and hence

discharges fully. However, when 𝑣𝑐𝑙 is low, 1 is high and 2 is low. 𝐶𝐹 now discharges

in steps (per clock) of 𝑉𝑅 (𝐶𝑥 /𝐶𝐹 ) due to the charge 𝑉𝑅 𝐶𝑥 supplied by 𝐶𝑥 , causing 𝑣𝑜𝑖 to

gradually descend to 0 V which 𝑣𝑐 flips 𝑣𝑐 from high to low. At the end of that clock

cycle 𝑄 becomes low. Thus, the proposed scheme operates as a relaxation oscillator and

𝑄 continues to oscillate from low to high and vice-versa. Integrator output 𝑣𝑜𝑖 in the 𝑘th

clock, in mode - 𝐶𝑥 , is given in (2.1), where 𝑀𝑠𝑔𝑛 is taken as 1 during the integration

phase and as −1 for the de-integration phase. When 𝑣𝑠𝑒𝑙 is low, the oscillator operates in

the same way as in mode - 𝐶𝑥 but with 𝐶𝑅 in the circuit instead of 𝐶𝑥 , through the

switches 𝑆3 and 𝑆4 . Integrator output 𝑣𝑜𝑖 in this case can be determined by replacing 𝐶𝑥

by 𝐶𝑅 in (2.1). Important waveforms of the CDC, while in mode-𝐶𝑥 , are shown in

Fig. 2.2. Note that in the absence of interference and circuit non-idealities, the lengths

of the ON-time and OFF-time of 𝑄 are the same.

𝑣𝑜𝑖 (𝑘) = 𝑣𝑜𝑖 (𝑘 − 1) + 𝑀𝑠𝑔𝑛 [𝑉𝑅 (𝐶𝑥 ⁄𝐶𝐹 )] (2.1)

To digitize the value of 𝐶𝑥 , the number of transitions of 𝑄 during the fixed time interval

𝑁𝑇𝐶 , corresponding to the mode - 𝐶𝑥 and mode - 𝐶𝑅 , need to be counted.

Taking the number of steps (clocks) to charge to 𝑉𝑅1 as 𝑛𝑥𝑖 and that to discharge from

𝑉𝑅1 to zero as 𝑛𝑥𝑑 , under ideal conditions, 𝑛𝑥𝑖 = 𝑛𝑥𝑑 = 𝑛𝑥 , during mode - 𝐶𝑥 , and

𝑛𝑥𝑖 = 𝑛𝑥𝑑 = 𝑛𝑅 , during mode - 𝐶𝑅 . Since the change in 𝑣𝑜𝑖 per clock cycle during

mode - 𝐶𝑥 and mode - 𝐶𝑅 is 𝑉𝑅 (𝐶𝑥 /𝐶𝐹 ) and 𝑉𝑅 (𝐶𝑅 /𝐶𝐹 ), respectively, 𝑛𝑥 and 𝑛𝑅 can

21
22
Fig. 2.1 Block diagram of the proposed SC CDC. Cx is the sensor capacitance. The compensation network is employed to correct for
the error in voi during the transitions in 𝑣𝑐 . The switch control signals 1 , 2 , 3 and 4 are derived using the switch control
block as per the logic given at the bottom left corner. 𝑣𝑖𝑛𝑡𝑟 represents the interference source. Its coupling capacitance 𝐶𝐶 to
the sensitive node 𝑚 of the CDC is indicated.
be expressed as in (2.2).

𝑉𝑅1 𝑉𝑅1 𝐶𝐹 𝑉𝑅1 𝑉𝑅1 𝐶𝐹

𝑛𝑥 = (𝑉 = and 𝑛𝑅 = (𝑉 = (2.2)
𝑅 𝐶𝑥 ⁄𝐶𝐹 ) 𝑉𝑅 𝐶𝑥 𝑅 𝐶𝑅 ⁄𝐶𝐹 ) 𝑉𝑅 𝐶𝑅

The total number of transitions, 𝑁𝑥 , in mode - 𝐶𝑥 , and 𝑁𝑅 , in mode - 𝐶𝑅 , corresponding

to 𝐶𝑥 and 𝐶𝑅 can be obtained as given in (2.3).

𝑁𝑇𝐶 𝑁𝑇𝐶
𝑁𝑥 = 𝑛 and 𝑁𝑅 = 𝑛 (2.3)
𝑥 𝑇𝐶 𝑅 𝑇𝐶

Substituting (2.2) in (2.3), we will get (2.4).

𝑁𝑇𝐶 𝑁𝑉𝑅 𝐶𝑥 𝑁𝑇𝐶 𝑁𝑉𝑅 𝐶𝑅

𝑁𝑥 = 𝑉𝑅1 𝐶𝐹 = and 𝑁𝑅 = 𝑉𝑅1 𝐶𝐹 = (2.4)
( )𝑇𝐶 𝑉𝑅1 𝐶𝐹 ( )𝑇𝐶 𝑉𝑅1 𝐶𝐹
𝑉𝑅 𝐶𝑥 𝑉𝑅 𝐶𝑅

From (2.4), 𝐶𝑥 can be obtained as in (2.5) in terms of the number of transitions, given

by the counter outputs 𝑁𝑥 and 𝑁𝑅 and the known capacitance 𝐶𝑅 .

𝑁
𝐶𝑥 = 𝑁𝑥 𝐶𝑅 (2.5)
𝑅

As can be seen from (2.5), the sensor capacitance 𝐶𝑥 is directly proportional to the output

count 𝑁𝑥 , realizing a digitizer with linear a characteristic.

In this CDC, the absence of an auto-zero phase leads to an error in the integration phase

of the first integration-de-integration cycle. As the total number of integration-de-

integration cycles in the measurement time is large, this error is negligible. However, to

completely remove this error, either an auto-zero phase can be included

or the transitions can be counted for a duration of 𝑁𝑇𝐶 after the first transition has

occurred in the DFF output.

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24
Fig. 2.2 Important waveforms recorded, using an oscilloscope, from the prototype without the compensation network. A zoom-
in of the clock signal 𝑣𝑐𝑙 and integrator output voltage 𝑣𝑜𝑖 are illustrated in the inset for ease of understanding. The
DFF output 𝑄, dc reference voltage 𝑉𝑅1 and ground potential for the channel-2 are indicated.
2.2.2 Effect of a Fractional 𝐕𝐑𝟏 /(𝐕𝐑 𝐂𝐱 /𝐂𝐅 ) on 𝑵𝒙 and Resolution

In practice, the ratio expressed by (2.2) will rarely be an integer. Hence 𝑣𝑜𝑖 can go

beyond 𝑉𝑅1, say by 𝑒𝑣𝑜𝑖 , during integration and similarly go below zero during

de-integration. The maximum value of 𝑒𝑣𝑜𝑖 ≅ (𝑉𝑅 𝐶𝑥 /𝐶𝐹 ) in mode - 𝐶𝑥 ; the same is

applicable during mode - 𝐶𝑅 . This will result in an error, similar to the quantization error

in an ADC, but occurring in each transition of 𝑄, introducing a noticeable deviation

from the expected value in the final output. The error occurring in each transition can be

neglected if the voltage steps (𝑉𝑅 (𝐶𝑥 /𝐶𝐹 ) and 𝑉𝑅 (𝐶𝑅 /𝐶𝐹 )) are extremely small

compared to 𝑉𝑅1. The voltage step can be kept very small by selecting a suitable (large)

𝐶𝐹 in comparison to 𝐶𝑥 and 𝐶𝑅 . This approach will increase 𝑛𝑥 and 𝑛𝑅 and reduce the

total number of transitions 𝑁𝑥 and 𝑁𝑅 , thereby reducing the resolution. Hence a better

solution, as the one discussed below, is required.

2.2.3 Operation of the CDC with Compensation Network

The total number of clocks 𝑛𝑡𝑜𝑡 between two consecutive low to high (or high to low)

transitions in 𝑄 is 𝑛𝑡𝑜𝑡 = 𝑛𝑥𝑖 + 𝑛𝑥𝑑 . As mentioned above, 𝑣𝑜𝑖 can go beyond 𝑉𝑅1 . Then,

′
𝑛𝑥𝑖 becomes 𝑛𝑥𝑖 = (𝑛𝑥𝑖 + 1). In this condition, an extra step is required in the

′
de- integration phase to reach 0 V. Thus, 𝑛𝑥𝑑 becomes 𝑛𝑥𝑑 = (𝑛𝑥𝑑 + 1). Similarly, 𝑛𝑥𝑖

and 𝑛𝑥𝑑 vary whenever 𝑣𝑜𝑖 goes below 0 V. This can occur in each transition of 𝑄 during

𝑁𝑇𝑐 and the cumulative error over this period can cause a noticeable error in 𝑁𝑥 .

The 𝑛𝑥𝑑 becoming 𝑛𝑥𝑑 + 1, as discussed above, can be avoided if 𝑣𝑜𝑖 can be brought

back to 𝑉𝑅1 before the de-integration starts. For this, the extra voltage, 𝑒𝑣𝑜𝑖 , needs to be

subtracted from the 𝑣𝑜𝑖 before the next clock. Once this is implemented, the sum of the

counts during integration and de-integration will be unaffected if one count is subtracted

25
 ′
from 𝑛𝑥𝑑 , whenever 𝑛𝑥𝑖 becomes 𝑛𝑥𝑖 . This can be achieved by subtracting twice the

extra voltage, i.e., 2𝑒𝑣𝑜𝑖 , instead of 𝑒𝑣𝑜𝑖 , from 𝑣𝑜𝑖 . This is realized using the

compensation scheme and illustrated in Fig. 2.3.

The compensation scheme consists of two new capacitors 𝐶𝐹1 and 𝐶𝐹2 , such that

𝐶𝐹1 = 𝐶𝐹2 = 2𝐶𝐹 , along with switches 𝑆5 , 𝑆6 and 𝑆7 . This portion of the circuit is

marked separately in Fig. 2.1. Initially, let the charge across 𝐶𝐹1 and 𝐶𝐹2 be zero. When

𝑄 is low, 𝑆5 , 𝑆6 , 𝑆7 are in position ‘0’. 𝐶𝐹1 is connected to 𝑣𝑜𝑖 via 𝑆5 and to 𝑉𝑅1 via 𝑆6 ,

whereas one end of 𝐶𝐹2 is connected to node m via 𝑆7 and the other to ground. In this

condition, 𝐶𝐹1 charges to (𝑣𝑜𝑖 − 𝑉𝑅1). When 𝑄 changes from low to high, 𝑆5 , 𝑆6 , 𝑆7 are

flipped to position ‘1’. At the instant right before this transition, 𝐶𝐹1 has the extra voltage

𝑒𝑣𝑜𝑖 = (𝑣𝑜𝑖 − 𝑉𝑅1 ) due to the fractional step error discussed above. When 𝑄 becomes

high, 𝐶𝐹1 is connected to node m via 𝑆5 and to ground via 𝑆6 , thus providing a

compensation charge related to 𝑒𝑣𝑜𝑖 into the inverting terminal of 𝑂𝐴. This charge will

reach 𝐶𝐹 and introduce a change in voltage of −2𝑒𝑣𝑜𝑖 . One half of the injected charge

brings 𝑣𝑜𝑖 back to 𝑉𝑅1 and thus (𝑛𝑥𝑑 + 1) to 𝑛𝑥𝑑 . The other half reduces 𝑛𝑥𝑑 further by

one count keeping 𝑛𝑡𝑜𝑡 unchanged, as explained above. Similarly, when 𝑄 is changed

from high to low, 𝐶𝐹2 is connected to node m and change 𝑣𝑜𝑖 by 2(0 − 𝑣𝑜𝑖 ), i.e., twice

the amount by which 𝑣𝑜𝑖 has gone below 0 V. The compensation and correction occur

in the same clock cycle as can be seen in Fig.2.3. Thus, the relaxation oscillator is now

compensated for the error discussed in section 2.2.2 and thus the resolution will not be

affected.

26
27
Fig. 2.3 Oscilloscope waveforms recorded from the prototype with compensation network. Signals 𝑣𝑐𝑙 , 𝑣𝑜𝑖 and 𝑄 of the SC
relaxation oscillator, when 𝑣𝑜𝑖 crosses 𝑉𝑅1 and 0 V are visible. It can be seen that the compensation scheme has
faithfully transferred the required voltage change, twice 𝑒𝑣𝑜𝑖 , to the next transition as illustrated in inset. This scheme
helps to improve the accuracy and resolution.
2.2.4 Insensitivity of CDC Output to Interference

1
In the proposed SC-CDC, 𝑛𝑡𝑜𝑡 𝑇𝑐 <<(𝑓 ) = 𝑁𝑇𝑐 , where 𝑓𝑖𝑛𝑡𝑟 is the interference
𝑖𝑛𝑡𝑟

frequency and multiple transitions occur in 𝑄 within a single cycle of the sine wave

interference signal, 𝑣𝑖𝑛𝑡𝑟 , coupled via capacitance 𝐶𝐶 , as shown in Fig. 2.1. Hence,

between two consecutive transitions in 𝑄 (duration of 𝑛𝑡𝑜𝑡 𝑇𝑐 ), 𝑣𝑜𝑖 due to interference

can be approximated as a straight line with a finite slope equal to the average slope of
𝐶
the signal − 𝐶𝑐 𝑣𝑖𝑛𝑡𝑟 during 𝑛𝑡𝑜𝑡 𝑇𝑐 . The slope of this line will be different for the next
𝐹

integration-de-integration cycle, such that if we plot these segments together during

𝑇𝑖𝑛𝑡𝑟 , its shape will be sinusoidal. Let the contribution of the interference to 𝑣𝑜𝑖 during

𝑛𝑥𝑖 𝑇𝑐 be 𝑛𝑖𝑛𝑡𝑟 counts. Thus, the number of clocks during integration will increase to

𝑛𝑥𝑖 +𝑛𝑖𝑛𝑡𝑟 . However, in the subsequent de-integration phase the corresponding number

of clocks will decrease approximately by the same amount i.e., 𝑛𝑥𝑑 − 𝑛𝑖𝑛𝑡𝑟 . Thus,

𝑛𝑡𝑜𝑡  𝑛𝑥𝑖 +𝑛𝑥𝑑 , causing negligible change in the final output. During negative cycle of

interference signal, the polarity of 𝑣𝑖𝑛𝑡𝑟 will change and the contribution will become

+𝑛𝑖𝑛𝑡𝑟 . Still, the count 𝑛𝑡𝑜𝑡 will be almost unaffected. Since the effect of interference is

significantly reduced within an integration - de-integration cycle, the circuit has a good
𝑛 1
rejection to interference even if ≠ 𝑁𝑇𝑐 , provided 𝑛𝑡𝑜𝑡 𝑇𝑐 <<𝑓 . If both
𝑓𝑖𝑛𝑡𝑟 𝑖𝑛𝑡𝑟

conditions are fulfilled, the interference rejection becomes stronger. The previous

explanation is valid as long as the current injected by 𝑣𝑖𝑛𝑡𝑟 is a small amount in

comparison to the charging current introduced by 𝐶𝑥 in mode- 𝐶𝑥 or that by 𝐶𝑅 in mode-

𝐶𝑅 . This condition limits the maximum 𝑣𝑖𝑛𝑡𝑟 allowed for the CDC for a given 𝐶𝑥 or 𝐶𝑅 .

The criteria to be maintained to ensure negligible effect due to 𝑣𝑖𝑛𝑡𝑟 is explained below.

28
2.2.5 Condition for Negligible Effect Due to Interference

For further analysis, while preserving the accuracy, 𝑣𝑖𝑛𝑡𝑟 is assumed to be a triangular

wave, instead of a sine wave, with an amplitude 𝑉𝑡𝑟 and a time period 𝑇𝑡𝑟 . 𝑉𝑡𝑟 is set such

that the magnitude of the slope of the triangular wave is equal to slope of interfering

sinewave at zero crossing. The amount of change ∆𝑣𝑜𝑖𝑡𝑟 in 𝑣𝑜𝑖 due to 𝑣𝑖𝑛𝑡𝑟 , during 𝑇𝐶 ,

is given by (2.6).

𝐶 𝑇𝐶
∆𝑣𝑜𝑖𝑡𝑟 = 𝐶𝐶 𝑉𝑡𝑟 𝑇 (2.6)
𝐹 𝑡𝑟 ⁄4

Then, 𝑛𝑥𝑖 and 𝑛𝑥𝑑 can be written, respectively as

𝑉𝑅1 𝑉𝑅1
𝑛𝑥𝑖 = 𝐶𝑥 and 𝑛𝑥𝑑 = 𝐶 . (2.7)
𝑉𝑅 ± ∆𝑣𝑜𝑖𝑡𝑟 𝑉𝑅 𝑥 ∓ ∆𝑣𝑜𝑖𝑡𝑟
𝐶𝐹 𝐶𝐹

Substituting (2.2) and (2.6) in (2.7) and rearranging, we get (2.8).

𝑛𝑥 𝑛
𝑥
𝑛𝑥𝑖 = (1±Ɛ) and 𝑛𝑥𝑑 = (1∓Ɛ) (2.8)

𝑉 𝐶 𝑇
In (2.8), Ɛ = 4 𝑉𝑡𝑟 𝐶𝐶 𝑇 𝐶 . On evaluating Ɛ, it is found that Ɛ << 1 for the prototype
𝑅 𝑥 𝑡𝑟

developed; this condition can be fulfilled at the design stage. Under this condition, the

equations for 𝑛𝑥𝑖 , 𝑛𝑥𝑑 and 𝑛𝑡𝑜𝑡 can be simplified using the Taylor series expansion for

(1-x)-1 and (1-x2)-1, where |x| < 1. Thus the relative error 𝑒𝑛𝑡𝑜𝑡 in 𝑛𝑡𝑜𝑡 ,

𝑒𝑛𝑡𝑜𝑡 = (𝑛𝑡𝑜𝑡 − 2𝑛𝑥 )⁄2𝑛𝑥 is obtained. Similarly, the relative error 𝑒𝑛𝑥 in 𝑛𝑥𝑖 or 𝑛𝑥𝑑 is

determined. The expressions for 𝑒𝑛𝑡𝑜𝑡 and 𝑒𝑛𝑥 are as in (2.9).

𝑒𝑛𝑡𝑜𝑡 = ( Ɛ2 + Ɛ4 +. . ) and 𝑒𝑛𝑥 = ( Ɛ + Ɛ2 + Ɛ3 +. . ) (2.9)

29
 𝑒𝑛𝑥
From (2.9), it can be obtained that  1/Ɛ. Thus, the error in 𝑛𝑡𝑜𝑡 due to
𝑒𝑛𝑡𝑜𝑡

interference is  1/Ɛ times lower than that in 𝑛𝑥𝑖 or 𝑛𝑥𝑑 . For example, when there is

10% error in 𝑛𝑥𝑖 or 𝑛𝑥𝑑 , the error in 𝑛𝑡𝑜𝑡 will be about 1%. This serves as a proof for

the cancellation effect within 𝑛𝑡𝑜𝑡 𝑇𝐶 , mentioned in section 2.2.4. To verify this, a

simulation was performed using LTSPICE for different magnitudes of interference

current, corresponding to different 𝐶𝐶 . The associated 𝑣𝑜𝑖 and 𝑄 observed are shown in

Fig. 2.4. As seen, the error in 𝑛𝑡𝑜𝑡 is very small, although 𝑛𝑥𝑖 and 𝑛𝑥𝑑 are affected. Based

on (2.9), the total error counts/clocks due to 𝑣𝑖𝑛𝑡𝑟 during 𝑁𝑇𝑐 can be approximated to

𝑁 𝑛𝑡𝑜𝑡
Ɛ2 𝑛𝑡𝑜𝑡 . (𝑛 ) = Ɛ2 𝑁. To avoid occurrence of a new transition in 𝑄, Ɛ2 < .
𝑡𝑜𝑡 2𝑁

2.3 EFFECT OF NON-IDEALITIES

This section analyses the effect of non-idealities of the circuit parameters on the final

output of the proposed SC-CDC. The non-idealities considered are the parasitic

capacitances and leakage resistance of the sensor, offset voltage and bias currents of

opamps and comparators, charge injection, ON-resistance and switching-time delay of

switches. The impact of the mismatch between 𝐶𝐹1 and 𝐶𝐹2 , and charge injection of the

switches used in the compensation network have been analyzed separately. Additionally,

the effect of noise of the final output of the SC-CDC has been studied.

2.3.1 Parasitic Capacitance and Leakage Resistance of the Sensor

The equivalent circuit of sensor, 𝐶𝑥 , with the leakage resistance, 𝑅𝑃 , and the parasitic

capacitances, 𝐶𝑆1 and 𝐶𝑆2 , is shown in Fig.2.5. In mode- 𝐶𝑥 , 𝑅𝑃 does not affect the

integrator output as long as 𝑅𝑃 is very large compared to the ON-resistance 𝑅𝑂𝑁 of the

switch. In its presence, for 𝑆1 and 𝑆2 with same ON resistance 𝑅𝑂𝑁 , the expression for

30
31
Fig. 2.4 Effect of sinusoidal interference on voi. The waveforms are obtained from a simulation study using LTSPICE. The
CDC was implemented in the LTSPICE using equivalent models of the ICs employed to realize the same in
hardware [49]. vintr was set as 325sin100t volts. The 𝐶𝐶 (shown in Fig. 2.1) was varied from 0 to 5.5 pF in steps of
1.375 pF. Error in nx for the largest 𝐶𝐶 is 16.7%, while that in ntot is only 2%. The error is reduced by about 8 times,
showing the expected trend.
 2 (𝑒 −𝑇𝑐 ⁄2𝑅𝑒𝑓𝑓 𝐶𝑥
𝑉𝑅 𝐶𝑥 𝑅𝑝 −1)
the change in 𝑣𝑜𝑖 per clock cycle during the integration phase is ( ).
𝐶𝐹 (𝑅𝑝 +𝑅𝑂𝑁 )2

−𝑇𝑐 ⁄2𝑅𝑒𝑓𝑓 𝐶𝑥
𝑉𝑅 𝑇𝑐 𝑅𝑂𝑁 𝑉𝑅 𝐶𝑥 𝑅𝑝 (𝑒 −1)
and that during the de-integration phase is (𝑅 . (𝑅 )-( ) ,
𝑒𝑓𝑓 𝐶𝐹 𝑝 +2𝑅𝑂𝑁 ) 𝐶𝐹 (𝑅𝑝 +2𝑅𝑂𝑁 )

2𝑅𝑝 𝑅𝑂𝑁
where 𝑅𝑒𝑓𝑓 = 𝑅 . In the case of the standard capacitor, with air as the dielectric,
𝑝 + 2𝑅𝑂𝑁

used as 𝐶𝑥 , the value of 𝑅𝑝 is in tens of mega-ohms. Also, in the prototype implemented

using the components in Table 2.1, 𝑅𝑂𝑁 =400 Ω. Thus, the effect of 𝑅𝑝 will be

negligible. This is valid for, say capacitive proximity sensors with air as the dielectric.

In the case of capacitive sensors with lower values of 𝑅𝑝 , the integration phase gets

extended, due to the discharge of 𝐶𝑥 through 𝑅𝑝 , if 𝑅𝑂𝑁 is not negligible, and the de-

integration phase gets shortened, due to the current through 𝑅𝑝 charging 𝐶𝐹 . As these

effects are opposing, partial cancelation of the resistance effect occurs as far as the total

time ntotTC, is concerned.

To test the effect of Rp in the prototype, 𝑅𝑝 was varied from 25 MΩ to 5 MΩ in steps of

5 MΩ and the error in 𝑁𝑥 , corresponding to 𝐶𝑥 = 20 pF, varied 0.1% to 2.6% from the

expected value. The effect can be reduced if the duration of current through 𝑅𝑝 can be

reduced, by increasing the clock frequency. This was verified when the errors

corresponding to the varied 𝑅𝑝 was found to reduce to 0.02% to 1.1% by doubling the

clock frequency. Thus, in applications where 𝑅𝑝 varies considerably, such as humidity

sensors, a high-frequency clock can be employed with suitable components and ICs in

the proposed design.

In the presence of input offset voltage 𝑉𝑂𝑆𝐴 , of OA, a current of magnitude  𝑉𝑂𝑆𝐴 ⁄𝑅𝑃

flows through 𝑅𝑃 . This current leads to an additional charge of voltage 𝑉𝑂𝑆𝐴 𝑇𝐶 ⁄2𝑅𝑃 𝐶𝐹

in 𝑣𝑜𝑖 . This additional voltage step does not impact the final output as long as 𝑉𝑅 >>𝑉𝑂𝑆𝐴 .

32
In mode-𝐶𝑥 , when 𝑆1 = 1, 𝐶𝑆1 charges to 𝑉𝑅 and discharges through 𝑆1 when 𝑆1 = 0. In

the case of 𝐶𝑆2 the terminal connected to 𝑆2 is either connected to the ground (𝑆2 = 1)

or virtual ground (𝑆2 = 0) and thus it has no role to play. In the presence of 𝑉𝑂𝑆𝐴 , 𝐶𝑆2

charges to 𝑉𝑂𝑆𝐴 when 𝑆2 = 0, thus contributing an additional voltage 𝑉𝑂𝑆𝐴 𝐶𝑆2 ⁄𝐶𝐹 in 𝑣𝑜𝑖

per clock.

2.3.2 Input Offset Voltage and Bias Current of the Operational Amplifier OA

The input offset voltage 𝑉𝑂𝑆𝐴 contributes an additional voltage of 𝑉𝑂𝑆𝐴 (𝐶𝑥 ⁄𝐶𝐹 ) to the

voltage step during the integration and de-integration operations. This occurs in both

these phases of mode-𝐶𝑥 and mode-𝐶𝑅 and the number of transitions are, respectively,

2 2
𝑉𝑅2 −𝑉𝑂𝑆𝐴 𝐶𝑥 𝑉𝑅2 −𝑉𝑂𝑆𝐴 𝐶𝑅
𝑁𝑥 = 𝑁 and 𝑁𝑅 = 𝑁 . (2.10)
𝑉𝑅2 𝐶𝐹 𝑉𝑅2 𝐶𝐹

On simplification, (2.5) can be obtained from (2.10). This means that the 𝑉𝑂𝑆𝐴 does not

affect the final output of the proposed SC-CDC.

Bias current 𝐼𝐵𝐴 of opamp 𝑂𝐴 contributes a voltage (− 𝐼𝐵𝐴 𝑇𝐶 ⁄𝐶𝐹 ) to the voltage step

during the integration and de-integration phases. Thus, the number of transitions in

mode-𝐶𝑥 and mode-𝐶𝑅 are, respectively,

[(𝑉𝑅 𝐶𝑥 )2 −(𝐼𝐵𝐴 𝑇𝐶 )2 ] [(𝑉𝑅 𝐶𝑅 )2 −(𝐼𝐵𝐴 𝑇𝐶 )2 ]

𝑁𝑥 = 𝑁 and 𝑁𝑅 = 𝑁 (2.11)
𝑉𝑅2 𝐶𝑥 𝐶𝐹 𝑉𝑅2 𝐶𝑅 𝐶𝐹

From (2.11), the ratio (𝑁𝑥 ⁄𝑁𝑅 ) can be obtained as in (2.12).

𝑁𝑥 𝐶 [ 1−(𝐼𝐵𝐴 𝑇𝐶 ⁄𝑉𝑅 𝐶𝑥 )2 ]
= 𝐶𝑥 2
(2.12)
𝑁𝑅 𝑅 [ 1−(𝐼𝐵𝐴 𝑇𝐶 ⁄𝑉𝑅 𝐶𝑅 ) ]

As long as 𝐼𝐵𝐴 𝑇𝐶 ≪ 𝑉𝑅 𝐶𝑥 , the error introduced can be neglected. In the prototype built,

for the nominal value of 𝐶𝑥 = 20 pF, this error works out to be 0.00004%.
33
 2.3.3 Input Offset Voltage and Input Bias Current of the Comparator 𝐎𝐂

In the presence of an input offset voltage 𝑉𝑂𝑆𝐶 of 𝑂𝐶, 𝑣𝑜𝑖 swings from 𝑉𝑂𝑆𝐶 to (𝑉𝑅1 +

𝑉𝑂𝑆𝐶 ) instead of 0 to 𝑉𝑅1. Since the swing in 𝑣𝑜𝑖 is 𝑉𝑅1 in both cases, the transition count

in both modes remains unaffected. As bias current 𝐼𝐵𝐶 of 𝑂𝐶 is in nA and ON-resistance

𝑅𝑂𝑁 of the switch in a few hundred ohms, the voltage drop 𝐼𝐵𝐶 𝑅𝑂𝑁 is negligible. Even

if the 𝐼𝐵𝐶 𝑅𝑂𝑁 is present, the effect will be equivalent to having a 𝑉𝑂𝑆𝐶 , which does not

affect the output, as explained.

2.3.4 Charge Injection, ON-resistance and Switching-time Delay of the Switches

To analyze the effect of charge injection, the switch can be replaced by the charge

injection model given in [50], as shown in Fig. 2.5. The charge injected at the output of

each switch is a combination of charges generated during the breaking of contact, say

position ‘1’, and making of the next, say position ‘0’.

Fig. 2.5 The leakage resistance 𝑅𝑝 and parasitic capacitances 𝐶𝑆1 and 𝐶𝑆2
associated with 𝐶𝑥 are given. Switches 𝑆1 and 𝑆2 are represented with
injection model of MOSFET based switch.

Let the first iteration begin in mode-𝐶𝑥 , with 𝑆1= 1 and 𝑆2 = 1. Here the injected charges

do not affect 𝑣𝑜𝑖 since 𝐶𝑥 is not connected to OA. When 𝑆1= 0 and 𝑆2 = 0, the charge

34
𝑄10 = (𝑄11𝑂𝐹𝐹 + 𝑄10𝑂𝑁 ) is injected at the output of S1 , and 𝑄20 = (𝑄21𝑂𝐹𝐹 + 𝑄20𝑂𝑁 )

at the output of S2 . This causes an additional charge 𝑄𝑖𝑛𝑡 = (𝑄10 + 𝑄20 ) to be

transferred to 𝐶𝐹 causing a voltage change in 𝑣𝑜𝑖 .

In the de-integration phase when 𝑆1= 0 and 𝑆2 = 1, 𝐶𝑥 discharges to the ground. When

𝑆1= 1 and 𝑆2 = 0, 𝑄11 = (𝑄10𝑂𝐹𝐹 + 𝑄11𝑂𝑁 ), and 𝑄20 = (𝑄21𝑂𝐹𝐹 + 𝑄20𝑂𝑁 ) are injected

at the outputs of 𝑆1 and 𝑆2 , respectively. This causes an additional charge transfer of

𝑄𝑑𝑒−𝑖𝑛𝑡 = (𝑄11 + 𝑄20 ) to 𝐶𝐹 . As the switching sequence is the same, a similar effect is

present during the integration and de-integration in mode-𝐶𝑅 .

If 𝑄𝑖𝑛𝑡 = 𝑄𝑑𝑒−𝑖𝑛𝑡 then the injected charges will aid the integration and oppose the de-

integration causing a negligible effect in number of the transitions, 𝑁𝑥 in mode-𝐶𝑥 and

𝑁𝑅 in mode-𝐶𝑅 . Otherwise, the number of transitions will vary and so it is advisable to

use switches like MAX4709, used in the prototype of the proposed CDC, which is

designed for zero charge injection.

The equivalent circuit with the ON-resistance (𝑅𝑂𝑁 ) of the switch is shown in Fig. 2.5.

During both integration and de-integration phases, charging and discharging of 𝐶𝑥 via

𝑅𝑂𝑁1 and 𝑅𝑂𝑁2 takes place with time constants 𝜏𝑐ℎ and 𝜏𝑑𝑐ℎ , respectively. In the

proposed system 𝜏𝑐ℎ = 𝜏𝑑𝑐ℎ = 𝜏 = (𝑅𝑂𝑁1 + 𝑅𝑂𝑁2 )𝐶𝑥 . 𝑅𝑂𝑁1 and 𝑅𝑂𝑁2 have a

negligible impact on 𝑣𝑜𝑖 as long as 𝜏 <<𝑇𝐶 ⁄2, where 𝑇𝐶 is the clock period.

As long as the delay, 𝑇𝑑𝑆𝑊 , is much smaller than 𝑇𝐶 ⁄2, it does not affect the number of

transitions. This condition holds true in the case of MAX4709 (𝑇𝑑𝑆𝑊 = 170 ns) used in

the implementation of the prototype.

35
2.3.5 Effect of Mismatch between 𝑪𝑭𝟏 and 𝑪𝑭𝟐 and Charge Injection of Switches

in the Compensation Network

For the compensation scheme to work effectively, 𝐶𝐹1 = 𝐶𝐹2 = 2𝐶𝐹 . If not, the amount of

charge that the network provides at the input of the proposed SC-CDC will result in

under-compensation or over-compensation leading to an error in 𝑣𝑜𝑖 for every transition

in 𝑣𝑐 .

In the first iteration with Q = 0, 𝐶𝐹1 is connected between 𝑣𝑜𝑖 and 𝑉𝑅1. Then charge

𝑄50𝑂𝑁 is injected by S5 and 𝑄60𝑂𝑁 by S6 . Still 𝐶𝐹1 charges to 𝐶𝐹1 (𝑣𝑜𝑖 − 𝑉𝑅1) as it is

connected across that voltage. Also, 𝑄70𝑂𝑁 is injected by S7 into 𝐶𝐹2 . Since one end of

S7 is connected to the input of 𝑂𝐴, this affects the 𝑣𝑜𝑖 . When 𝑄 = 1, S5 injects (𝑄50𝑂𝐹𝐹 +

𝑄51𝑂𝑁 ) at its output, S6 injects (𝑄60𝑂𝐹𝐹 + 𝑄61𝑂𝑁 ). The resultant voltage across 𝐶𝐹1 is

present at the input of OA in addition to the voltage developed across 𝐶𝑥 . In this state,

𝐶𝐹2 is charged to the excess in 𝑣𝑜𝑖 beyond 0 V and S7 injects (𝑄70𝑂𝐹𝐹 + 𝑄71𝑂𝑁 ) at its

output. The final charge developed across 𝐶𝐹2 is only due to the excess voltage beyond

0 V. As charge injection can affect the performance of the compensation mechanism and

hence it is preferable to use switches with zero charge injection like MAX4709 used in

the prototype.

2.3.6 Effect of Noise

In the proffered scheme the switches 𝑆1 − 𝑆7, opamp 𝑂𝐴 and comparator 𝑂𝐶 introduces

noise in 𝑣𝑜𝑖 . In a MOS switch, the notable types of noise are thermal noise and flicker

(1/f) noise. Since in the proposed circuit the current flow in the switches consists of short

pulses occurring at the clock rate, the flicker noise has a negligible effect [51]. Thus, in

the analysis, the thermal noise due to 𝑆1 − 𝑆7 , 𝑂𝐴 and 𝑂𝐶 are considered. To perform

36
the analysis each switch is replaced by a noise voltage and ON-resistance and 𝑉𝑅 , 𝑉𝑅1

are grounded.

When 𝑆1 = 1 and 𝑆2 = 1 the circuit containing 𝐶𝑥 can be represented by the branch

given in Fig. 2.6 (a). The ON-resistances and noise voltages are pair-wise combined as
𝑘 𝑇
in Fig. 2.6 (b). The noise power accumulated by 𝐶𝑥 in this case, is ̅̅̅̅̅̅̅̅
2
𝑣𝑐𝑥,1,1 = 𝐶𝐵 , where
𝑥

𝑘𝐵 is the Boltzmann constant and T is the temperature in Kelvin. When 𝑆1 = 0 and 𝑆2 =

0, the equivalent circuit is as shown in Fig. 2.6 (c). Here 𝐶𝑥 acquires an additional charge

𝑘 𝑇
due to thermal noise, ̅̅̅̅̅̅̅̅
2
𝑣𝑐𝑥,0,0 = 𝐶𝐵 , from 𝑆1 and 𝑆2 , in position ‘0’ and ̅̅̅̅̅̅̅
2
𝑣𝑐𝑥,𝑜𝑝 , due to 𝑂𝐴.
𝑥

2 = ̅̅̅̅̅̅̅̅
Thus, noise power across 𝐶𝑥 , ̅̅̅̅
𝑣𝑐𝑥 2
𝑣𝑐𝑥,1,1 ̅̅̅̅̅̅̅̅
+𝑣 2 ̅̅̅̅̅̅̅
2
𝑐𝑥,0,0 +𝑣𝑐𝑥,𝑜𝑝 . In this state, the charge in

𝐶𝑥 is transferred to 𝐶𝐹 resulting in the noise charge stored in 𝐶𝐹 , ̅̅̅̅̅̅̅

2
𝑞𝑐𝑓|𝑐𝑥 = 2𝑘𝐵 𝑇𝐶𝑥 +

𝐶𝑥2 ̅̅̅̅̅̅̅
2
𝑣𝑐𝑥,𝑜𝑝 .

̅̅̅̅̅̅̅̅̅̅̅
The noise voltages 𝑣 2
𝑖𝑛𝑡,𝑢𝑐𝑚𝑝 at the output of the proposed SC-CDC, in the integration

phase, is obtained by summing the noise powers at the integrator output ̅̅̅̅̅
2
𝑣𝑂𝐴 and at the

input of the comparator, ̅̅̅̅̅

2
𝑣𝑂𝐶 . i.e.,

̅̅̅̅̅̅̅̅̅̅̅
2 2 2 ̅̅̅̅̅̅̅
2 ̅̅̅̅
2 ̅̅̅̅̅
2
𝑣 𝑖𝑛𝑡,𝑢𝑐𝑚𝑝 = [((1⁄𝐶𝐹 ) (2𝑘𝐵 𝑇𝐶𝑥 + 𝐶𝑥 𝑣𝑐𝑥,𝑜𝑝 )) + 𝑣𝑜𝑝 ] + 𝑣𝑂𝐶 (2.13)

When 𝑣𝑜𝑖 approaches 𝑉𝑅1 the branch of compensation network with 𝐶𝐹1 , comes into

play. The equivalent circuit for noise analysis of the proposed SC-CDC, including the

compensation network, is given in Fig. 2.6 (d). When 𝑆5 = 0 and 𝑆6 = 0, the

corresponding noise voltages 𝑣𝑛5 and 𝑣𝑛6 contribute a noise across 𝐶𝐹1 , ̅̅̅̅̅̅̅
2
𝑣𝐶𝐹1,0 , and

when the flip in the comparator output, 𝑄, occurs and 𝑆5 = 1 and 𝑆6 = 1, the existing

̅̅̅̅̅̅̅
noise voltage across 𝐶𝐹1 , and additional noise, 𝑣 2
𝐶𝐹1,1 is fed into the input of 𝑂𝐴.

37
38
Fig. 2.6 (a) Switches S1 and S2, on either sides of Cx, are replaced with equivalent noise voltages and ON - resistances for
S1 = 1 and S2 = 1. (b) The independent noise voltages and ON- resistances are combined assuming RON1,1 = RON2,1 =
RON (c) The proposed circuit is redrawn for noise analysis for S1 = 0, S2 = 0 and opamp OA without the compensation
network (d) The proposed circuit, including the compensation network, with noise sources and ON-resistances.
Thus, the total noise voltage including the effect of the compensation circuit is given by

(2.14). From (2.14) it can be seen that the cumulative noise power is proportional to

(1⁄𝐶𝐹2 ).

̅̅̅̅̅
2 2 2 ̅̅̅̅̅̅̅
2 2 ̅̅̅̅̅̅̅
2 ̅̅̅̅̅̅̅
2 ̅̅̅̅
2 ̅̅̅̅̅
2
𝑣 𝑖𝑛𝑡 = [(1⁄𝐶𝐹 ) (2𝑘𝐵 𝑇𝐶𝑥 + 𝐶𝑥 𝑣𝑐𝑥,𝑜𝑝 + 𝐶𝐹1 (𝑣𝐶𝐹1,0 + 𝑣𝐶𝐹1,1 )) + 𝑣𝑜𝑝 +𝑣𝑂𝐶 ] (2.14)

On performing analysis in a similar manner during the de-integration phase the noise

̅̅̅̅̅̅̅̅̅
2
𝑣𝑑𝑒−𝑖𝑛𝑡 is obtained as

̅̅̅̅̅̅̅̅̅ 1 2 ̅̅̅̅̅̅̅
2
𝑣𝑑𝑒−𝑖𝑛𝑡 = [𝐶 2 (2𝑘𝐵 𝑇𝐶𝑥 + 𝐶𝑥2 ̅̅̅̅̅̅̅
2
𝑣𝑐𝑥,𝑜𝑝 + 𝐶𝐹2 2
(𝑣𝐶𝐹2,1 + ̅̅̅̅̅̅̅
2
𝑣𝐶𝐹2,0 2 ] + ̅̅̅̅̅
))) + ̅̅̅̅
𝑣𝑜𝑝 2
𝑣𝑂𝐶 (2.15)
𝐹

The value of ̅̅̅̅̅

2
𝑣𝑖𝑛𝑡 and ̅̅̅̅̅̅̅̅̅
2
𝑣𝑑𝑒−𝑖𝑛𝑡 have been calculated as around 0.15 nV2 for the prototype,

2 = ̅̅̅̅̅
using ̅̅̅̅
𝑣𝑜𝑝 2
𝑣𝑂𝐶 , at room temperature 300 K. Its RMS value is about 4000 times smaller

𝐶
than the typical change in 𝑣𝑜𝑖 per clock, i. e. 𝑉𝑅 (𝐶𝑥 ), hence the effect is negligible.
𝐹

2.4 EXPERIMENTAL SETUP AND RESULTS

The components used to implement the prototype are given in Table 2.1. The

microcontroller was programmed to count and record 𝑁𝑥 and 𝑁𝑅 . In order to test the

prototype CDC, the sensor 𝐶𝑥 was emulated using a variable capacitor, with negligible

leakage conductance, from Rohde and Schwarz. It was calibrated using a 5½ digit LCR

meter HP 4274A with an accuracy of 0.1%. The entire system is powered by ±5 V

power supply.

2.4.1 Testing the Linearity, Resolution and Repeatability

In order to test the linearity, the prototype was operated with 𝐶𝑥 , emulated by a standard

capacitance box with air medium, varied from 10 pF to 32.5 pF in steps of 2.5 pF. This

39
range encompasses that of the capacitive proximity sensors reported in [52]-[54], and

can be changed, by suitably selecting the value of the 𝐶𝐹 in the SC integrator, such that

𝐶𝐹 ≫ 𝐶𝑥 , 𝐶𝑅 [32].

The number of transitions, 𝑁𝑥 , corresponding to each value of 𝐶𝑥 , was recorded setting

𝑁𝑇𝐶 = 100 ms and 𝐶𝑅 = 20 pF. For every value of 𝐶𝑥 , the output was computed using

(2.5) for 𝑁 (=16000) clock cycles. The results recorded from this study are shown in

Fig. 2.7. As expected, the output characteristic was linear and the maximum non-

linearity error was found to be 0.4%.

Repeatability of the output was verified by setting 𝐶𝑥 = 25 pF and recording the output

of the CDC for 30 consecutive measurements. The measurements made for 𝑁 cycles

resulted in an ENOB = 9.55 bits and SNR = 59.27 dB, while those for 5 𝑁 cycles gave

an improved ENOB = 11.13 bits and SNR = 68.77 dB, as expected. Under this

measurement condition, the resolution of the prototype CDC in terms of capacitance

observed is 11 fF with an estimated accuracy of 0.2%. The associated parameters were

computed using this measured data, by employing the equations given in Table 2.2. The

results are also given in Table 2.2. The repeatability was found to be 0.11% which, along

with the other parameters given in Table 2.2, shows the usefulness of the prototype.

2.4.2 Testing the Usefulness of Compensation Circuit and Effect of the

Duration N𝑻𝑪

To evaluate the effectiveness of the compensation scheme, the prototype was tested

under both the uncompensated and compensated conditions at the full-scale value of

𝐶𝑥 = 32.5 pF. The results obtained are given in Table 2.3. An improvement in the

repeatability is observed when the compensation circuit was used. The compensation

corrects for the random error in 𝑛𝑡𝑜𝑡 owing to the issue of 𝑣𝑜𝑖 going beyond 𝑉𝑅1 and 0,

40
 Table 2.1 Components of the SC-CDC Prototype

Component Part/Value Component Part/Value

Using LM385-
𝑉𝑅 𝑉𝑅1
LM385-2.5V 1.2V

𝑆1 − 𝑆8 MAX4709 𝐴𝑁𝐷 𝑔𝑎𝑡𝑒 DM74LS08

𝐷𝐹𝐹 HD14013BP 𝑋𝑂𝑅 𝑔𝑎𝑡𝑒 HD74LS86

𝑂𝐶 LM311 𝑂𝐴 OPA227
𝐶𝐿𝑈 MSP430 𝑇𝐶 12.5 µs
Using 1 nF
𝑣𝑐𝑙 𝐶𝐹
AFG3022B
10 pF to 𝐶𝑅 20 pF
𝐶𝑥
32.5 pF

Fig. 2.7 Results obtained on testing the prototype CDC for the range of
𝐶𝑥 = 10 pF to 32.5 pF. The observed non-linearity error (%) for each
measurement is also shown.

41
 Table 2.2 Repeatability Study of SC-CDC
Parameter Formula Value
Signal-to-noise ratio ∑𝑀𝑖=1 𝐶(𝑖)
2
𝑆𝑁𝑅 = 10 𝑙𝑜𝑔 68.77 dB
(SNR) ∑𝑀
𝑖=1[𝐶(𝑖) − 𝐶 ]
̅2

∑𝑀 ̅2
𝑖=1[𝐶(𝑖) − 𝐶 ]
Standard Deviation, 𝜎 𝜎= √ 4.68 fF
𝑀−1

Accuracy, 𝑒𝑟 (Relative |𝐶𝑚 − 𝐶𝑒 |

𝑒𝑟 = × 100% 0.2%*
error) 𝐶𝑒

(𝑆𝑁𝑅 − 1.76)
Resolution (ENOB), 𝑛 bits 𝑛= 11.13 bits
6.02
∆
% Linearity, 𝑒𝑙 𝑒𝑙 = 𝐶 𝑚𝑎𝑥 × 100% 0.4%*
−𝐶
𝑢 𝑙
∆
Repeatability, 𝑑𝑅 𝑑𝑅 = 𝐶𝑟𝑚𝑎𝑥 × 100% 0.11%
−𝐶 𝑢 𝑙

*
Computed using the data presented in Fig. 2.7.
𝐶(𝑖) = ith capacitance measurement
𝐶̅ = average value of the measured capacitance data
𝑀 = total number of measurements recorded for the repeatability study
𝐶𝑚 = measured value of capacitance
𝐶𝑒 = expected value of capacitance (true value, for Cx = 25 pF)
∆𝑚𝑎𝑥 = maximum difference between measured capacitance values and
the fitted line
𝐶𝑢 = upper limit of the measurement range of CDC
𝐶𝑙 = lower limit of the measurement range of CDC
∆𝑟𝑚𝑎𝑥 = maximum difference between repeated measurements

as explained in section 2.2.2. The test results presented in Table 2.3 are conducted for

two different time intervals, 𝑁𝑇𝐶 = 100 ms and 1s, respectively. The results confirm two

facts: (a) as 𝑁𝑇𝐶 is increased, the number of transitions 𝑁𝑥 is increased, improving the

resolution irrespective of compensation. As can be seen from Table 2.3, when the

duration is increased from 𝑁𝑇𝐶 to 10𝑁𝑇𝐶 , SNR is increased by 17 dB and ENOB by

almost 3 bits. However, higher 𝑁, results in higher power consumption. This approach

is useful for measuring slowly varying measurands at a higher resolution. Hence the

tradeoff must be made accordingly. (b) Compared to the results from the uncompensated
42
circuit, the SNR was about 10 dB higher for the compensated circuit, irrespective of the

duration being 𝑁𝑇𝐶 or 10𝑁𝑇𝐶 . This shows the effectiveness of the compensation scheme

in improving the resolution.

As a complete conversion involves both mode-𝐶𝑥 and mode-𝐶𝑅 , the total time taken for

one measurement is 2𝑁𝑇𝐶 . For the prototype developed, the shortest 𝑁𝑇𝐶 tested is

100 ms, leading to an overall measurement time of 200 ms. Thus, a change in 𝐶𝑥 will be

reflected at the output after a duration of 2𝑁𝑇𝐶 . For applications that require

2𝑁𝑇𝐶 < 200 ms, the clock frequency can be increased.

Table 2.3 Effectiveness of Compensation on the SC-CDC

Uncompensated Compensated
Parameters
𝑁 10𝑁 𝑁 10𝑁
SNR 49.02 66.31 59.41 76.15
ENOB 7.85 10.72 9.58 12.36
Note: 𝑁 = 8000.

2.4.3 Testing the Effect of Interference

To examine the impact of interference on the performance of the proposed SC-CDC, a

sinusoidal interference signal 𝑣𝑖𝑛𝑡𝑟 was introduced at the critical point, node m, of the

circuit in Fig. 2.1, via a coupling capacitance 𝐶𝐶 . In the case of a typical power line

interference signal, the RMS value of the 𝑣𝑖𝑛𝑡𝑟 sinewave is 230 V at 50 Hz in frequency.

The typical value of the 𝐶𝐶 is in the range of hundreds of fF [55]. The associated current

𝐼𝑖𝑛𝑡𝑟 that is injected in node m is about 14.5 nA (for 𝐶𝐶 = 200 fF). To replicate such an

interference injection to the prototype CDC, a 50 Hz, 10 V peak-to-peak sinusoidal

signal was introduced into the node m via 𝐶𝐶 = 13.1 pF. For this experiment, 𝑁𝑇𝐶 was

43
set as 100 ms and 𝑁𝑥 recorded at 𝐶𝑥 = 20 pF. The change in the output was negligible

as it was less than 1% of the charging current 𝐼𝑐ℎ .

Table 2.4 Testing the Effect of Interference on the SC-CDC

𝐼𝑖𝑛𝑡𝑟 % Error due to 𝑣𝑖𝑛𝑡𝑟 for different 𝑓𝑖𝑛𝑡𝑟 [Hz]

%( ) Ɛ
𝐼𝑐ℎ 30 50 70 90
4 0.036 0.34 0.10 0.06 0.06
6 0.054 0.50 0.53 0.38 0.40
8 0.072 0.61 0.55 0.53 0.46
10 0.090 0.71 0.67 0.74 0.67
12 0.108 0.73 0.92 0.78 0.71

Further, 𝑁𝑥 was recorded, at 𝐶𝑥 = 20 pF, for different percentages of (𝐼𝑖𝑛𝑡𝑟 /𝐼𝑐ℎ ) as

presented in Table 2.4. During this experiment, 𝐼𝑐ℎ (= 4 µA) was kept constant. To

achieve different 𝐼𝑖𝑛𝑡𝑟 , at 50 Hz, 𝐶𝐶 was varied from a very low value to 455 pF. Later,

the experiment was repeated for several other interference frequencies, as given in

Table 2.4, keeping (𝐼𝑖𝑛𝑡𝑟 /𝐼𝑐ℎ ) a constant by appropriately setting the value of 𝐶𝐶 . The

error was negligible when (𝐼𝑖𝑛𝑡𝑟 /𝐼𝑐ℎ )100  2%. For higher values of 𝐼𝑖𝑛𝑡𝑟 (4% to 12%

of the 𝐼𝑐ℎ ) a small increase in error is noted. The maximum error observed was less than

0.75% for (𝐼𝑖𝑛𝑡𝑟 /𝐼𝑐ℎ )100 = 10%. For 50 Hz interference alone, higher values of 𝐼𝑖𝑛𝑡𝑟

were injected (up to 20% of 𝐼𝑐ℎ ) in steps, by setting the value of 𝐶𝐶 appropriately. The

associated error trend continued as in the lower range in Table 2.4 and the maximum

error noted was less than 2%. In Table 2.4, the value of Ɛ is also given along with the

%𝐼𝑖𝑛𝑡𝑟 . As expected, the error is a function of Ɛ. Thus, depending on the expected

interference current and accuracy required, the designer can choose Ɛ and, hence, the

circuit parameters to meet the requirements.

44
To further study the effectiveness of the proposed CDC regarding the interference

insensitivity, triangular and square interference signals of 50 Hz frequency have been

applied instead of the sinusoidal interference. The amplitude of the triangular wave was

set to 1.45 𝑉𝑝𝑝 via 𝐶𝐶 = 100 pF into node m, such that the interference current is 14.5 nA.

This is the same value of current used in the above mentioned interference tests to

emulate typical power line interference coupled through the human body. Further, the

amplitude of the triangular wave was increased from 2𝑉𝑝𝑝 to 10𝑉𝑝𝑝 , keeping the same

𝐶𝐶 , injecting a maximum current of 100 nA. The corresponding change in 𝑁𝑥 was 0.06%.

Similarly, a square wave with amplitude varied from 𝑉𝑝𝑝 to 10𝑉𝑝𝑝 , was injected via the

𝐶𝐶 . In this case, the corresponding change in 𝑁𝑥 was 0.04% to 1.2%. The results adhere
𝑛𝑡𝑜𝑡
to the trend in Table 2.4. Thus, as long as the condition 𝜀 2 < , discussed in
2𝑁

section 2.2.5, holds good, the proposed CDC exhibits a high degree of interference

rejection. These results show the effectiveness and predictability of the performance of

the proposed CDC.

2.5 DISCUSSION

The proposed system comprising of a switched capacitor CDC and a unique

compensation network excited by precision dc voltage source, is simple in design, unlike

[56] which employs a complex demodulator, and [57], [58] that use an ac source and

two ac driving signals, respectively, and [59], [60] that use Finite State Machine and

classification algorithm, respectively. The prototype developed to test the functionality

and performance uses commercially available ICs. Hence the power consumption of the

prototype CDC is not optimal. The opamp, comparator, precision dc voltage source,

switches and the CLU together draw 60 mW. In this, the comparator consumes the major

portion ( 25 mW). This can be reduced by using low-power comparators such as

45
LP339, from Texas Instruments Inc. In [61] the resolution of the system is considerably

affected by the inherent noise and characteristics of the low pass filter and in [59], [62]-

[64] the output is in the analog domain. The proposed scheme provides digital output

with ENOB of 11.13 bits and SNR of 68.77 dB.

Though there are other CDCs employing either an ADC or relaxation oscillator or both,

most of them have not proven to be interference insensitive. For instance, in [65] a

successive approximation register (SAR)-based architecture is used to realize the

capacitance to digital conversion. This is an energy-efficient design. However, unlike

the proposed CDC, it is not intended for interference insensitivity. The SAR paradigm

does not by design have the capability of interference immunity. The circuit in [66] used

an active bridge to sense the value of the capacitance. The circuit has multiple nodes that

can be sensitive to interference signals and hence special care (shielding) will be required

if the sensor or the measurement circuit is exposed to interference. Detailed tests will be

required to quantify the effect. In [67], the circuit employs a dual-slope integrator which

can exhibit interference insensitivity. But, since this circuit is not designed to fix the de-

integration time as an integral multiple of the interference time period, the scale of

interference rejection may be limited [31].

The interference rejection displayed by the proposed scheme is realized by virtue of its

design. It is uncomplicated unlike the systems in [29] and [47]. Also, unlike the circuits

in [31], [32], and [48], the proffered system has control over the de-integration time and

is suitable for fabrication as an IC. Such IC realization can significantly reduce the power

consumption and facilitate ease of integration with other sensor systems.

46
2.6 CONCLUSION

A new Switched Capacitor (SC) based Capacitance-to-Digital Converter (CDC), with

high insensitivity to interference, formed by combining an SC relaxation oscillator and

an integrating-type ADC, is presented in this chapter. In this design, the sensor

capacitance is determined using the number of transitions in the output of the SC

relaxation oscillator. It provides accurate results even in the presence of interference. It

is inherently insensitive to interference for a wide range of values of coupling

capacitance, by virtue of its conversion mechanism. It shows a high SNR of 68.77 dB,

resolution of 11.13 bits and repeatability error of 0.11%. The maximum non-linearity

exhibited by the proposed prototype is 0.4%. Since it uses a dc reference voltage as an

excitation source, and not a complex ac excitation circuit, this scheme ensures higher

accuracy compared to others. The proffered SC-CDC is entirely realized using switched

capacitor circuits and hence is easy to fabricate on an IC. It is well suited to achieve

insensitivity to the power line-interference that is a serious issue while interfacing

sensors that have unshielded or partially shielded sensing electrodes, such as capacitive

touch sensors, that are widely used in industrial and consumer electronic applications.

The capacitance measurement scheme presented in this chapter is very useful in rejecting

the interference but suitable only for single-element capacitive sensors. Another very

important configuration of capacitive sensors is the differential capacitive sensor (DCS).

Also, the conversion time of the scheme presented in this chapter is large due to the

several cycles required to achieve sufficient resolution. A capacitance measurement

scheme that is compatible with both single-element as well as differential capacitive

sensors and provides a linear digital output at a faster update rate is presented in the next

chapter.

47