Experiment Number: 01

Experiment Name: Design 2- input NAND gate using Vivado Xilinx Design Suite.

Objective:
The objective of this experiment is to design a 2-input NAND gate using the Vivado Xilinx Design
Suite, and to verify the functionality of the design through simulation and testing.

Theory:
The NAND gate with two inputs is a digital logic gate that performs a NOT-AND operation on
two input signals. The NAND gate is a combination of an AND gate and a NOT gate, with the
AND gate's output inverted. A 2-input NAND gate is represented by a standard AND gate with a
small circle on the output indicating inversion. The inputs are marked A and B, and the output is
marked Y. The truth table for a two-input NAND gate displays the output for all possible input
combinations. When both A and B inputs are high (1), the output Y is low (0). When either input
A or B is zero, the output Y is positive (1).The 2-input NAND gate functions as a NOT-AND gate,
which means it will output a high signal (1) if both inputs are not high (0) and a low signal (0) if
both inputs are high (1). It can also be used as an AND-NOT gate, producing a high signal (1)
when one or both inputs are low (0) and a low signal (0) when both inputs are high (1).

Figure-1: Symbol of 2- input NAND gate.

Truth Table of 2-input NAND gate:

A(input) B(input) Y(output)

0 0 1
0 1 1
1 0 1
1 1 0

Required Apparatus:

1. Vivado Xilinx Design Suite HLx editions.

2. Personal Computer.
VHDL Code for 2-input NAND gate:

entity nand_gate10 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end nand_gate10;

architecture Behavioral of nand_gate10 is

begin
Y <= not (A and B);

end Behavioral;

OUTPUT:

Figure-2: Schematic diagram of 2- input NAND gate.

 Figure-3: Output waveform of 2- input NAND gate.

Result and Discussion:

In this experiment, we came to know about implementing NAND gate using VHDL language in
Vivado Xilinx design suite. Two input NAND gate is introduced here. After initiating proper
logical steps, output schematic and waveform is accomplished. Force clock pulses are given to
observe real time value of NAND gate operation. The waveform was generating accurate value of
input and output bits. The output is achieved by implementation, synthesis and simulation after
providing necessary instructions.

Precaution:

1. The VHDL code was correctly written.

2. The code was executed after it had completed its checks.
3. The output was thoroughly examined.