Republic of the Philippines

BATANGAS STATE UNIVERSITY

BatStateU Alangilan
Alangilan, Batangas City
College of Engineering, Architecture and Fine Arts
https://batstate-u.edu.ph/, Tel. No. (043) 425-0139 loc. 118/2121

Bal-ot, Chester Dave A.

EE-3108
Laboratory 3

Designing a Combinational Circuits

Design Problems 1

1. Design a 6-bit ripple carry adder using only 3-bit adder blocks like the one in Figure 3.4?
(Do not use individual full adders as building blocks.) Draw the schematic.

Fig. 3.4: 3-bit adder block

6-BIT RIPPLE CARRY ADDER:

 Republic of the Philippines
BATANGAS STATE UNIVERSITY
BatStateU Alangilan
Alangilan, Batangas City
College of Engineering, Architecture and Fine Arts
https://batstate-u.edu.ph/, Tel. No. (043) 425-0139 loc. 118/2121

Truth Table:

A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 CIN COUT S0 S1 S2 S3 S4 S5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1
0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2. Create a 4-bit ripple carry adder using only 3-bit adders? Hint: use one 3-bit adder for
the least significant 3 bits and use the most significant bit from the other 3-bit adder for the
fourth bit. (Again, do not use individual full adders as building blocks.) Draw the schematic.

4-BIT RIPPLE CARRY ADDER:

3. Using your design for the full adder, determine the worst-case propagation delay from
the inputs to the carry-out output bit. Assume each gate has the same delay, 1 gate delay.
 Republic of the Philippines
BATANGAS STATE UNIVERSITY
BatStateU Alangilan
Alangilan, Batangas City
College of Engineering, Architecture and Fine Arts
https://batstate-u.edu.ph/, Tel. No. (043) 425-0139 loc. 118/2121

Propagation delay is equal top:

Td = 1/2f

Propagation Delay from inputs to carry out using 1 gate delay:

Td = 1/2f

= ½(1000Hz)

=0.5 ms or 0.5x10-3s

4. Using your designs for the full adder and the 3-bit ripple carry adder (Design 3),
determine the worst-case propagation delay from the least significant input bit (of either input
number A or B) to the carry-out output bit. Again, assume each gate has the same delay, 1 gate
delay.
 Republic of the Philippines
BATANGAS STATE UNIVERSITY
BatStateU Alangilan
Alangilan, Batangas City
College of Engineering, Architecture and Fine Arts
https://batstate-u.edu.ph/, Tel. No. (043) 425-0139 loc. 118/2121

Propagation Delay on 1 input of the Full Adder:

Td = 1/2f

= ½(1000Hz)

=0.5 ms or 0.5x10-3s

Propagation Delay from inputs to carry out:

Td = 3(0.5x10-3s)

= 1.5x10-3s

= 1.5ms