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  • Programa VHDL

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    PrimoCardona
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    This document describes an 8-bit to 4-bit encoder. It defines an entity called ENCODER8 with an 8-bit input port A and 4-bit output port Y. The architecture uses a case statement to map each of the 8 possible input values of A to a unique 4-bit output on Y, effectively encoding the 8-bit input into a 4-bit representation. It then notes that the design will be simulated using Aldec Active HDL software.

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    This document describes an 8-bit to 4-bit encoder. It defines an entity called ENCODER8 with an 8-bit input port A and 4-bit output port Y. The architecture uses a case statement to map each of the 8 possible input values of A to a unique 4-bit output on Y, effectively encoding the 8-bit input into a 4-bit representation. It then notes that the design will be simulated using Aldec Active HDL software.

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    © All Rights Reserved
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    8 views1 page

    Programa VHDL

    Uploaded by

    PrimoCardona
    This document describes an 8-bit to 4-bit encoder. It defines an entity called ENCODER8 with an 8-bit input port A and 4-bit output port Y. The architecture uses a case statement to map each of the 8 possible input values of A to a unique 4-bit output on Y, effectively encoding the 8-bit input into a 4-bit representation. It then notes that the design will be simulated using Aldec Active HDL software.

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    © All Rights Reserved
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    of 1

    Programa 1.

    -
    Library IEEE;
    Use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;
    entity ENCODER8 is
    port (A: in std_logic_vector (7 downto 0);
    Y: out std_logic_vector (3 downto 0));
    end entity ENCODER8;
    architecture ARCH of ENCODER8 is
    begin
    process (A)
    begin
    case A is when "00000001" => Y <= "0000";
    when "00000010" => Y <= "0001";
    when "00000100" => Y <= "0010";
    when "00001000" => Y <= "0011";
    when "00010000" => Y <= "0100";
    when "00100000" => Y <= "0101";
    when "01000000" => Y <= "0110";
    when "10000000" => Y <= "0111";
    when others => Y <= "1XXX";
    end case;
    end process;
    end architecture ARCH;

    SIMULACIÓN EN ´´ALDEC ACTIVE´´

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