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Circuit Idea

20211104
Programmable Synchronous Rectifier for Zero Voltage Switching
Page 1 of 2

In lieu of a primary-side coupled active clamp, the


Summary of the Idea
secondary-side synchronous output rectifier S2 may
The synchronous output rectifier (S2) of a power
be used to discharge the parasitic capacitance CP to
converter may be used to facilitate zero voltage
achieve ZVS. The duration of time which the
switching (ZVS) of the main power switch (S1) of the
synchronous output rectifier S2 is turned ON to
power converter to reduce switching losses. The
facilitate ZVS, e.g. the ZVS on-time TZVS_ON, and the
duration of time which the synchronous output
duration of time between turning OFF the
rectifier S2 is turned ON to facilitate ZVS, e.g. TZVS_ON,
synchronous output rectifier S2 and turning ON the
along with the delay time between turning OFF the
power switch S1, e.g. ZVS delay time TZVS_DLY, are
synchronous output rectifier S2 and turning ON the
programmable. Programming may be accomplished
power switch S1, e.g. TZVS_DLY, may be programmable.
using the Inter-Integrated Circuit (I2C)
communication protocol.

Description
Switching losses may result from having a non-zero Figure 1 illustrates a power converter with a
voltage (VDS) across the power switch S1 at the secondary controller which controls the turn ON and
moment which the power switch S1 is turned ON due turn OFF of the synchronous output rectifier S2 and
to the associated parasitic capacitance CP of the allows programming of the ZVS on-time TZVS_ON and
power switch S1. A primary active clamp has been ZVS delay time TZVS_DLY. Figure 2 illustrates example
previously used to discharge the parasitic capacitance waveforms of the voltage VDS across power switch S1,
CP to reduce the voltage (VDS) across the power request signal REQ, secondary drive signal SR, and
switch S1 to zero. primary drive signal DR.

NP:NS IO

T1 +
CLAMP - UO
VP CO VOUT LOAD
CIRCUIT
+ S2 -
+
VIN
-
CP
S1 +
FWD SR
VDS
-

DR REQ REQUEST
SR CONTROL
CIRCUIT

PRIMARY FL
TZVS_ON
CONTROLLER PRGM
REGISTER
TZVS_DLY

SECONDARY CONTROLLER

Figure 1. Programmable zero voltage switching (ZVS) using the synchronous output rectifier S2, the ZVS on-time TZVS_ON and the ZVS delay time
TZVS_DLY may be programmed through a program terminal PRGM.

World Headquarters 5245 Hellyer Avenue, San Jose, CA 95138, USA, Main: +1-408-414-9200 REV 1, JUNE 2022
Customer Service Phone: +1-408-414-9665, Fax: +1-408-414-9765, Email: info@power.com 20211104
On the Web www.power.com
These ideas are presented for informational purposes only and Power Integrations makes no warranty herein expressed or implied.
Circuit Idea
20211104
Programmable Synchronous Rectifier for Zero Voltage Switching
Page 2 of 2

At time t4 of Figure 2, the request circuit asserts the the ZVS delay time TZVS_DLY has elapsed, the power
request signal REQ to turn ON the power switch S1 if switch S1 is turned on at time t6. As shown in Figure
the output voltage VO falls below a regulation 1, a communication signal FL is sent to the primary
reference for the output of the power converter. If controller from the secondary controller to turn ON
the power converter is also in discontinuous the power switch S1.
conduction mode (DCM), the synchronous output
rectifier S2 is turned ON for the duration of the ZVS The durations required for the ZVS on-time TZVS_ON
on-time TZVS_ON prior to the turn ON of the power and ZVS delay time TZVS_DLY to facilitate zero voltage
switch S1 as shown by the high secondary drive switching may vary with the input voltage VIN, output
signal SR. Between time t4 and time t5, the voltage VOUT and the load. Usually the ZVS on-time
magnetizing inductance of the transformer T1 is TZVS_ON and ZVS delay time TZVS_DLY are either fixed
charged in the negative direction at a rate determined durations or only a few trim options to cover the
by the reflected output voltage on the primary of operating range of the power converter. These
transformer T1. During this time, the drain voltage limited options can limit the potential of ZVS
VDS is substantially the sum of the input voltage VIN operation across line and load conditions and affect
and the voltage on the primary winding VP. the efficiency of the overall power converter.

Once the ZVS on-time TZVS_ON has elapsed, the ZVS With secondary-side ZVS utilizing the synchronous
delay time TZVS_DLY begins, the parasitic capacitance output rectifier S2, the ZVS on-time TZVS_ON and ZVS
CP is discharged and the drain voltage VDS decreases. delay time TZVS_DLY may be programmed though the
The duration of the ZVS delay time TZVS_DLY is I2C communication protocol. Potentially increasing
programmed such that the drain voltage VDS reaches efficiency for given line and load conditions.
zero prior to the power switch S1 turning ON. Once

S1 ON S1 OFF S1 ON S1 OFF

VIN+VP

VDS

0
TIME
REQ
0
S2 ON TIME
S2 ON
SR
0
TIME
DR

0
TIME
t1 t2 t3 t4 t5 t6

TZVS_ON TZVS_DLY

Figure 2. Timing diagram of various waveforms of Figure 1

World Headquarters 5245 Hellyer Avenue, San Jose, CA 95138, USA, Main: +1-408-414-9200 REV 1, JUNE 2022
Customer Service Phone: +1-408-414-9665, Fax: +1-408-414-9765, Email: info@power.com 20211104
On the Web www.power.com
These ideas are presented for informational purposes only and Power Integrations makes no warranty herein expressed or implied.

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