Advanced Digital Circuit Design

Task:
Continuous assignment with delay allows us to specify gate delays (propagation delays) in Verilog. By including delays, we can
model the real-world behavior of logic gates more accurately. In this lab, we implemented a logic equation (AC' + BC) using
continuous assignment with a gate delay of 5 nanoseconds for each logic gate. We also created a testbench to simulate the behavior
of the logic equation.

Answer:
The given code consists of two Verilog modules: `Lab6` and ‘tb_Lab6’. Here's how they work…

1. `Lab6` module:
In this code, we defined a module named Lab6 with input ports A, B, C, and an output port Z. Inside the module, we instantiated
several gates (g1, g2, g3, g4, g5) with a delay of 5 nanoseconds using the #5 notation. These gates perform the necessary
computations to implement the logic equation (AC' + BC). Gates 1-4 are responsible for the first portion of the lab while gate 5 is
responsible for the glitch fix of ‘ + AB ‘ to the original logic equation.

2. `tb_Lab6` module:
In the testbench module, we instantiated the Lab6 module and provided inputs A, B, C, and observed the output Z. Inside the initial
block, we set the inputs to specific values and added delay using # notation. This allowed us to simulate the behavior of the logic
equation (AC' + BC) under different input conditions. The input conditions we were testing for this instance were 110 and 111.
Pin Assignments:
Btn Input PIN_B8
D[3] Input PIN_C12
D[2] Input PIN_D12
D[1] Input PIN_C11
D[0] Input PIN_C10
clk Input PIN_P11
hex0[0] Output PIN_C14
hex0[1] Output PIN_E15
hex0[2] Output PIN_C15
hex0[3] Output PIN_C16
hex0[4] Output PIN_E16
hex0[5] Output PIN_D17
hex0[6] Output PIN_C17
hex1[0] Output PIN_C18
hex1[1] Output PIN_D18
hex1[2] Output PIN_E18
hex1[3] Output PIN_B16
hex1[4] Output PIN_A17
hex1[5] Output PIN_A18
hex1[6] Output PIN_B17
hex2[0] Output PIN_B20
hex2[1] Output PIN_A20
hex2[2] Output PIN_B19
hex2[3] Output PIN_A21
hex2[4] Output PIN_B21
hex2[5] Output PIN_C22
hex2[6] Output PIN_B22
hex3[0] Output PIN_F21
hex3[1] Output PIN_E22
hex3[2] Output PIN_E21
hex3[3] Output PIN_C19
hex3[4] Output PIN_C20
hex3[5] Output PIN_D19
hex3[6] Output PIN_E17
hex4[0] Output PIN_F18
hex4[1] Output PIN_E20
hex4[2] Output PIN_E19
hex4[3] Output PIN_J18
hex4[4] Output PIN_H19
hex4[5] Output PIN_F19
hex4[6] Output PIN_F20
hex5[0] Output PIN_J20
hex5[1] Output PIN_K20
hex5[2] Output PIN_L18
hex5[3] Output PIN_N18
hex5[4] Output PIN_M20
hex5[5] Output PIN_N19
hex5[6] Output PIN_N20
Results:

FIGURE 1.1: ‘Lab7’ Verilog Code

FIGURE 1.2: ‘DisplayHex’ Verilog Code

Self-Assessment:

My code worked, and I demonstrated and explained my result ✔

I simulated the testbench using ModelSim and obtained the waveform and results. The waveform displayed the transitions of A, B,
C, and Z over time. The simulation results showed the following values: Initial values: A=1, B=1, C=1, Z=X (undefined) After 40
nanoseconds: A=1, B=1, C=0, Z=1 After another 40 nanoseconds: A=1, B=1, C=1, Z=1. From the simulation results, we observed
that the output Z correctly followed the logic equation (AC' + BC). Initially, when inputs A, B, and C were 1, the output Z was
undefined (X). However, after 40 nanoseconds, when C was changed to 0 while A and B remained 1, the output Z correctly became
1. After another 40 nanoseconds, when C was changed back to 1, the output Z remained 1. The continuous assignment with delay
allowed us to model the propagation delays of the logic gates accurately. By specifying a delay of 5 nanoseconds for each gate, we
ensured that the output Z stabilized correctly after input transitions. Overall, the simulation results confirm that the implementation
of the logic equation and the testbench were successful, and the continuous assignment with delay worked as expected. Conclusion:
In this lab, we learned about continuous assignment with delay in Verilog and implemented a logic equation (AC' + BC) using this
concept. I also created a testbench to verify the correctness of our design. It was wrong, big ole glitch. So I added AB to the logic
equation, compiled, then simulated and it was good!