Priya Document - Organized

A Project Report
On
STRATEGIES FOR ACCELERATING CLOCK- DELAYED DUAL

KEEPER USING DOMINO LOGIC STYLE
A Project report submitted to
SREENIVASA INSTITUTE OF TECHNOLOGY AND MANAGEMENT STUDIES, CHITTOOR
In partial fulfilment of the requirements for the award of the
Degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
By
K. POOJITHA 19751A0466
K. MUKUNDHA PRIYA 19751A0465
M.SAI PAVANI 19751A0497
L.DIVYA 19751A0487
Under the Guidance of
Dr.S. Vijaya Kumar

PROFESSOR,DEPARTMENT OF ECE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SREENIVASA INSTITUTE OF TECHNOLOGY AND MANAGEMENT
STUDIES
(Autonomous)
Affiliated to J.N.T.U.A, Anantapuramu & NBA Accredited CHITTOOR-517127
i
(2019-2023)
ii
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SREENIVASA INSTITUTE OF TECHNOLOGY AND MANAGEMENT STUDIES
(Autonomous)
Affiliated to J.N.T.U.A, Anantapuramu& NBA
Accredited CHITTOOR-517 127
Certificate
This is to certify that the project report entitled “STRATEGIES FOR ACCELERATING
CLOCK- DELAYED DUAL KEEPER USING DOMINO LOGIC STYLE”. That is being
submitted by, Ms. K. POOJITHA (19751A0466), Ms. K. MUKUNDHA PRIYA
(19751A0465), Ms. M. SAI PAVANI (19751A0497), Ms. L. DIVYA (19751A0487), in
partial fulfilment for the award of the Degree of Bachelor of Technology in
ELECTRONICS AND COMMUNICATION ENGINEERING to the Jawaharlal Nehru
Technological University Anantapuramu, Anantapuramu is a record of Bonafede work
carried out under my guidance and supervision. The results embodied in this project report
have not been submitted to any other University or Institute for the award of any degree.
Dr.S. Vijaya Kumar Dr. K. GOPI, M.E., Ph.D.
Professor, ECE Dept Head of the Department

Internal Guide Dept. of ECE
Submitted for University Examination (Viva-Voce) held on
Internal Examiner External Examiner

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ACKNOWLEDGEMENT
The successful completion of this project work was made possible with the help and
guidance received from various quarters. We would like to take advantage of this opportunity
to express our sincere thanks and gratitude to all of them.
I would like to express my heartfelt gratitude to our Management, Chairperson

SRI. K. RANGANATHAM GARU for providing excellent institutional support to complete
this project.
I would like to express profound gratitude to our beloved principal

Dr.N. VENKATACHALAPATI, M. Tech, Ph. D GARU., and Prof. M. SARAVANAN,
M. Tech, Ph. D dean academics for giving us the opportunity to Embark upon this Course
and make use of the facilities available in college.
I pay our sincere note of felicitation to Dr. K. GOPI, M. Tech, Ph. D Professor &
Head, Department of the ECE for providing excellent departmental support as well as
motivation to all of us, which enhanced our thrust to complete the project.
I thank our project guide Dr. S. Vijaya Kumar Professor, ECE Dept for his valuable
guidance, support and offering necessary material and willingly giving us advice whenever
needed.
I would like to extend our gratitude to our Project Coordinator Mr.S. ASHMAD
Assistant Professor for his valuable support.
Finally, we thank all the teaching faculty and non-teaching staff of the Department of
Electronics and Communication Engineering for giving their advice and their help during our
project work as well as studies.
K. Poojitha 19751A0466
K. Mukundha Priya 19751A0465
M. Sai Pavani 19751A0497
L. Divya 19751A0487
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Course Outcomes for project work
On completion of project work we will be able to,

CO1. Demonstrate in-depth knowledge on the project topic.
CO2. Identify, analyze, and formulate complex problem chosen for project work to attain
substantiated conclusions.
CO3. Design solutions to the chosen project problem.
CO4. Undertake investigation of project problem to provide valid conclusions.
CO5. Use the appropriate techniques, resources, and modern engineering tools necessary for
project work.
CO6. Apply project results for sustainable development of the society.
CO7. Understand the impact of project results in the context of environmental
sustainability. CO8. Understand professional and ethical responsibilities while executing
the project work. CO9. Function effectively as individual and a member in the project team.
CO10. Develop communication skills, both oral and written for preparing and presenting project
report.
CO11. Demonstrate knowledge and understanding of cost and time analysis required for carrying
out the project.
CO12. Engage in lifelong learning to improve knowledge and competence in the chosen area of the
project.
CO – PO MAPPING
COs PO PO PO PO PO PO PO PO PO PO PO PO
\ 1 2 3 4 5 6 7 8 9 10 11 12
POs
CO1 √
CO2 √
CO3 √
CO4 √
CO5 √
CO6 √
CO7 √
CO8 √
CO9 √
CO10 √
CO11 √
CO12 √
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Evaluation Rubrics for Project work
Rubric (CO) Excellent (Wt = 3) Good (Wt = 2) Fair (Wt = 1)
Select a latest topic through Select a topic through Select a topic through
Selection of Topic (CO1) complete knowledge of facts partialknowledge of facts improper knowledge of
and concepts. and concepts. factsand concepts.
Thorough comprehension Reasonable Improper comprehension

Analysis and Synthesis (CO2)
through analysis/ synthesis. comprehensionthrough through analysis/
analysis/ synthesis. synthesis.
Thorough comprehension about Reasonable comprehension Improper comprehension
Problem Solving (CO3) what is proposed in the literature about what is proposed in about what is proposed
papers. theliterature papers. in theliterature.
Extensive literature survey with Considerable literature Incomplete literature survey

Literature Survey (CO4)
standard references. surveywith standard with substandard references.
references.
Clearly identified and has
Usage of Techniques & Identified and has sufficient Identified and has
complete knowledge of
Tools (CO5) knowledge of techniques & inadequateknowledge of
techniques & tools used in
tools used in the project techniques & tools used in
the project work.
work. project work.
Project work impact on Conclusion of project work has Conclusion of project work Conclusion of project
Society (CO6) strong impact on society. hasconsiderable impact on workhas feeble impact on
society. society.
Conclusion of project Conclusion of project
Project work impact on Conclusion of project work has
work hasconsiderable workhas feeble impact on
Environment (CO7) strong impact on Environment.
impact on environment. environment.
Clearly understands ethical Moderate understanding Insufficient understanding

Ethical attitude (CO8)
and social practices. ofethical and social ofethical and social
practices. practices.
Did literature survey and Did literature survey and
Selected a topic as
Independent Learning (CO9) selected topic with a selected topic with
suggestedby the supervisor
little guidance considerableguidance
Presentation in logical sequence Presentation with key points, Presentation with

Oral Presentation (CO10) with key points, clear conclusion and good insufficientkey points and
conclusion and excellent language improper conclusion
language
Status report with clear and Status report with logical
Report Writing (CO10) Status report not
logical sequence of sequence of chapters
properlyorganized
chapters using excellent usingunderstandable
language language
Comprehensive time and cost Moderate time and Reasonable time and
Time and Cost Analysis (CO11)
analysis costanalysis costanalysis
Highly enthusiastic towards Interested in Inadequate interest

Continuous learning (CO12)
continuous learning continuouslearning incontinuous
learning
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ABSTRACT
Domino circuits are known for high-speed operation, robustness, and lower power
consumption. This work focuses on enhancing the speed of Clock-Delayed Dual Keeper
Domino (CDDK) circuit. The speed is enhanced by delaying the enabling of keeper circuit,
controlling the swing variation of keeper circuit, sizing of keeper transistors and using an
additional conditional discharge path. The robustness is enhanced by upsizing the stacked
dual keeper transistors without degrading the speed. The major drawback in the existing
system is the feedback loop gain and process parameter variations contribute to considerable
amount of delay variability. In this project propose transistor sizing along with sleep or
leakage control transistors by improved power consumption with less delay variability. The
simulation of enhancement techniques has been performed using DSCH and MICROWIND
Tools for various nm technology libraries. The simulation results are verified with the
conventional domino logic circuit for various parameters like delay, area, and power
dissipation.
Keywords:
Domino logic circuit; high speed techniques; noise gain margin; robustness;
process variation tolerance
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LIST OF CONTENTS
CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY 60-62
CHAPTER PAGE
NO TITLE NO
LIST OF FIGURES ix
LIST OF TABLES x
1 INTRODUCTION 11
1.1 VLSI 14-16
1.2 VLSI DESIGNS CLASSIFICATION 16
1.3 VLSI DESIGN STYLES 17-20
2 LITERATURE SURVEY 21-24
3 SCOPE OF THE PROJECT AND PROPOSED APROACH 25-27
3.1 SCOPE OF THE PROJECT 26
3.2 PROPSOED APPROCH 26-27
4 SOFTWARE AND HARDWARE DESCRIPTION 28-39
4.1 REQUIREMENTS 29
4.2 TOOL (DSCH & EXPORT MICRO WIND) 29-34
4.3 SIMULATION ENVIRONMENT 34
4.3.1 DSCH (DIGITAL SCHEMATIC) 35-36
4.3.2 MICROWIND 36-39
5 IMPLEMENTATION 40-48
5.1 INTRODUCTION 41-44
5.2 CLOCK-DELAYED DUAL KEEPER (CDDK) DOMINO 44-45
CIRCUIT
5.3 ADDITIONAL CONDITIONAL DISCHARGE PATH 46
5.4 PROPOSED DOMINO (WITH SLEEP TRANSISTOR) 47-48
6 SIMULATION RESULTS 49-68
6.1 CONVENTIONAL DOMINO LOGIC 50-51
6.2 HIGH SPEED DOMINO LOGIC 52-53
6.3 GROUNDED PMOS KEEPER 54-55
6.4 LEAKAGE CURRENT REPLICA KEEPER DOMINO LOGIC 56-57
6.5 FOOT DRIVER STACKED TRANSISOR DOMINO LOGIC 67-
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6.6
6.7 CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY 62-65
WITH ADDITIONAL DISCHARGE PATH
6.8 PROPOSED DOMINO LOGIC 65-68
7 CONCLUSION AND FUTURE SCOPE 69-70
REFERENCES 71-72
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LIST OF FIGURES
Figure No Page No
Figure Caption
1.1 Moore’s Law 13

4.1 N-Channel and P-Channel 30
4.2 The Transmission Gate. 31
4.3 Logics of Inverter. 31
4.4 Logic Symbol of the NAND gate. 33
4.5 CMOS Inverter Circuits. 33
4.6 CMOS Inverter Simulation 34
4.7 CMOS Inverter Wave forms 34
4.8 Symbol of NMOS and PMOS. 35
4.9 Creating the N-channel MOS transistor. 37
4.10 N-Channel MOS characteristics. 37
4.11 Selecting the PMOS device. 38
5(a) Depict the high-speed domino (HSD) 42
5(b) Leakage current replica keeper domino logic 42
5(c) Grounded PMOS keeper 43
5(d) Foot-driven stacked transistor domino logic 43
5.2 Clock-delayed domino keeper circuit topology 45
5.3 CDDK domino circuit with additional conditional discharge path 46
5.4 Proposed Domino (with sleep transistor) 47
x
LIST OF TABLES
Table Table title Page

No. No.
4.1 Logic Levels. 30

4.2 Basic Gate 32
6.1 Comparison For Conventional and Proposed Circuit 68
x
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CHAPTER-1
INTRODUCTION
STRATEGIES FOR ACCELERATING CLOCK- DELAYED DUAL KEEPER USING DOMINO LOGIC STYLE
INTRODUCTION
Complementary Metal Oxide Semiconductor for wide variety of applications in

VLSI field became the logic style of choice for the design of digital semiconductor
domain because of its low power dissipation and ease of design with increased
robustness [1-6]. This became the major advantage of CMOS logic over the other
available manufacturing processes then, which suffered from flow of leakage currents
or constant dissipation of bias currents. The rapid development of VLSI technology
made a remarkable shift in the fabrication industry with its emerging qualities like high
speed, low power, increased robustness, and low area overhead. Scaling brought
impeccable change in the recent trends. The evolution of various logic families like
pseudo NMOS, DCVSL, PTL, and DPTL changed the ongoing market trend in
manufacturing field. Then speed and overhead area became the primary parameters of
choice for fabrication industry that led to invention of clocked logic styles named as
Dynamic logic and Domino logic families. Power consumption, noise immunity, speed
of operation, area and cost are the predominant parameters that must be taken into
consideration before designing any kind of digital logic circuit technique. There may be
a requirement for the effective tradeoff between any two parameters depending on the
situation and application of design. Sometimes, the design techniques might not meet
all the mentioned requirements in their application, but still an optimization may be
followed to proceed further in research areas. Because of its high speed and low
overhead area domino logic became process of choice for many digital circuits. The
concerning issues are large power consumption and high sensitivity towards noise.
Hence, there is a need for designing new domino methodology or improving existing
techniques to meet the requirements by overcoming the drawbacks which led to ample
opportunities for diversified research in this field. Therefore, the outcome of research
must be able to handle the primary design parameters efficiently. Besides this, the
designed circuit must exhibit high degree of robustness towards noise.
History
The revolution in integration industry and IC design made an impeccable shift in

VLSI industry in the 1960s. According to Moore’s law, the number of transistors that
can be accommodated or integrated on a single die would exponentially grow with time
[1]. Figure 1.1 shows Moore’s prediction. It is observed that the complexity of
integration
Department of ECE, SITAMS, CHITTOOR Page 12

doubles approximately every year. In the early 1970s, the microprocessor has begun to
grow up in integration complexity and high performance.
Fig.1.1 Moore’s Law
Domino logic circuits are widely in use due to their reduced transistor count, high-
speed performance and reduced logical effort (Ding & Mazumder, 2004). Realization
of wide fan in gates using domino logic circuit style is normally preferred as in the
Pull-Up Network (PUN); they evade stacking of transistors and are extensively used in
design of Static Random Access Memory (SRAM) pre-decoders, tag comparators and
programmable encoders (Asyaei & Ebrahimi, 2018; Naserian, Kafi-Kangi, Maymandi-
Nejad, & Moradi, 2016; Peiravi & Asyaei, 2012a). The domino logic circuit design
with reduced transistor count and the evaluation being performed only by N-type Metal
Oxide Semiconductor (NMOS) transistors makes it a preferable circuit style compared
to static Complementary Metal Oxide Semiconductor (CMOS) circuit in terms of chip
area and speed performance. However, it offers low noise gain margin due to leakage
current and charge sharing which occur in the internal nodes. In addition, the dynamic
power consumption is increased because of redundant switching at output node for
every precharge operation, even for consecutive identical inputs.
Domino logic circuits have been making a profound impact in addressing the
requirements of high-speed and low-power consumption applications, such as the read-
out paths of register files, tag comparators, SRAM pre-decoder gate and programmable

encoders, and multiport memories [1]. The realization of wide fan in gates using
domino logic style is more remarkable, since it avoids stacking of transistors in the pull
up- network (PUN). However, due to multiple paths to ground, they are prone to
increased leakage current.
1.1 VLSI
The electronics industry has achieved a phenomenal growth over the last two
decades, mainly due to the rapid advances in integration technologies, large-scale
systems design - in short, due to the advent of VLSI. The number of applications of
integrated circuits in high-performance computing, telecommunications, and consumer
electronics has been rising steadily, and at a very fast pace. Typically, the required
computational power (or, in other words, the intelligence) of these applications is the
driving force for the fast development of this field. Gives an overview of the prominent
trends in information technologies over the next few decades. The current leading-edge
technologies (such as low bit-rate video and cellular communications) already provide
the end-users a certain amount of processing power and portability. This trend is
expected to continue, with very important implications on VLSI and systems design.
One of the most important characteristics of information services is their increasing
need for very high processing power and bandwidth (to handle real-time video, for
example). The other important characteristic is that the information services tend to
become more and more personalized (as opposed to collective services such as
broadcasting), which means that the devices must be more intelligent to answer
individual demands, and at the same time they must be portable to allow more
flexibility/mobility.
Very-large-scale integration (VLSI) is the process of creating integrated circuits

by combining thousands of transistor-based circuits into a single chip. VLSI began in
the 1970s when complex semiconductor and communication technologies were being
developed. The microprocessor is a VLSI device. The term is no longer as common as
it once was, as chips have increased in complexity into the hundreds of millions of
transistors. VLSI stands for "Very Large-Scale Integration". This is the field which
involves packing more and more logic devices into smaller and smaller areas. Thanks to
VLSI, circuits that would have taken board full of space can now be put into a small
space few millimeters across! This has opened a big opportunity to do things that were
not possible before. VLSI circuits are everywhere ... your computer, your car, your
brand new state-of-the-art digital camera, the cellphones, and what have you. All this
involves

a lot of expertise on many fronts within the same field, which we will look at in later
sections. VLSI has been around for a long time, there is nothing new about it ... but as a
side effect of advances in the world of computers, there has been a dramatic
proliferation of tools that can be used to design VLSI circuits. Alongside, obeying
Moore's law, the capability of an IC has increased exponentially over the years, in
terms of computation power, utilization of available area, yield. The combined effect of
these two advances is that people can now put diverse functionality into the IC's,
opening new frontiers. Examples are embedded systems, where intelligent devices are
put inside everyday objects, and ubiquitous computing where small computing devices
proliferate to such an extent that even the shoes you wear may do something useful like
monitoring your heartbeats.
Verilog was developed at a time when designers were looking for tools to
combine different levels of simulation. In the early 1980s, there were switch-level
simulators, gate-level simulators, functional simulators (often written ad-hoc in
software) and no simple means to combine them. Further, the more-widespread,
traditional programming languages themselves were/are essentially sequential and thus
"semantically challenged" when modeling the concurrency of digital circuitry.
Verilog was created by Phil Moore in 1983 at Gateway Design Automation and
the first simulator was written a year later. It borrowed much from the existing
languages of the time: the concurrency aspects may be seen in both Modula and
(earlier) Simulate; the syntax is deliberately close to that of C; and the methods for
combining different levels of abstraction owe much to Hilo.
In 1989, Gateway Design Automation (and rights to Verilog) was purchased by

Cadence who put Verilog in the public domain in the following year. This move did
much to promote the use of Verilog since other companies were able to develop
alternatives tools to those of Cadence which, in turn, allowed users to adopt Verilog
without dependency on a single (primarily workstation-tool) supplier. In 1992, work
began to create an IEEE standard (IEEE-1364) and in December 1995 the final draft
was approved. Thus, Verilog has become an n international standard - which will
further increase its commercial development and use.
At present, there is standards activity to extend Verilog beyond purely digital

circuits. This includes Verilog-MS for "mixed signal specification" and Verilog A for

"analog" design; the latter was recently approved (June 1996) by the board of Open
Verilog International and is now under consideration by the IEEE. In addition, work is
underway to automate the proof of "equivalence [between] behavioral and
synthesizable specifications" (see the Cambridge web site below) to which Verilog
readily lends itself.
While Verilog emerged from developments within private companies, its main rival
came from the American Department of Defense (DOD). In 1981, the DOD sponsored
a workshop on hardware description languages as part of its Very High-Speed
Integrated Circuits (VHSIC) program, and the outcome formed a specification for the
VHSIC hardware description language (VHDL) in 1983. There is, of course, the
question as to which language is better. And this, of course, is a hard question to answer
without causing excitement and rebuttals from the marketing departments of the less
preferred language. However, the following points featured in a recent debate in the
VHDL and Verilog news groups.
The main factor is the language syntax - since Verilog is based on C and VHDL is
based on ADA. Verilog is easier to learn since C is a far simpler language. It also
produces more compact code: easier both to write and to read. Furthermore, the large
number of engineers who already know C (compared to those who know ADA) makes
learning and training easier. VHDL is very strongly typed, and allows programmer to
define their own types although, in practice, the main types used are either the basic
types of the language itself, or those defined by the IEEE. The benefit is that type
checking is performed by the compiler which can reduce errors; the disadvantage is that
changing types must be done explicitly.
1.2 VLSI DESIGNS CLASSIFICATION
There are THREE CATEGORIES in today`s VLSI domain they are.
Analog:
Small transistor count precision circuits such as Amplifiers, Data converters, filters,
Phase locked loops, Sensors etc.
ASICS or Application Specific Integrated Circuits:
Progress in the fabrication of IC's has enabled us to create fast and powerful
circuits in smaller and smaller devices. This also means that we can pack a lot more of
functionality into the same area. The biggest application of this ability is found in the

design of ASIC's. These are IC's that are created for specific purposes - each device is
created to do a particular job and do it well. The most common application area for this
is DSP - signal filters, image compression, etc. To go to extremes, consider the fact that
the digital wristwatch normally consists of a single IC doing all the time-keeping jobs
as well as extra features like games, calendar, etc.
SOC or Systems on a chip:
These are highly complex mixed signal circuits (digital and analog all on the same
chip). A network processor chip or a wireless radio chip is an example of a SOC.
1.3 VLSI DESIGN STYLES
Several design styles can be considered for chip implementation of specified

algorithms or logic functions. Each design style has its own merits and shortcomings,
and thus a proper choice must be made by designers to provide the functionality at low
cost.
FIELD PROGRAMMABLE GATE ARRAY (FPGA)
Fully fabricated FPGA chips containing thousands of logic gates or even more,
with programmable interconnects, are available to users for their custom hardware
programming to realize desired functionality. This design style provides a means for
fast prototyping and for cost-effective chip design, especially for low-volume
applications. A typical field programmable gate array (FPGA) chip consists of I/O
buffers, an array of configurable logic blocks (CLBs), and programmable interconnect
structures. The programming of the interconnects is implemented by programming of
RAM cells whose output terminals are connected to the gates of MOS pass transistors.
A more detailed view showing the locations of switch matrices used for interconnect
routing.
A simple CLB (model XC2000 from XILINX) It consists of four signal input
terminals (A, B, C, D), a clock signal terminal, user-programmable multiplexers, an
SR- latch, and a look-up table (LUT). The LUT is a digital memory that stores the truth
table of the Boolean function. Thus, it can generate any function of up to four variables
or any two functions of three variables.
CLB is configured such that many different logic functions can be realized by
programming its array. More sophisticated CLBs have also been introduced to map
complex functions. The typical design flow of an FPGA chip starts with the behavioral

description of its functionality, using a hardware description language such as VHDL.

The synthesized architecture is then technology-mapped (or partitioned) into circuits or
logic cells. At this stage, the chip design is completely described in terms of available
logic cells. Next, the placement and routing step assigns individual logic cells to FPGA
sites (CLBs) and determines the routing patterns among the cells in accordance with the
net list.
Performance of the design can be simulated and verified before downloading the
design for programming of the FPGA chip. The programming of the chip remains valid
as long as the chip is powered-on or until new programming is done. In most cases, full
utilization of the FPGA chip area is not possible - many cell sites may remain unused.
The largest advantage of FPGA-based design is the very short turn-around time,
i.e., the time required from the start of the design process until a functional chip is
available. Since no physical manufacturing step is necessary for customizing the FPGA
chip, a functional sample can be obtained almost as soon as the design is mapped into a
specific technology.
The typical price of FPGA chips are usually higher than other realization
alternatives (such as gate array or standard cells) of the same design, but for small-
volume production of ASIC chips and for fast prototyping, FPGA offers a very
valuable option.
GATE ARRAY DESIGN
In view of the fast-prototyping capability, the gate array (GA) comes after the
FPGA. While the design implementation of the FPGA chip is done with user
programming, that of the gate array is done with metal mask design and processing.
Gate array implementation requires a two-step manufacturing process: The first phase,
which is based on generic (standard) masks, results in an array of uncommitted
transistors on each GA chip. These uncommitted chips can be stored for later
customization, which is completed by defining the metal interconnects between the
transistors of the array Since the patterning of metallic interconnects is done at the end
of the chip fabrication, the turn- around time can be still short, a few days to a few
weeks. a corner of a gate array chip which contains bonding pads on its left and bottom
edges, diodes for I/O protection, nMOS transistors and pMOS transistors for chip
output driver circuits in the neighboring

areas of bonding pads, arrays of nMOS transistors and pMOS transistors, underpass
wire segments, and power and ground buses along with contact windows.
Magnified portion of the internal array with metal mask design (metal lines
highlighted in dark) to realize a complex logic function. Typical gate array platforms
allow dedicated areas, called channels, for inter cell routing. The availability of these
routing channels simplifies the interconnections, even using one metal layer only. The
interconnection patterns to realize basic logic gates can be stored in a library, which can
then be used to customize rows of uncommitted transistors according to the net list.
While most gate array platforms only contain rows of uncommitted transistors
separated by routing channels, some other platforms also offer dedicated memory
(RAM) arrays to allow a higher density where memory functions are required. The
layout views of a conventional gate array and a gate array platform with two dedicated
memory banks.
With the use of multiple interconnect layers, the routing can be achieved over
the active cell areas; thus, the routing channels can be removed as in Sea-of-Gates
(SOG) chips. Here, the entire chip surface is covered with uncommitted nMOS and
pMOS transistors. As in the gate array case, neighboring transistors can be customized
using a metal mask to form basic logic gates. For intercell routing, however, some of
the uncommitted transistors must be sacrificed. This approach results in more flexibility
for interconnections, and usually in a higher density. The basic platform of a SOG chip
is shown in offers a brief comparison between the channeled (GA) vs. the channel less
(SOG) approaches.
STANDARD-CELLS BASED DESIGN
The standard-cells based design is one of the most prevalent full custom design
styles which require development of a full custom mask set. The standard cell is also
called the police. In this design style, all the commonly used logic cells are developed,
characterized, and stored in a standard cell library. A typical library may contain a few
hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates,
D-latches, and flip-flops. Each gate type can have multiple implementations to provide
adequate driving capability for different fan outs. For instance, the inverter gate can
have standard size transistors, double size transistors, and quadruple size transistors so
that the chip designer can choose the proper size to achieve high circuit speed and
layout density. The characterization of each cell is done for several different categories.

It consists of

 delay time vs. load capacitance
 circuit simulation model
 timing simulation model
 fault simulation model
 cell data for place-and-route, mask data
To enable automated placement of the cells and routing of inter-cell connections,

each cell layout is designed with a fixed height, so that several cells can be abutted
side- by-side to form rows. The power and ground rails typically run parallel to the
upper and lower boundaries of the cell; thus, neighboring cells share a common power
and ground bus. The input and output pins are located on the upper and lower
boundaries of the cell. Notice that the nMOS transistors are located closer to the ground
rail while the pMOS transistors are placed closer to the power rail.
FULL CUSTOM DESIGN
Although the standard-cells based design is often called full custom design, in a
strict sense, it is somewhat less than fully custom since the cells are pre-designed for
general use and the same cells are utilized in many different chip designs. In a fuller
custom design, the entire mask design is done anew without use of any library.
However, the development cost of such a design style is becoming prohibitively high.
Thus, the concept of design reuse is becoming popular to reduce design cycle time and
development cost. The most rigorous full custom design can be the design of a memory
cell, be it static or dynamic. Since the same layout design is replicated, there would not
be any alternative to high density memory chip design. For logic chip design, a good
compromise can be achieved by using a combination of different design styles on the
same chip, such as standard cells, data-path cells and PLAs. In real full-custom layout
in which the geometry, orientation and placement of every transistor is done
individually by the designer, design productivity is usually very low - typically 10 to 20
transistors per day, per designer.
In digital CMOS VLSI, full-custom design is rarely used due to the high labor
cost. Exceptions to this include the design of high-volume products such as memory
chips, high- performance microprocessors and FPGA masters. The full layout of the
Intel 486 microprocessor chip which is a good example of a hybrid full-custom design.
Here, one

can identify four different design styles on one chip: Memory banks (RAM cache),
data- path units consisting of bit-slice cells, control circuitry mainly consisting of
standard cells and PLA blo

CHAPTER2
LITERATURE SURVEY
LITERATURE SURVEY
LITERATURE SURVEY
During the LOW state of the clock signal the pre-loading voltage transistor
charge to HIGH state and this phase of operation is known as the precharge phase and
then in evaluation phase the CLK signal is represented in HIGH state then the pull in
network performs during the analysis stage [1].
The domino logic circuit is an exact from as that of clocked CMOS circuit. Here the
precharge, evaluation phases and clock were used for a cascaded series of domino logic
block. A conventional dynamic circuit needs M Keeper transistor to defend the level of
the D node in case of splitting of charge, outflow of current and source of noise. In the
mainstream domino logic that integrate M pmos keeper to refresh and to keep the D
node HIGH against the intrinsic noise source such as a gradual transfer of current and
splitting of charge affects the D node during the FALSE state evaluation of the PIN.
Though if PIN accurate the charge at the D node that carry out to the pull network
invariant as the keeper transistor seeks to sustain the D node HIGH [2].
The compliment loop combines the keeper circuit of the domino circuit additionally
provokes the change of the delay and the outcome of the process modifications in the
delay of the dynamic and static CMOS are analyzed in the depth as a function of the
circuit specifications. The objective of the delay variability depends upon the circuit
parameters like number of arranged transistors like fan-in their capacitance of load,
size, and circuit topology. The variability of the delay is doubled when compared to the
static logic consequent the keeper circuit transistor [4].
The growth of low technology nodes executes current leakage, supply and threshold
voltage are major occurring factors. The threshold leakage of current is defined as Is1
and the gate oxide leakage current is defined as Ig1 defined major elements of the
domino circuit and such component convert domino circuit as a high sensitive circuit,
the small input noise that tends to the reduction of robustness and it also been note that
the state of the clock and the combinations of input holds an extreme impact on the
mechanism of the outcome of the transistor or robustness and even when accuracy of
speed is increased. The study seeks solutions related to increases of leakage current,
increasing of complexity of the keeper circuit transistor current consequent, extended
noise margin and

resultant an extreme delay and rise of charge and disparate measurements are obtained.
The mutation of the domino circuit improves reliability and momentum of the domino
circuit [5].
The domino logic acquires the extreme throughput caused by minimum a noise
margin collated to the conventional CMOS. Reduced noise margin indicates a rise of
acuteness of the domino logic circuit towards the noise source. In domino logic circuits
noise exception can increase by downscaling technology. This scaling factor increases
the power consumption of the circuit. Hence to decreases consumption of power the
voltage supply is scaled down then delay in the circuit increased and satisfies the
threshold delay scaling voltage is done through voltage supply scaling. The reduction of
threshold voltage boosts up the speed of the domino circuit reduces the immune of
noise of the circuit by increasing of the leakage sub-threshold current. The technologies
of scaling abate the concentration of the gate oxide that generates a sharp growth of sub
threshold, leakage current at the gate and the overflow of current. Due to overcome off
current, the noise source and low threshold voltage makes to lower the execution of the
domino circuit at extreme frequencies. The scaling of the devices leads to increase the
overflowing of the current of the domino circuit by the Small Channel Effects. The
small channel effects reduce efficiency of the length of a channel in the device due to
the reduction of the efficiency of the length the threshold voltage also reduces [6].
The approach for the first model is more efficient during the power of dynamic
CMOS is proportional to the voltage swing led to power saving. The advantage of the
next perspective of the dynamic power leads to the decreases the conflict current by a
smart keeper circuit. The next approach of the domino circuit that is proposed was a
Modified Charging Based Domino circuit that can stabilize the reducing the large
amount of power dissipation in large fan-in gates [7, 8, 15]. The static output reduces
through voltage swing at D nodes are continued keeping the preceding assert charge of
the D node during the consecutive precharge and as a result the reduction of power
consumption is observed [9, 10].
The D node is in the drifting condition during the time of delay and produces
the utilization of power and outflow of current reproduction is in the fig.1. Hence the
strength of the keeper is controlled by current mirror circuits which reconstruct the
outflow of the current in the pull down the network [11].

This technique is utilized to reduce the robustness and to increases the power
dissipation when it is practiced in the fan-in circuits. If the PMOS is in the grounded
state, then the additional transistor is kept in progress to reduce gain in the loop that is
produced. The grounded PMOS is observed in the fig. [12].
The foot-driven stacked transistor domino logic (FDSTDL) the circuit consists
of an auxiliary recharge path used to control the obtained output and delay reduced by
foot node voltage [8].
The proposed CDDK circuit reduces conflict current describes for increased
delay enabled by the keeper circuit that is performed with the auxiliary keeper transistor
Mk2. The auxiliary keeper was kept activated by an inverter circuit that was
inaugurated after the delay time. The input signal is a CLK that is associated by the
footer device of the domino logic circuit of CDDK. The formal keeper Mk1 restricts at
the terminal of the gate of the domino output [13].
Earlier in few decades before the speed and area in CMOS technology circuits
had essential reduced by describing the new design techniques done by fully integral
CMOS circuit logic functioning of every gate is executed twice. The main problem that
occurred by this approach is that a complex gate of 32 AOI gate has no static power,
but extreme capacitance of output and a significant amount of area has wasted. To
defeat that problem, they stated a new close-packed high- performance circuit design
technique was introduced to use with the CMOS technology. The main objective of this
paper was that they proposed a circuit with area comparability of static NMOS or
Pseudo-NMOS allows a speed improvement of 1.5 to 2 and performed without
resorting some multiphase and static stability maintained in the circuit [14].
In the CMOS circuit, power predominate the dissipation of power, by reduces
the voltage supply which active to reduce the dissipation of dynamic power. The
overcasting of VDD is crucial effect to reduce reliability problems and by reducing the
voltage supply alone causes the huge downgrade in the circuit performance, the Vdd,
threshold voltage Vth to scale down by the circuit performance. To maintain critical
path the delay the low threshold voltage is to be utilized. A newly shaped domino
circuit was proposed, and it is a scaling down approached techniques stated that the
speed and the threshold voltage decreased by controlling the noise margin
implementing by High-Speed Domino, the main objective is that a new modification of
the domino logic circuit is MTCMOS is proposed that momentum and low dynamic
power is maintained in the effective mode [15].

CHAPTER-3
SCOPE OF THE PROJECT AND PROPOSED APPROACH
SCOPE OF THE PROJECT AND PROPOSED APPROACH
3.1 SCOPE OF THE PROJECT

The scope of the project "Speed Enhancement Techniques for Clock-Delayed
Dual Keeper Domino Logic Style Using Sleep Transistor" involves the following:
1. Study of Clock-Delayed Dual Keeper Domino Logic Style: The first step is to
understand the Clock-Delayed Dual Keeper Domino logic style and its basic
operation. This involves studying the basic building blocks of the logic style,
such as the Domino gate, the Keeper transistor, and the Delay element.
2. Study of Sleep Transistor: The second step is to understand the Sleep transistor
and its operation. This involves studying the basic building blocks of the Sleep
transistor, such as the Body biasing technique, the Gate biasing technique, and
the Sleep signal generation.
3. Implementation of the Circuit: The third step is to implement the circuit using the
Clock-Delayed Dual Keeper Domino logic style and integrate the Sleep transistor
into the circuit. The circuit will be designed using a standard CMOS process
technology.
4. Simulation and Analysis: The fourth step is to simulate the circuit using a circuit
simulator and analyze the results. The simulation will be performed for different
input patterns and the results will be analyzed in terms of speed, power
consumption, and delay.
5. Comparison with Existing Techniques: The fifth step is to compare the proposed
technique with the existing techniques in terms of speed, power consumption,
and delay. This will help in identifying the advantages of the proposed technique
over the existing techniques.
6. Conclusion and Future Work: The final step is to draw conclusions from the
results obtained and identify the future work that can be done to further improve
the proposed technique.
Overall, the project aims to develop a new technique to enhance the speed of
the Clock-Delayed Dual Keeper Domino logic style using the Sleep transistor. The
proposed technique will be compared with the existing techniques to demonstrate its
effectiveness.

3.2PROPSOED APPROCH
This project presents speed enhancement techniques for the Clock-Delayed Dual
Keeper Domino logic style using Sleep transistor. The Clock-Delayed Dual Keeper
Domino logic style is a popular design technique that offers high-speed performance
with low power consumption. However, there is still room for improvement in terms
of speed, which is critical for high-performance applications.
The proposed technique involves the integration of Sleep transistors into the
Clock-Delayed Dual Keeper Domino logic style. Sleep transistors are a type of
transistor that can be used to switch off the circuit during idle periods, thereby
reducing power consumption. The Sleep transistor can also be used to reduce the
delay of the circuit by reducing the leakage current.
The circuit was implemented using a standard CMOS process technology,
and simulations were performed using a circuit simulator. The simulation results
showed that the proposed technique offers significant speed improvement compared
to the existing techniques. The proposed technique also offers a reduction in power
consumption and delay, making it suitable for high-performance applications.
The results of this project demonstrate that the integration of Sleep transistors
into the Clock-Delayed Dual Keeper Domino logic style can lead to significant speed
improvement, making it an effective technique for high-performance applications.

CHPATER 4
SOFTWARE AND HARDWARE DESCRIPTION
SOFTWARE AND HARDWARE DESCRIPTION

4.1 REQUIREMENTS
Hardware
 Hard Disk-1GB
 RAM-4GB
 LAPTOP
 Windows-7 OS
Software
 DSCH
 MICROWIND
4.2 TOOL (DSCH& EXPORT MICRO WIND)
The DSCH3 program is a logic editor and simulator. DSCH3 is used to
validate the architecture of the logic circuit before the microelectronics design is
started. DSCH3 provides a user-friendly environment for hierarchical logic design,
and fast simulation with delay analysis, which allows the design and validation of
complex logic structures. Some techniques for low power design are described in the
manual. DSCH3 also features the symbols, models, and assembly support for 8051
and 18f64. DSCH3 also includes an interface to SPICE. The
MICROWIND3program allows the student to design and simulate an integrated
circuit at physical description level. The package contains a library of common logic
and analog ICs to view and simulate. MICROWIND3includes all the commands for
a mask editor as well as original tools never gathered before in a single module (2D
and 3D process view, Verilog compiler, tutorial on MOS devices). You can gain
access to Circuit Simulation by pressing one single key. The electric extraction of
your circuit is automatically performed, and the analog simulator produces voltage
and current curves immediately.
THE MOS DEVICE:
Logic Levels:
Three logic levels 0,1 and X are defined as follows Table. 4.1:

Table. 4.1 Logic Levels.

The MOS transistor is basically a switch. When used in logic cell design, it
can be on or off. When on, a current can flow between drain and source. When off,
no current flow between drain and source. The MOS is turned on or off depending on
the gate voltage. In CMOS technology, both n-channel (and nMOS) and p-channel
MOS (or pMOS) devices exist. The nMOS and pMOS symbols are reported below.
The symbols for the ground voltage source (0 or VSS) and the supply (1 or VDD).
Fig. 4.1 N-Channel and P-Channel.
The n-channel MOS device requires a logic value 1 (or a supply VDD) to be
on. In contrary, the p-channel MOS device requires a logic value 0 to be on. When
the MSO device is on, the link between the source and drain is equivalent to a
resistance. The order of range of this ‘on’ resistance is 100Ω-5KΩ. The ‘off’
resistance is considered infinite at first order, as its value is several MΩ.
THE TRANSMISSION GATE:
Both NMOS devices and PMOS devices exhibit poor performances when
transmitting one logic information. The nMOS degrades the logic level 1, the pMOS
degrades the logic level 0. Thus, a perfect pass gate can be constructed from the
combination of nMOS and pMOS devices working in a complementary way, leading
to improved switching performances. Such a circuit is called the transmission
gate. In

DSCH3, the symbol may be found in the Advance menu in the palette. The
transmission gate includes one inverter, one NMOS and one PMOS.
Figure. 4.2 The Transmission Gate.
THE LOGIC INVERTER:

In this section, an inverter circuit is loaded and simulated. Click File→ Open
in the main menu. Select INV.SCH in the list. In this circuit are one button situated
on the left side of the design, the inverter and a led. Click Simulate→ Start
simulation in the main menu.
Fig.4.3 Logics of Inverter.

Now, click inside the buttons situated on the left part of the diagram. The
result is displayed on the lids. The red value indicates logic 1; the black value means
logic 0. Click the button Stop simulation shown in the picture below. You are back
to the editor.
Click the chronogram icon to get access to the chronograms of the previous
simulation. As seen in the waveform, the value of the output is the logic opposite of
that of the input.

Double click on the INV symbol; the symbol properties window is activated.
In this window appear the VERILOG description (left side) and the list of pins (right
side). A set of drawing options is also reported in the same window. Notice the gate
delay (0.03ns in the default technology), the fan out that represents the number of
cells connected to the output pin (1 cell connected), and the wire delay due to this
cell connection (An extra 0.140ns delay).
BASIC GATES:
Table 4.2 gives the corresponding symbol to each basic gate as it appears in
the logic editor window as well as the logic description. In this description, the
symbol & refers to the logical AND, | to OR, ~ to INVERT, NAND ^ to XOR.
Table. 4.2 Basic Gate
The Nand Gate:
The truth-table and logic symbol of the NAND gate with 2 inputs are shown
below. In DSCH, select the NAND symbol in the palette, add two buttons and one
lamp as shown above. Add interconnects if necessary to link the button and lamps to
the cell pins. Verify the logic behavior of the cell.

Figure.4.4 Logic Symbol of the NAND gate.
THE CMOS INVERTER:
The CMOS inverter design is detailed in the figure below. Here the p-channel
MOS and the n-channel MOS transistors function as switches. When the input signal
is logic 0 the nMOS is switched off while PMOS passes VDD through the output.
When the input signal is logic 1, the pMOS is switched off while the nMOS passes
VSS to the output.
The fan-out corresponds to the number of gates connected to the inverter

output. Physically, a large fan-out means many connections, that is a large load
capacitance. If we simulate an inverter loaded with one single output, the switching
delay is small. Now, if we load the inverter by several outputs, the delay and the
power consumption are increased due to the current needed to charge and discharge
that capacitance.
Figure. 4.5 CMOS Inverter Circuits.

Inverter Simulation:
The inverter simulation is conducted as follows. Firstly, a VDD supply source

(1.2V) is fixed to the upper metal2 supply line, and a VSS supply source (0.0V) is
fixed to the lower metal2 supply line. The properties are in the palette menu. Simply
click the desired property and click on the desired location in the layout. Add a clock
on the inverter input node (The default node name clock1 has been changed into Vin)
and a visible property on the output node Vout.
Figure. 4.6 CMOS Inverter Simulation.
The command Simulate → Run Simulation gives access to the analog

simulation. Select the simulation mode Voltage vs. Time. The analog simulation of
the circuit is performed. The time domain waveform, proposed by default,
details the evolution of the voltages in1 and out1 versus time. This mode is also
called transient simulation.
Figure.4.7 CMOS Inverter Wave forms.

4.3 SIMULATION ENVIRONMENT

The simulation parameters have been analyzed with the help of the Micro
wind tool an DSCH for the schematic verification.
4.3.1 DSCH (DIGITAL SCHEMATIC):
DSCH is software for logic design. Based on primitives, a hierarchical circuit

can be built and simulated. It also includes delay and power consumption evaluation.
Silicon is for 3D display of the atomic structure of silicon, with emphasis on the
silicon lattice, the do pants, and the silicon dioxide.
MOS as a Switch:
The MOS transistor is basically a switch. When used in logic cell design, it
can be on or off. When on, a current can flow between drain and source. When off,
no current flow between drain and source. The MOS is turned on or off depending on
the gate voltage. In CMOS technology, both n-channel (and nMOS) and p-channel
MOS (or pMOS) devices exist. The nMOS and pMOS symbols are reported below.
Fig. 4.8 Symbol of NMOS and PMOS.
The n-channel MOS device requires a logic value 1 (or a supply VDD) to be
on. In contrary, the p-channel MOS device requires a logic value 0 to be on. When
the MSO device is on, the link between the source and drain is equivalent to a
resistance. The order of range of this ‘on’ resistance is 100Ω-5KΩ. The ‘off’
resistance is considered infinite at first order, as its value is several MΩ.
Connecting Procedure:
Instantiate NMOS or PMOS transistors from the symbol library and place
them in the editor window. Connect Vdd and GND to the schematic. Connect input
button and

The simulation output can be observed as a waveform after the application of the
inputs as above. Click on the timing diagram icon in the icon menu to see the timing
diagram of the input and output waveforms. The Verilog, Hierarchy and Net list
window appears. This window neither shows the Verilog representation of NOR
gate. Click OK to save the Verilog as a .txt file.
4.3.2 MICROWIND:
Micro wind is a tool for designing and simulating circuits at layout level. The
tool features full editing facilities (copy, cut, past, duplicate, move), various views
(MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator.
The Micro wind program allows designing and simulating an integrated circuit at
physical description level. The package contains a library of common logic and
analog ICs to view and simulate.
Micro wind includes all the commands for a mask editor as well as original
tools never gathered before in a single module (2D and 3D process view, Verilog
compiler, tutorial on MOS devices). You can gain access to Circuit Simulation by
pressing one single key. The electric extraction of your circuit is automatically
performed, and the analog simulator produces voltage and current curves
immediately.
MOS Layout:
Micro wind is used to draw the MOS layout and simulate its behavior. The
Micro wind display window includes four main windows:
1. The main menu
2. The layout display window
3. The icon menu
4. The layer palette.
The layout window features a grid, scaled in lambda (λ) units. The lambda
unit is fixed to half of the minimum available lithography of the technology. The
default technology is a CMOS 6-metal layers 0.12µm technology, consequently
lambda is 0.06µm (60nm). The palette is in the lower right corner of the screen. A
red color indicates the current layer. Initially the selected layer in the palette is
polysilicon. By using the following procedure, you can create a manual design of the
n-channel MOS.
1. Fix the first corner of the box with the mouse. While keeping the mouse button
pressed, move the mouse to the opposite corner of the box. Release the button.
This creates a box in polysilicon layer. The box width should not be inferior to 2
λ, which is the minimum width of the polysilicon box.
2. Change the current layer into N+ diffusion by a click on the palette of the
Diffusion N+ button. Make sure that the red layer is now the N+ Diffusion. Draw
a n-diffusion box at the bottom of the drawing as in Figure. 6.2 N-diffusion boxes
are represented in green. The intersection between diffusion and polysilicon
creates the channel of the nMOS device.
Fig. 4.9 Creating the N-channel MOS transistor.
Static MOS Characteristics:
The MOS size (width and length of the channel situated at the intersection
of the polysilicon gate and the diffusion) has a strong influence on the value of the
current. In Figure, the MOS width is 1.74µm and the length is 0.12µm. A high gate
voltage (Vg
=1.2V) corresponds to the highest Id/Vdd curve. For Vg=0, no current flows. You may
change the voltage values of Vdd, Vg, Vs by using the voltage cursors situated on the
right side of the window. A maximum current around 1.5mA is obtained for Vg=1.2V,
Vdd=1.2V, with Vs=0.0. The MOS parameters correspond to SPICE Level 3.

Fig. 4.10 N-Channel MOS characteristics.
Layout Design:
Click the icon MOS generator on the palette. The following window
appears. By default, the proposed length is the minimum length available in the
technology (2 lambda), and the width is 10 lambda. In 0.12µm technology, where
lambda is 0.06µm, the corresponding size is 0.12µm for the length and 0.6µm for the
width. Simply click Generate Device and click on the middle of the screen to fix the
MOS device. Click again the icon MOS generator on the palette. Change the type of
device by a tick on p-channel and click Generate Device. Click on the top of the
nMOS to fix the pMOS device.
Fig.4.11 Selecting the PMOS device.
Connection between
Devices: Metal to Poly:

As polysilicon is a poor conductor, metal is preferred to interconnect

signals and supplies. Consequently, the input connection of the inverter is made with
metal. Metal and polysilicon are separated by an oxide which prevents electrical
connections. Therefore, a box of metal drawn across a box of polysilicon does not
allow an electrical connection. To build an electrical connection, a physical contact is
needed. The corresponding layer is called "contact". You may insert a metal-to-
polysilicon contact in the layout using a direct macro situated in the palette.
Supply Connections:
The next design step consists in adding supply connections, that is the
positive supply VDD and the ground supply VSS. We use the metal2 layer (Second
level of metallization) to create horizontal supply connections. Enlarging the supply
metal lines reduces the resistance and avoids electrical overstress. The simplest way
to build the physical connection is to add a metal/Metal2 contact that may be found
in the palette. The connection is created by a plug called "via" between metal2 and
metal layers. The final layout design step consists in adding polarization contacts.
These contacts convey the VSS and VDD voltage supply close to the bulk regions of
the device. Remember that the n-well region should always be polarized to a high
voltage to avoid short-circuit between VDD and VSS. Adding the VDD polarization
in the n-well region is a very strict rule.
Interconnects:
Up to 6 metal layers are available for signal connection and supply purpose. A
significant gap exists between the 0.7µm 2-metal layer technology and the 0.12µm
technology in terms of interconnects efficiency.
Firstly, the contact size is 6 lambdas in 0.7µm technology, and only 4 lambdas
in 0.12µm. This features a significant reduction of device connection to metal and
metal2. Notice that a MOS device generated using 0.7µm design rules is still
compatible with 0.12µm technology. But a MOS device generated using 0.12µm
design rules would violate several rules if checked in 0.7µm technology. Secondly,
the stacking of contacts is not allowed in micro technologies. This means that a
contact from poly to metal2 requires a significant silicon area as contacts must be
drawn in a separate location. In deep-submicron technology (Starting 0.35µm and
below), stacked contacts are allowed.

Simulation:
A simulation window appears with inputs and output, shows the tphl, tplh
and tp of the circuit. The power consumption is also shown on the right bottom
portion of the window. If you are unable to meet the specifications of the circuit
change the transistor sizes. Generate the layout again and run the simulations till you
achieve your target delays. Depending on the input sequences assigned at the input
the output is observed in the simulation. The power value is also given.
Checking the Layout:
The Design Rule Checker (DRC) scans the design and verifies a set of design
rules. The errors are highlighted in the display window, with an appropriate message
giving the nature of the error. Details about the position and type of error(s) appear on
the screen. Only an error-free layout can be sent to fabrication.

CHAPTER-5
IMPLEMENTATION
IMPLEMENTATION
5.1 INTRODUCTION
Domino logic circuits are widely in use due to their reduced transistor
count, high-speed performance and reduced logical effort. Realization of wide fan in
gates using domino logic circuit style is normally preferred as in the Pull-Up
Network (PUN); they evade stacking of transistors and are extensively used in design
of Static Random Access Memory (SRAM) pre-decoders, tag comparators and
programmable encoders. The domino logic circuit design with reduced transistor
count and the evaluation being performed only by N-type Metal Oxide
Semiconductor (NMOS) transistors makes it a preferable circuit style compared to
static Complementary Metal Oxide Semiconductor (CMOS) circuit in terms of chip
area and speed performance. However, it offers low noise gain margin due to leakage
current and charge sharing which occur in the internal nodes. In addition, the
dynamic power consumption is increased because of redundant switching at output
node for every pre-charge operation, even for consecutive identical inputs. In
conventional domino logic circuit, the PUN comprises of a single pre-charge PMOS
transistor and pull-down network (PDN) consists of NMOS evaluation transistors,
with a static inverter connected at the dynamic node D as shown in Figure 1. The
keeper transistor MK protects the dynamic node against leakage current and charge
sharing. The keeper ratio K stated as K ¼ W Keeper WPDN (1) where W Keeper is
the keeper transistor width and WPDN is the evaluation transistor’s width in the
PDN. The upsizing of keeper transistor MK improves the robustness of the circuit,
by trading off the speed performance (Moradi et al., 2013). This has been addressed
by various researchers to design high speed, robust domino logic circuit topologies
for reduced power consumption. This had led to design of various other domino logic
structures with modification in the keeper circuit or the PDN of the conventional
domino logic circuit style The controlling of the keeper circuit is based on anyone of
the following approaches such as:
(i) delayed enabling of the keeper circuit,
(ii) abrupt keeper control mechanism,
(iii) keeper control signal with voltage swing variation,
(iv) keeper mechanisms with process variation tolerance and
(v) bias voltage variation of the keeper device.

The various other topologies based on PDN modification have also

been proposed in the literature, in which an additional discharge path is
augmented. This results in increased operating speed and reduction of leakage
current mechanisms.
Figure 5 (a) depict the high-speed domino (HSD)

Figure 5 (a) depict the high-speed domino (HSD) logic in which the keeper
control circuit is enabled after a small delay. This causes the dynamic node to remain
in floating condition during that initial delay time. This can however result in
increased power consumption. In leakage current replica (LCR) keeper technique
Figure 5(b) Leakage current replica keeper domino logic


Figure 5(b), the strength of the keeper device is controlled by an analog

current mirror circuit, which is dependent on the leakage current of PDN. On the
other hand, it is to be noted that for wider fan in circuits, this technique incurs
increased power dissipation with reduced robustness.
Figure 5 (c) Grounded PMOS keeper

An additional keeper transistor along with the conventional keeper transistor
reduces the loop gain and decreases the delay variability in grounded PMOS keeper
structure shown in Figure 5 (c).
An additional discharge path is controlled by output voltage and foot node voltage
in foot-driven stacked transistor domino logic (FDSTDL) as depicted in Fig.5(d)
Fig. 5(d) Foot-driven stacked transistor domino logic

This reduces the delay in discharge of the dynamic node and accelerates
the transitions in the output node. Clock-delayed dual keeper (CDDK) domino circuit
structure has also been proposed in the same line of research with modifications in
keeper circuit for decreasing the contention during the beginning of evaluation phase.
CDDK circuit operates on the principle of delayed enabling of keeper circuit, which
comprises of dual PMOS keeper transistors in series. This feature of delayed
enabling of keeper circuit reduces the contention current between the keeper
transistor and PDN.

Hence, ifthe PDN evaluates a TRUE condition, it facilitates faster discharge of the
dynamic nodal charge through PDN, which enhances the operating speed of circuit.
In domino logic circuits, the feedback loop gain and process parameter variations
contribute to considerable amount of delay variability. These issues accentuate the
necessity of identifying suitable enhancement techniques, which can offer high-speed
performance with reduced delay variability under statistical process parameter
variations of the keeper circuit. This paper proposes the following four high-speed
enhancement techniques on CDDK circuit to enhance the speed performance by
alleviating the contention current problem.
(1) Controlled clock delay time in enabling the keeper transistor
(2) Keeper control signal with voltage swing variation
(3) Keeper transistor sizing
(4) Additional conditional discharge pat
Also, reduced delay variability is ensured in all the techniques for repeated runs. The
high-speed techniques of CDDK domino circuits have been simulated and analyzed
for speed, power consumption, noise gain margin and delay variability factor using
wide fan- in benchmark circuits. UMC 90nm technology node library using Cadence
Virtuoso® ADEL and ADEXL environments has been utilized for design and
simulation of enhancement techniques on CDDK domino circuit. Delay variability is
observed using Monte–Carlo analysis for 2000 runs under statistical variations of
process parameters.
5.2 CLOCK-DELAYED DUAL KEEPER (CDDK) DOMINO CIRCUIT

Figure 5.2 depicts CDDK circuit comprising pre-charge transistor MP and
keeper transistors MK1 and MK2 in series. The MK2 keeper device is controlled by
the delayed inverted clock CLK_DI which is introduced by inverter I2 on CLK
signal While the CLK is LOW (pre-charge phase), the transistor MP conducts and
makes the dynamic node to be HIGH. Consequently, the output becomes LOW.
While the CLK is HIGH (evaluation phase), the PDN evaluates for the inputs. The
evaluation phase is deterred as follows. The inverter I2 introduces a delay on CLK
signal as characterized by the inverter device size. This makes the keeper transistor
MK2 to be cut-off initially for a brief duration, due to delayed inverted clock signal
CLK_DI that is still HIGH.

The inverter I2 is optimally sized such that it is sufficient to offer a

momentary delay in disabling the keeper device MK1, only during the beginning of
the evaluation phase and reduce the contention current between the keeper circuit
and the PDN. Thus,
if the PDN evaluates a TRUE condition, the keeper circuit being cut-off prevents
replenishing the dynamic node to HIGH state through keeper circuit and this feature
facilitates faster discharge of the dynamic node charge and the output signal OUT
becomes HIGH. If the PDN evaluates a FALSE condition, the dynamic node is still
retained at VDD, as the keeper transistor MK2 is enabled after the delay incurred by
the inverter I2 circuit. During the brief period of MK2 cut-off time and during the
beginning of the evaluation phase, the dynamic node D is self-sufficient in retaining
the dynamic nodal charge (acquired through pre-charge operation).
Thus, the additional keeper transistor MK2, in series along with the conventional
keeper transistor MK1, reduces the contention and thereby results in increased
operating speed. Table 1 depicts the transistor’s states of CDDK circuit during
various phases of operation. In the domino keeper structure, the positive feedback
loop gain T decreases as transconductance offered by the keeper transistor gmK1 is
reduced as stated in Equation (2). Here, A in v is the inverter gain and ZX is the total
impedance of dynamic node. T ¼ AinvgmK1ZX (2) In CDDK domino circuit, the
keeper transistor MK2 behaves as a closed switch offering a resistance R during
evaluation phase. This reduced resistance accounts for source degeneration of keeper
transistor Mk1 in the feedback circuit. This reduces the effective trans-conductance
Gm; eff of the keeper device K1 in the feedback loop as expressed by Gm; eff ¼
GmK1 ð Þ 1 þ GmK1.
Figure 5.2. Clock-delayed domino keeper circuit topology

5.3 ADDITIONAL CONDITIONAL DISCHARGE PATH

During evaluation, due to PDN input conditions, when the dynamic node is to
be discharged, it incurs the path delay imposed by PDN. Hence, CDDK domino
circuit is incorporated with an additional discharge path which facilitates faster
discharge of dynamic node. Figure 4 depicts the CDDK domino circuit, comprising
the additional discharge path with MN1 and MN2 devices controlled by the footer
node voltage V foot and the clock CLK, respectively. During pre-charge phase, when
the CLK is LOW, since MN2 is cut-off, the additional discharge path is cut-off.
During initial evaluation phase, if the PDN is TRUE, the V foot attains HIGH and
enables MN1 and the clock CLK enables MN2. This paves way for faster discharge
of the dynamic node through MN1 and MN2. The sizing of both the footer transistor
Mf and the devices in the PDN determines V foot, which is set to be slightly above
Vth of the MN1. Upsizing the evaluation transistors of PDN increases the V foot and
upsizing the footer transistor decreases the V foot. Hence, the sizing of the PDN
transistors and the footer device are done in such a way that V foot Vth MN1, to
enable the additional discharge path, while the PDN evaluates TRUE condition.
Figure 5.3. CDDK domino circuit with additional conditional discharge path

5.4 PROPOSED DOMINO (WITH SLEEP TRANSISTOR)
Figure 5.4 Proposed Domino (with sleep transistor)

Domino logic with sleep transistor is a technique that combines the speed and
efficiency of domino logic with the low power consumption of sleep transistor
design. In this technique, sleep transistors are added to the domino logic gates to
reduce power consumption when the gates are not in use.
The sleep transistors act as switches that disconnect the gate from the power
supply, effectively turning it off when it is not needed. When the gate is needed
again, the sleep transistor is turned on, and the gate is reactivated.
The use of sleep transistors allows the domino logic circuit to conserve power
by reducing the leakage current that flows through the gate when it is not in use. This
can be especially beneficial in applications where power consumption is a critical
factor, such as in portable devices or low-power sensors.
Operation
Domino Logic is a type of dynamic logic circuit that uses the precharge-
evaluate technique to perform logical operations. In Domino Logic, a precharge
signal is used to

precharge the output node to a high voltage level, and an evaluate signal is used to
evaluate the input and produce a logical output. The output node is then restored to
its initial precharged state during the precharge phase of the next clock cycle.
To reduce power consumption in Domino Logic, sleep transistors can be
added to the circuit. A sleep transistor is a transistor that can be used to cut off the
power supply to a part of the circuit when it is not needed. When the sleep transistor
is turned off, it blocks the flow of current and reduces power consumption in the
circuit.
The operation of Domino Logic with sleep transistor is as follows:
During the precharge phase, the sleep transistor is turned on, allowing the
output node to be precharged to a high voltage level.
During the evaluate phase, the sleep transistor is turned off, allowing the input
signal to be evaluated and a logical output to be produced.
After the evaluate phase, the sleep transistor is turned on again, cutting off the
power supply to the output node and reducing power consumption in the circuit.
During the next clock cycle, the sleep transistor is turned off again during the
precharge phase, allowing the output node to be precharged to a high voltage level.
By adding sleep transistors to the Domino Logic circuit, power consumption
can be reduced when the circuit is idle or not in use. The sleep transistors allow parts
of the circuit to be powered down when they are not needed, reducing the overall
power consumption of the circuit. However, the addition of sleep transistors may
also increase the delay in the circuit due to the time required to turn the sleep
transistor on and off. Therefore, the design of the sleep transistor circuit must
carefully balance the tradeoff between power consumption and circuit performance.

CHAPTER-6
IMPLEMENTATION
SIMULATION RESULTS
6.1 CONVENTIONAL DOMINO LOGIC
In the context of digital circuits, Domino refers to a type of dynamic logic called
Domino logic. This type of logic is based on the principle of signal propagation by
"domino effect," where the output of one stage of the circuit triggers the next stage to
produce its output.
In Domino logic, the output of a logic gate is connected to the input of the next
stage, and the signal is propagated through the circuit by the discharge of the output
node of each stage. The circuit is precharged before each evaluation phase, and the
evaluation determines whether the output node should discharge or remain charged
based on the input signal.
CONVENTIONAL DOMINO LOGIC DSCH OUTPUT

CONVENTIONAL DOMINO LOGIC MICROWIND LAYOUT
CONVENTIONAL DOMINO LOGIC MICROWIND OUTPUT

6.2 HIGH SPEED DOMINO LOGIC
HIGH SPEED DOMINO LOGIC DSCH OUTPUT

HIGH SPEED DOMINO LOGIC MICROWIND LAYOUT
HIGH SPEED DOMINO LOGIC MICROWIND OUTPUT

6.3 GROUNDED PMOS KEEPER
GROUNDED PMOS KEEPER DSCH OUTPUT

GROUNDED PMOS KEEPER MICROWIND LAYOUT
GROUNDED PMOS KEEPER MICROWIND OUTPUT

6.4 LEAKAGE CURRENT REPLICA KEEPER DOMINO LOGIC
LEAKAGE CURRENT REPLICA KEEPER DOMINO LOGIC DSCH

OUTPUT

LEAKAGE CURRENT REPLICA KEEPER DOMINO LOGIC

MICROWIND LAYOUT
LEAKAGE CURRENT REPLICA KEEPER DOMINO LOGIC

MICROWIND OUTPUT

6.5 FOOT DRIVEN STACKED TRANSISTOR DOMINO LOGIC
FOOT DRIVEN STACKED TRANSISTOR DOMINO LOGIC DSCH

OUTPUT

FOOT DRIVEN STACKED TRANSISTOR DOMINO LOGIC

MICROWIND LAYOUT
FOOT DRIVEN STACKED TRANSISTOR DOMINO LOGIC

MICROWIND OUTPUT

6.6 CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY
The Clock Delayed Domino Keeper (CDDK) circuit topology is a technique used
in digital integrated circuits to improve their performance by reducing the clock skew
and the clock-to-output delay. It achieves this by using a clock signal that is delayed by a
certain amount before it is applied to the logic gates in the circuit.
The operation of the CDDK circuit topology involves the following steps:
1. The clock signal is delayed by a certain amount using a delay element, such as a
series of inverters or a delay line.
2. The delayed clock signal is then applied to the clock inputs of the sequential logic
gates in the circuit.
3. The combinational logic gates in the circuit receive their inputs from the outputs of
the sequential logic gates and the input signals.
4. The outputs of the combinational logic gates are then latched by the sequential logic
gates on the rising edge of the delayed clock signal.
5. The outputs of the sequential logic gates are then propagated to the next stage of the
circuit or to the output pins of the integrated circuit.
By using the CDDK circuit topology, the clock skew and the clock-to-output
delay are reduced, which allows for faster operation and higher performance of the
digital

integrated circuit. However, it also requires additional circuitry and design complexity,
which can increase the cost and power consumption of the circuit.
CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY DSCH
OUTPUT
CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY MICROWIND

LAYOUT

CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY MICROWIND

OUTPUT
6.7 CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY WITH

ADDITIONAL DISCHARGE PATH

The Clock Delayed Domino Keeper (CDDK) circuit topology is a type of

dynamic logic circuit that uses a delayed clock signal to improve the performance of the
circuit. The basic operation of the CDDK circuit is as follows:
1. At the rising edge of the clock signal, the input signal is latched into a feedback loop.
2. The feedback loop is composed of a chain of gates that are connected in a domino
fashion. The output of each gate drives the input of the next gate in the chain.
3. The feedback loop is completed when the output of the last gate in the chain is fed
back to the input of the first gate in the chain.
4. As the input signal propagates through the feedback loop, it triggers the gates in the
chain, causing them to change state and produce an output signal.
5. The output signal is delayed by the propagation delay of the feedback loop.
6. The delayed output signal is then used to drive downstream logic circuits.
To further improve the performance of the CDDK circuit, an additional discharge
path can be added to the feedback loop. The discharge path provides a way to reset the
feedback loop and reduce the amount of charge that is stored in the feedback loop during
the evaluation phase.
The operation of the CDDK circuit with an additional discharge path is as follows:
1. At the rising edge of the clock signal, the input signal is latched into the feedback loop.
2. The feedback loop is composed of a chain of gates that are connected in a domino
fashion, and an additional discharge gate that is connected to the output of the last
gate in the chain and the input of the first gate in the chain.
3. As the input signal propagates through the feedback loop, it triggers the gates in the
chain, causing them to change state and produce an output signal.
4. The output signal is delayed by the propagation delay of the feedback loop.
5. At the same time, the delayed output signal is used to drive the additional discharge
gate.
6. The discharge gate is designed to provide a low impedance path to ground, which
discharges any charge that is stored in the feedback loop during the evaluation phase.
7. The discharge gate is activated at the end of the evaluation phase, after the delayed
output signal has been used to drive downstream logic circuits.
8. The discharge gate remains active for a short period of time to ensure that any charge
that is stored in the feedback loop is fully discharged.
9. After the discharge gate has been deactivated, the feedback loop is reset and ready to
receive the next input signal at the next rising edge of the clock signal.

Overall, the addition of the discharge path to the CDDK circuit topology
provides a way to reduce the amount of charge that is stored in the feedback loop during
the evaluation phase, which improves the performance and reliability of the circuit.
CLOCK DELAYED DOMINO KEEPER CIRCUIT TOPOLOGY WITH
ADDITIONAL DISCHARGE PATH DSCH OUTPUT

ADDITIONAL DISCHARGE PATH MICROWIND LAYOUT


ADDITIONAL DISCHARGE PATH MICROWIND OUTPUT
6.8 PROPOSED DOMINO (WITH SLEEP TRANSISTOR)

 Domino logic with sleep transistor is a technique that combines the speed and
efficiency of domino logic with the low power consumption of sleep transistor design.
In this technique, sleep transistors are added to the domino logic gates to reduce power
consumption when the gates are not in use.
 The sleep transistors act as switches that disconnect the gate from the power supply,
effectively turning it off when it is not needed. When the gate is needed again, the
sleep transistor is turned on, and the gate is reactivated.
 The use of sleep transistors allows the domino logic circuit to conserve power by
reducing the leakage current that flows through the gate when it is not in use. This can
be especially beneficial in applications where power consumption is a critical factor,
such as in portable devices or low-power sensors.
Operation
Domino Logic is a type of dynamic logic circuit that uses the precharge-evaluate
technique to perform logical operations. In Domino Logic, a precharge signal is used to
precharge the output node to a high voltage level, and an evaluate signal is used to
evaluate the input and produce a logical output. The output node is then restored to its
initial precharged state during the precharge phase of the next clock cycle.
To reduce power consumption in Domino Logic, sleep transistors can be added
to the circuit. A sleep transistor is a transistor that can be used to cut off the power
supply to a part of the circuit when it is not needed. When the sleep transistor is turned
off, it blocks the flow of current and reduces power consumption in the circuit.
The operation of Domino Logic with sleep transistor is as follows:
1. During the precharge phase, the sleep transistor is turned on, allowing the output
node to be precharged to a high voltage level.
2. During the evaluate phase, the sleep transistor is turned off, allowing the input signal
to be evaluated and a logical output to be produced.
3. After the evaluate phase, the sleep transistor is turned on again, cutting off the power
supply to the output node and reducing power consumption in the circuit.
4. During the next clock cycle, the sleep transistor is turned off again during the
precharge phase, allowing the output node to be precharged to a high voltage level.
By adding sleep transistors to the Domino Logic circuit, power consumption can
be reduced when the circuit is idle or not in use. The sleep transistors allow parts of the
circuit to be powered down when they are not needed, reducing the overall power

consumption of the circuit. However, the addition of sleep transistors may also increase
the delay in the circuit due to the time required to turn the sleep transistor on and off.
Therefore, the design of the sleep transistor circuit must carefully balance the tradeoff
between power consumption and circuit performance.
PROPOSED DOMINO (WITH SLEEP TRANSISTOR) DSCH OUTPUT
PROPOSED DOMINO (WITH SLEEP TRANSISTOR) MICROWIND LAYOUT

PROPOSED DOMINO (WITH SLEEP TRANSISTOR) MICROWIND OUTPUT
6.9 COMPARISON FOR CONVENTIONAL AND PROPOSED CIRCUITS
S. PARAMETERS CONVENTIONAL PROPOSED

No
1 Power 0.73µW 0.58µW
2 Rise Time 65ps 60ps
3 Fall Time 55ps 48ps
4 Time Delay 60ps 54ps
5 Area 132.055µm² 79.502µm²

CHAPTER -7
CONCLUSION AND FUTURE SCOPE

CHAPTER 7
CONCLUSION AND FUTURE SCOPE
CONCLUSION
So, clock-delayed dual keeper domino logic is a high-performance circuit technique
used to increase the speed of digital circuits. Sleep transistors are used to reduce
power consumption and improve the timing characteristics of the circuit. In this
paper, we have discussed various speed enhancement techniques that can be used in
clock-delayed dual keeper domino logic with sleep transistors. These techniques
include using high-VT sleep transistors, using adaptive body biasing, and using
source-coupled sleep transistors. Each of these techniques has been shown to
improve circuit speed and power consumption in different ways. Overall, the use of
sleep transistors in clock-delayed dual keeper domino logic is an effective way to
enhance circuit performance while maintaining low power consumption.
.FUTURE SCOPE
In Future One potential area for future research is the use of advanced process
technologies, such as F in FETs or nanowires, which can provide better control over
the transistor characteristics and potentially further reduce power consumption while
increasing performance. Additionally, the use of new materials such as graphene
could potentially provide better conductivity and reduce power consumption even
further.

REFERENCES
REFERENCES
[1] Anita Angeline, A., Kanchana Bhaaskaran: Design impacts of Delay invariant high-
speed clock delayed dual keeper domino circuit, IET Circuits, Devices and Systems,
2019. Journal of the Maharaja Sayajirao University of Baroda ISSN :0025-0422
Volume- 55, No.1(XI) 2021 89
[2] Peiravi, A., Asyaei, M: ‘Robust low leakage-controlled keeper by current
comparison domino for wide fan-in gates’, Integr. VLSI J., 2012.
[3] Meher, P., Mahapatra, K.: ‘Modifications in CMOS dynamic logic style: a review
paper’, Journal of The Institution of Engineers (India): Series B., 2015.
[4] Dadgour, H.F., Banerjee, K.: ‘A novel variation-tolerant keeper architecture for
high performance low-power wide fan-in dynamic OR gates’, IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., 2010.
[5] Anita Angeline, A., Kanchana Bhaaskaran, V. S.: ‘High speed wide fan-in designs
using clock controlled dual keeper domino logic circuits’, ETRI J., 2019.
[6] Garg, S., Gupta, T.K.: ‘Low power domino logic circuits in deep-submicron
technology using CMOS’, Eng. Sci. Technol. Int. J., 2018.
[7] Moradi, F., Cao, T.V., Vatajelu, E.I., et al.: ‘Domino logic designs for high
performance and leakage-tolerant applications’, Integr. VLSI J., 2013.
[8] Nasserian, M., Kafi-Kangi, M., Maymandi-Nejad, M., et al.: ‘A low-power fast tag
comparator by modifying charging scheme of wide fan-in dynamic OR gates’, Integr.
VLSI J., 2016.
[9] Asyaei, M., Ebrahimi, E.: ‘Low power dynamic circuit for power efficient bitlines’,
AEU-Int. J. Electron. Commun., 2018.
[10] Asyaei, M., Moradi, F.: ‘A domino circuit technique for noise-immune high fan-in
gates’, J. Circuits Syst. Comput., 2018.
[11] Lih, Y., Tzartzanis, N., Walker, W.W.: ‘A leakage current replica keeper for
dynamic circuits’, IEEE J. Solid-State Circuits, 2007.
[12] Alioto, M., Palumbo, G., Pennisi, M., et al.: ‘A simple circuit approach to reduce
delay variations in domino logic gates’, IEEE Trans. Circuits Syst. I, Regul.Pap., 2012.
[13] Angeline, A.A., Bhaaskaran, V.K.: ‘High performance domino logic circuit design
by contention reduction’. VLSI Design: Circuits, Systems and Applications Springer,
Singapore, 2018.

[14] Hua, C.H., Hwang, W., Chen, C.K.: ‘Noise-tolerant XOR-based conditional keeper for
high fan in dynamic circuits. Proc. of IEEE International Symposium on Circuits and
Systems., Japan, 2005.
[15] Krambeck, R.H., Lee, C.M., Law, H.-F.S.: ‘High-speed compact circuits with CMOS’,
IEEE J. Solid-State Circuits, 1982.
[16] Kursun, V., Friedman, E.G.: ‘Domino logic with Variable threshold voltage keeper’,
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2003.
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for scaled-down CMOS and MTCMOS technologies’, IEEE Trans. Very Large Scale
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A Project Report

STRATEGIES FOR ACCELERATING CLOCK- DELAYED DUAL

Under the Guidance of

Dr.S. Vijaya Kumar

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SREENIVASA INSTITUTE OF TECHNOLOGY AND MANAGEMENT STUDIES

Affiliated to J.N.T.U.A, Anantapuramu& NBA

Accredited CHITTOOR-517 127

Dr.S. Vijaya Kumar Dr. K. GOPI, M.E., Ph.D.

Professor, ECE Dept Head of the Department

Submitted for University Examination (Viva-Voce) held on

Internal Examiner External Examiner

I would like to express my heartfelt gratitude to our Management, Chairperson

I would like to express profound gratitude to our beloved principal

K. Mukundha Priya 19751A0465

M. Sai Pavani 19751A0497

On completion of project work we will be able to,

Rubric (CO) Excellent (Wt = 3) Good (Wt = 2) Fair (Wt = 1)

Thorough comprehension Reasonable Improper comprehension

Extensive literature survey with Considerable literature Incomplete literature survey

Clearly understands ethical Moderate understanding Insufficient understanding

Presentation in logical sequence Presentation with key points, Presentation with

Highly enthusiastic towards Interested in Inadequate interest

1.1 Moore’s Law 13

Table Table title Page

4.1 Logic Levels. 30

Complementary Metal Oxide Semiconductor for wide variety of applications in

The revolution in integration industry and IC design made an impeccable shift in

Department of ECE, SITAMS, CHITTOOR Page 12

Fig.1.1 Moore’s Law

Department of ECE, SITAMS, CHITTOOR Page 13

Very-large-scale integration (VLSI) is the process of creating integrated circuits

Department of ECE, SITAMS, CHITTOOR Page 15

In 1989, Gateway Design Automation (and rights to Verilog) was purchased by

At present, there is standards activity to extend Verilog beyond purely digital

Department of ECE, SITAMS, CHITTOOR Page 16

1.2 VLSI DESIGNS CLASSIFICATION

There are THREE CATEGORIES in today`s VLSI domain they are.

ASICS or Application Specific Integrated Circuits:

Department of ECE, SITAMS, CHITTOOR Page 17

SOC or Systems on a chip:

1.3 VLSI DESIGN STYLES

Several design styles can be considered for chip implementation of specified

FIELD PROGRAMMABLE GATE ARRAY (FPGA)

Department of ECE, SITAMS, CHITTOOR Page 18

description of its functionality, using a hardware description language such as VHDL.

GATE ARRAY DESIGN

Department of ECE, SITAMS, CHITTOOR Page 19

STANDARD-CELLS BASED DESIGN

Department of ECE, SITAMS, CHITTOOR Page 20

Department of ECE, SITAMS, CHITTOOR Page 21

 delay time vs. load capacitance

 circuit simulation model

 timing simulation model

 fault simulation model

 cell data for place-and-route, mask data

To enable automated placement of the cells and routing of inter-cell connections,

FULL CUSTOM DESIGN

Department of ECE, SITAMS, CHITTOOR Page 22

Department of ECE, SITAMS, CHITTOOR Page 23

Department of ECE, SITAMS, CHITTOOR Page 22

Department of ECE, SITAMS, CHITTOOR Page 23

Department of ECE, SITAMS, CHITTOOR Page 24