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IRL60B216
Application HEXFET® Power MOSFET
Brushed Motor drive applications
VDSS 60V
BLDC Motor drive applications D
Benefits S
Optimized for Logic Level Drive G
D
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
TO-220AB
Fully Characterized Capacitance and Avalanche SOA
IRL60B216
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free*
RoHS Compliant, Halogen-Free G D S
Gate Drain Source
Standard Pack
Base part number Package Type Orderable Part Number
Form Quantity
IRL60B216 TO-220 Tube 50 IRL60B216
6 315
RDS(on), Drain-to -Source On Resistance (m)
225
ID, Drain Current (A)
TJ = 125°C 180
3
135
2
90
1 TJ = 25°C
45
0 0
2 4 6 8 10 12 14 16 18 20 25 50 75 100 125 150 175
Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A. Note that
Current imitations arising from heating of the device leads may occur with some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.107mH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 1420A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 46A, VGS =10V.
Pulse drain current is limited to 780A by source bonding technology.
8.0V
100 100
100 1.8
TJ = 175°C (Normalized)
TJ = 25°C
10 1.4
1 1.0
VDS = 25V
60µs PULSE WIDTH
0.1 0.6
0 2 4 6
-60 -20 20 60 100 140 180
VGS, Gate-to-Source Voltage (V) TJ , Junction Temperature (°C)
1000000 14
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED ID= 100A
12
VGS, Gate-to-Source Voltage (V)
Crss = Cgd
VDS = 48V
Coss = Cds + Cgd
100000 VDS = 30V
10
C, Capacitance (pF)
VDS= 12V
Ciss 8
10000
Coss 6
Crss
4
1000
100 0
0.1 1 10 100 0 50 100 150 200 250 300 350 400 450
VDS , Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)
100µsec
100
100
Limited by Package
1msec
TJ = 25°C 10
10
1
10msec
1 DC
0.1 Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
0.1 0.01
0.0 0.5 1.0 1.5 2.0 2.5 0.1 1 10
Fig 9. Typical Source-Drain Diode Forward Voltage Fig 10. Maximum Safe Operating Area
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
74 2.0
Id = 2.0mA
1.8
72
1.6
70 1.4
1.2
Energy (µJ)
68
1.0
66
0.8
64 0.6
0.4
62
0.2
60 0.0
-60 -20 20 60 100 140 180 -10 0 10 20 30 40 50 60
TJ , Temperature ( °C )
VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage Fig 12. Typical Coss Stored Energy
4.0
RDS (on), Drain-to -Source On Resistance (m)
VGS = 3.5V
3.5 VGS = 4.0V
VGS = 4.5V
VGS = 8.0V
3.0 VGS = 10V
2.5
2.0
1.5
1.0
0 50 100 150 200
ID, Drain Current (A)
1000
100
10
600
TOP Single Pulse Notes on Repetitive Avalanche Curves , Figures 15, 16:
BOTTOM 1.0% Duty Cycle (For further info, see AN-1005 at www.irf.com)
500 ID = 100A 1.Avalanche failures assumption:
EAR , Avalanche Energy (mJ)
IRRM (A)
1.5
8
1.0 ID = 250µA
ID = 1.0mA
ID = 1.0A 4
0.5
0.0 0
-75 -25 25 75 125 175 0 200 400 600 800 1000
TJ , Temperature ( °C ) diF /dt (A/µs)
Fig 17. Threshold Voltage vs. Temperature Fig 18. Typical Recovery Current vs. dif/dt
20 400
IF = 100A IF = 60A
VR = 51V 350 VR = 51V
16 TJ = 25°C
TJ = 25°C
TJ = 125°C 300 TJ = 125°C
12
QRR (nC)
IRRM (A)
250
200
8
150
4
100
0 50
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)
Fig 19. Typical Recovery Current vs. dif/dt Fig 20. Typical Stored Charge vs. dif/dt
400
IF = 100A
350 VR = 51V
TJ = 25°C
300 TJ = 125°C
QRR (nC)
250
200
150
100
50
0 200 400 600 800 1000
diF /dt (A/µs)
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
20V
tp 0.01 I AS
Fig 23a. Unclamped Inductive Test Circuit Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Fig 25a. Gate Charge Test Circuit Fig 25b. Gate Charge Waveform
EXAM PLE: T H IS IS A N IR F 1 0 1 0
LO T C O D E 1789 IN T E R N A T IO N A L PART NUM BER
ASSEM BLED O N W W 19, 2000 R E C T IF IE R
IN T H E A S S E M B L Y L IN E "C " LO G O
D ATE C O D E
YEA R 0 = 2000
N o t e : "P " in a s s e m b ly lin e p o s it io n ASSEM BLY
in d ic a t e s "L e a d - F r e e " LO T C O D E W EEK 19
L IN E C
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Qualification Information†
Industrial
Qualification Level (per JEDEC JESD47F) ††
Revision History
Date Comments
10/9/2015 Corrected typo on Fig5. Vds from 10V to 25V on page 4.