A 3D stacked nanowire technology -

Applications in advanced CMOS and beyond

T. Ernst, L. Duraffourg, C. Dupré, K. Tachi, E. Bernard, P. Andreucci, V. Maffini-Alvaro,

S. Bécu, E. Ollier, E. Colinet, P. Cherns, A. Hubert, C. Halté, C. Vizioz, S. Barnola,
J. Buckley, O. Thomas, G. Delapierre, V. Delaye, J.-M. Hartmann, M. Cassé, P. Rivallin,
M. A. Jaud, E. Saracco, M. Jublot, B. de Salvo, J.P. Colonna, S .Deleonibus and O. Faynot

CEA/LETI, MINATEC, 17 rue des Martyrs,

38054 Grenoble Cedex 9, France

Contact: thomas.ernst@cea.fr

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copyright: CEA- Leti
 Outline

• Introduction

• Stacking nanowires for MOSFETs and memories

• Sensors

• Conclusion

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Thin films toward 5nm gate length ?
Bulk drain 3D devices

Gate ThinSOI n x dSi

/SON
dSi
sourcet drain
L
Gate
source source
Planar source
t
Double-gates drain
L=5nm Finfet, planar
dSi= 1.25nm Ground plane Gate
dSi Trigate &
source nanowire
dSi
L=5nm
Thin film dSi= 2.5 nm L=5nm
dSi= 5-10 nm
technologies: Gate L
- undoped (low variability) 3
- low IOFF leakage copyright: CEA- Leti
 Nanowire for sub 22nm nodes ?
Si SiGe

CVD nanowires > above IC ?

More than
Moore T. Ernst et al. , N. Singh et al. ,
IEDM06 IEDM06
3D Nanowires
3D Memories
3D 3D stacked devices

Bio detection -
NEMS

3D
Mono electronic

Logic FDSOI Std SOI UTBOX Nanowire

More 22nm 16nm 11nm <11nm

Moore 4
2009 2010 2012 2013 2014 2015 2016
copyright: CEA- Leti
NanowireFET scalability - state of the art
C. Jahan et al, VLSI’05 – 20 x 50 nm trigate 1E-03
V D=1.2V
Lg = 10 nm
Lg = 10 nm 1E-04
1E-05 V D=0.1V

ID (A/µm)
HfO 2 1E-06
TiN
1E-07 SS = 90 mV/V
DIBL=105mV/V
Si 1E-08
1E-09 Lg=10 nm
1E-10
-0.2 0 0.2 0.4 0.6 0.8 1 1.2
V G (V)
K. H. Suk et al. IEDM’06 8x8 nm GAA nanowire

TiN
SiO2

Si

Functional 10nm (IOFF<1nA/µm) gate length ΩFETs with good 5

electrostatic control, even with relaxed diameter and trigate
copyright: configuration
CEA- Leti
Multi-Channel FET - state of the art

M.S. Kim et al. , VLSI 06

Excellent static noise margin

Several technologies for levels separation:
=> Preferential oxidation
=> Wet etching
=> Dry plasma etching or HCl
6
N. Singh et al. ,
IEDM06 copyright: CEA- Leti
 Outline

• Introduction

• Why stacking nanowires for MOSFETs and memories ?

• Sensors and hybrid CMOS

• Conclusion

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Building stacked nanowires
... pitch limitation 3D overbalanced

pitch

TEM

SEM

Use of nanowires limits the available Si surface for conduction

3D Multi-channels: a very efficient approach to increase available surface

Open tunable width and tunable shape possibilities 8
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Tunable width

6
Conductance (a.u.)

5 3 multi W
W
- channels
4 v v
(MC)
3 v
Fin FETs
2 pitch
Planar
1
1 level nanowires
0
0 1 2 1 2
Layout width (a.u.) Layout width
See for details:
T. Ernst et al, IEDM’06,’08 SSDM’07, ICIDT’08 Design flexibility to tune
E. Bernard et al. VLSI’08, ESSDER’07
C. Dupré et al, IEEE SOI Conference 07 the conductance 9
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Internal spacers
TEM L=50nm W=50nm
Cof
0
10

Drain Current, ID (A/µm)

W 10
-1 w/ internal spacers L = 50nm
10
-2 w/o internal spacers TiN/HfO2
-3
Tspacer 10 -1.2V
-4
1.2V
10 VD = 0.05V
-5
10 VD = -0.05V
-6
10 p-MCFET n-MCFET
Cside -7
10 IOFF_w/o= 17pA/µm IOFF_w/o= 16pA/µm
Cox Cov -8
10 IOFF_w/= 38pA/µm IOFF_w/= 27pA/µm
-9
Tgate 10 ION_w/o= 1.32mA/µm ION_w/o= 2.27mA/µm
-10
10 ION_w/= 1.52mA/µm ION_w/= 2.33mA/µm
-11
10
LG/2 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2
Gate Voltage, VG (V)

E. Bernard, N. Vulliet, B. Guillaumot, T. Ernst et al.

VLSI 2008 & Electron Device Letters Feb. 2009

CEA/LETI & STMicroelectronics collaboration on GAA/SON technology

Internal spacers reduce capacitances without impacting

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ION/IOFF current
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CV/I : 3D versus planar
W
Cof
Cof Tgate
Cside TRSD
W versus Cox C
ov Tspacer

LG/2
Tspacer
2.0
Planar FD-SOI reference

Normalized (Cg+Cwire)Vdd/I
Cside MCFET w/ internal spacers
Cox Cov 1.5 MCFET w/o internal spacers
Tgate
LG/2 1.0
L = 50nm
0.5

E. Bernard et al.
IEEE Trans. Elec. Device 0.0 -17 -16 -15 -14 -13
t.b.p., June 2009
10 10 10 10 10
Cwire (F)

Multi-Chanels CV/I outperform planar in a 11

loaded environment copyright: CEA- Leti
Tunable shape for flexible designs
P V =1.2V V =1.2V N
10-2 D D

Drain Current I D (A/µm)

3D-NWFET
10-4 V =50mV V =50mV
D
D
I =6.5mA/µm
10-6 ION=3.3mA/µm ON
I =0.5nA/µm I =27nA/µm
OFF OFF
-8
10 SS=65mV/dec SS=68mV/dec
DIBL=7mV/V DIBL=15mV/V
-10
10 V =-0.62V V =0.53V
T
T

10-12
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Gate Voltage V (V)
G

Flexible process :

- Reduced gate capacitance (spacers)

- Independent gate nanowire (PhiFet)
- Finfet compatible
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- Excellent current drivability due to 3D: 6.5 mA/µm !
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Nanowires with independent gates
Φ-Fet) electrical results
(Φ
10-4
V =0.8 to -1.4V L=550nm V =50mV
D
G2
-6 step = -0.2V
10

Drain Current I D (A)

4T-ΦFET
-8 3T-ΦFET VS
10 4T-FET

. c
/dec.

V/de
VG1 VG2
-10

2mV
10

82m
3T-FET VD

SS=6

SS=
10-12 VG

-14 VD
10
-1 -0.5 0 0.5 1 1.5 2
Gate 1 voltage VG1 (V)

TEM Nanowires with independent gates

allows ultra-low power management
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C. Dupré et al, IEDM 08
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 TEM Step 1
SiGe Si/SiGe
Si
SiGe Epitaxial growth Nanowires
Si < t relaxation
Si
SiGe
critical thickness 3D patterning
Si SiGe
SEM
Box

SEM

Step 2
Fins definitions
Hybrid DUV/e-beam
Triming
etching
⇒High aspect Step 3
ratio SiGe Selective
dry etch (SON)
T. Ernst et al, + thermal treatments
IEDM 06, IEDM 08 14
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Rounding by hydrogen annealing
Line
roughness (3σ) 6.5 nm

5 nm

3.5 nm

No anneal

3D Atomic Force Microscopy 800°C anneal

J. Fouchet, CEA-LETI

850°C anneal 15
E. Dornel et al , Appl. Phys. Lett. 91, 233502 (2007) copyright: CEA- Leti
Nanowires oxidation kinetics
SEM
3.4nm

4.8nm

Bulk - 1100°C - dry

800 NWs - 1100°C - dry
SiO thickness (Å)

Bulk - 950°C - wet

NWs - 950°C - wet
600

400
3,4 nm
2

200

0
0 300 600
Time (s)
900 1200 4.8nm HRTEM
⇒ Self-limited oxidation is used for
small diameter control and variability reduction 16
A. Hubert et al., ECS Trans. 2008 copyright: CEA- Leti
Nanostructuration by oxidation

5nm Ge nanowires

EFTEM (V. Delaye/M. Jublot)

JP Colonna et al. To be published

Complex 3D sub-10 nm
structures can be designed
by (Si/SiGe)n lateral oxidation
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Standard on-line SEM of 10nm
suspended nanowire ...

Accurate in-line
metrology for sub 10 nm
3D structures
is needed
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3D Atomic Force Microscopy

250
Before epitaxy

200
After

Height (nm)
epitaxy
150

100

50

0
-30 -20 -10 0 10 20 30

[J. Foucher et al. SPIE 08] Width (nm)

Systematic and non destructive accurate in line method

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3D nanowires TEM tomography
Rough SiGe nanowires

[P. Cherns al. EMC 08] This conference:

P. Cherns al., POSTER THO21
A. Chabli et al, invited
3D accurate description along the wire,
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including roughness
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3D Flash memories (concept) TEM

T. Ernst et al. , IEDM’08

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 Outline

• Introduction

• Why stacking nanowires for MOSFETs and memories ?

• Sensors and hybrid CMOS

• Conclusion

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Nanowires are introduced for
very sensitive mass measurement

10-9g

10-12g

10-15g

10-18...-21g

10-18...-21 g

Few molecules sensitivity can be achieved => 1zg 23

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Mass units in biology
Atomic mass unity = 1Da = 1 u ≈ 1.66053886 x 10-27kg
Nanowires 1zg = 10-21g = 602 Da ≈ a nucleotides pair (DNA)
NEMS

Parvoviridae
Hemoglobine Protein PrP
viruses:
(Prion) E. Coli bacteria
A-T G-C A molecule Hepatitis B

613.4 Da 66.2 kDa 150 kDa 1.1 MDa 4.2×1011 Da

616.4 Da

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Nanowire used for mass detection

Capacitive actuation & detection Capacitive actuation & piezo-resistive

detection with nanowires Thermo-elastic actuation
& piezo-resistive detection.
15 nm oscillator

Leti

First 200 mm wafers with 3.5 millions NEMS

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CALTECH & LETI VLSI NEMS Alliance
copyright: CEA- Leti
Mass resolution with nanowire

80 nm

He et al.
R. He, M. Roukes et al. Nanoletters 12/08
This work
10 nm

Released nanowire
Mass resolution according to the diameter Bending oscillation
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Nanowire for chemical detection
Buffer solution Buffer solution Buffer solution
at pH<7 at 7<pH<10 at pH>10

n-doped Si Metal Passivation Hole Electron

130
pH 2
120
Conductance (nS)

110 pH 3
100
pH 4
90
pH 5
pH 6
80
pH 7
70

60
0 2000 4000 6000 8000 10000 12000

Time (s)

Change of Si nanowire conductance according to pH 27

copyright: CEA- Leti
Summary
• Several methods were presented to overcome some difficulties linked to
3D structures:

- self-gate alignment
- internal spacers
- diameter control (oxidation …)
- VT modulation/power management (by independent gates…)

• Nanowire should be seen as a natural scaling of thin film technologies and

not as a one “ever ultimate” node or technology.

• New 3D nanowires matrices offer an original solution for lithography pitch

limitation => possible applications to memories and CMOS

• There is a convergence between thin film nanowire CMOS and sensors

technologies which open new applications opportunities.

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 Acknowledgements
A part of this work is performed as part of the
IBM-STMicroelectronics-CEA/LETI-MINATEC Development Alliance

A part of this work is performed within

CALTECH/LETI NEMS VLSI Alliance

Dr. T. Skotnicki, N. Vulliet and B. Guillaumot from STMicroelectronics are thanks

for intensive and fruitful collaborations on SON and GAA CMOS technologies

Many thanks for fruitful collaborations on nanowires to:

Pr. M. Roukes (Caltech)

Pr. G. Ghibaudo, S. Cristoloveanu and M. Mouis (IMEP/CNRS, Minatec, France)
Pr. I. Iwai (Tokyo Institute of Technology)
Pr. P. Wong (Stanford)
Pr. C. Bonafos (CEMES/CNRS, Toulouse, France,)
Pr. A. Ionescu (EPFL, Lausanne, Switzerland)
Dr. T. Baron, B. Salem (LTM/CNRS, Minatec, Grenoble , France)

NEMSIC European Project

NANOSIL European Network
RTRA-Core

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For further information on this work
Barnola, S., C. Vizioz, et al. (2008). "Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications." ECS Transactions
16(10): 923-934.

Bernard, E., T. Ernst, et al. (2009). "Multi-Channel Field-Effect Transistor (MCFET)-Part I: Electrical Performance and Current Gain
Analysis." Electron Devices, IEEE Transactions on 56(6): 1243-1251.

Bernard, E., T. Ernst, et al. (2009). "Multi-Channel Field-Effect Transistor (MCFET)-Part II: Analysis of Gate Stack and Series Resistance
Influence on the MCFET Performance." Electron Devices, IEEE Transactions on 56(6): 1252-1261.

Bernard, E., T. Ernst, et al. (2008). "Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on
SOI." Solid-State Electronics 52(9): 1297-1302.

Dornel, E., T. Ernst, et al. (2007). "Hydrogen annealing of arrays of planar and vertically stacked Si nanowires." Applied Physics Letters
91(23): 233502-3.

Dupre, C., T. Ernst, et al. (2008). A mobility extraction method for 3D multichannel devices. Solid-State Device Research Conference,
2008. ESSDERC 2008. 38th European.

Dupré, C., T. Ernst, et al. (2009). "Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET)."
Solid-State Electronics In Press, Corrected Proof.

Dupre, C., A. Hubert, et al. (2008). 15nm-diameter 3D stacked nanowires with independent gates operation: Phi-FET. Electron Devices
Meeting, 2008. IEDM 2008. IEEE International.

Ernst, T., C. Dupre, et al. (2006). Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs
with HfO2/TiN gate stack. Electron Devices Meeting, 2006. IEDM '06. International.

Ernst, T., L. Duraffourg, et al. (2008). Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid
integration? Electron Devices Meeting, 2008. IEDM 2008. IEEE International.

Ernst, T., R. Ritzenthaler, et al. (2007). "A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs." Electron
Devices, IEEE Transactions on 54(6): 1366-1375.

Hartmann, J. M., F. Andrieu, et al. (2008). "Reduced Pressure-Chemical Vapour Deposition of Si/SiGe heterostructures for
nanoelectronics." Materials Science and Engineering: B 154-155: 76-84.

Ollier, E., P. Andreucci, et al. (2008). NEMS based on top-down technologies: from stand-alone NEMS to VLSI NEMS Electron Devices
and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on.

Wacquez, R., P. Coronel, et al. (2007). A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar 30
Double-Gate Transistors for 32nm Node And Below. Solid State Devices and Materials (SSDM), Tsukuba (Japan), japan Society of
Applied Physics. copyright: CEA- Leti