6

PLDs and Memnories

INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES (PLDS)
Awide range of standard ICS are available in the market with a large number of logic
functions and logic arrangements in a chip. Inspite of the ease in availability of the numerous
type of TCS with large number of function on the chip, some design require hundreds and
thousands of such ICS to be interconnected. This large number inter connections of ICS have
inherent difficulties. For example a large circuit board space is required and cost of testing and
soldering are high. The development of PLDs has come out with the solution to replace a large
number of ICs with a single IC. APLD is an IChaving alarge number of gates, FFs and
registers internally interconnected on the chip. These connections are in the form of
programmable fuses. The devices are programmable as few of the fuses can be broken selectively
and others can be made intact. Even the users can blow the fuses as per the functions'
requirement. This process is called programming.
Basically PLD consists of 2 types of arrays
an array of AND gates for AND logic and
an array of OR gates for OR logic.
These arrays are programmably inter connected to produce the desired logic functions. The
AND array produces product terms where as the OR array produces the sum of these product
terms. We can program AND and OR array to get any desired function. Once all of the outputs
have been programmed, the device will permanently generate the selected output functions.
6.1. PROGRAMMABLE LOGICARRAYS (PLA)
The implementation of logic function plays a key role in the design of digital system. One
of the method in implementing the logic functions is to use a PLA. APLA with 'n' inputs and 'm'
outputs can realize m functions of n variables. In this we use two arrays. 1. AND array 2. OR
array. Both are programmable.

PLA

n input AND OR
lines Array Array

k word lines

m output lines

Fig. 6.0. Programmable logic array structure.

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VLSI DESIGN
The Fig. 6.1.2 (a). Shows NMOS PLA
From 3inputs we get complemented and architecture. It has 3 input line and 4 output lines,
to AND line through fuses and NMOS uncomplemented form. The input lines are connected
1,otherwise it is closed. Drain is PLA. NMOS PLA is open only when its gate is
given with
connected to V* and source is connected to Gnd. If the
series with gate is blown off then the fuse in
corresponding input has no effect on AND line. When
fuse is intact the input has effect on AND the
the AND line to OFF. Next if input is '0, line. For e.g. if input is 1,the NMOS is ON, it will pull
This is similar to a NOR operation. To haveNMOS is OFF. So A 1' is sent through the AND line.
inputs. This will function as an AND AND function from NOR we insert an
gate. inverter at all
A
A B A
B
B

A
A
C
o o AC

Fo=A B+ AG
Fig. 6.1.2 (b) AND-OR from
NOR-NOR.
Similarly for OR array also we
points of input line and product line.haveHere
one NMOS in series with fuse at all the
its operation is similar as beforeintersecting
exhibits a NOR function. At the output we putalso one inverter to get OR function, from and it also
is the desired one. So the NOR which
required AND OR combination is obtained.
The Fig. 6.1.2 (a) shows
terms and 4 outputs. It can be unprogrammed NMOS PLA structure having 3inputs, 5 product
series with NMOS. When fuses are programmed by blowing the corresponding fuses which is in
link is intact output depends on blown link is cut and input has no effect on output. When
The following e.g. Explains corresponding input.
how logic functionscan be realised using
e.g. Realise using NMOS PLA the
following :
NMOSPLA.
F,= Em0, 1, 4, 6), F, = Em(2, 3, 4, 6, 1), F,=
}m(0, 1, 2,6), F, = Zm(2, 3, 5, 6, 7)
Fo= Em (0, 1, 4, 6)
F, = Em(2, 3, 4, 6, 7)
AB AB+CA AB B+CA
00 01 11 10 C 00 01 11 10
1
1 1
1 1
1
1
1
1
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PLDs AND MEMORIES

F, = Em (2, 3, 5,6, 7)
F, = Em (0, 1, 2, 6) B+CA
AB+CB AB
11 10
AB 00 01
11 10
00 01

1 1

1
1

1
1 1
1

Fig. 6.1.3 (a) Karnaugh map.

6.1.3 (b) PLA Table
Outputs
Product terms
F, F,
AB F, F,
AC F,
B
BC F,
AC
F,=B+ CA
F, = AB + CA
F, = B+CA
F, = AB + CB
Inputs

V+

V+
AB
Produt
terme
A

BC

AC

X
[F=B+AC

=AB+CB
F, -B
F,+AC

Outputs
 VLSI DESIGN
200

R-r
5 product terms and 4 outputs.
Fig. 6.1.4. Programmed PLA with 3 inputs,
both AND array and OR array are programmable. Wherever we want a connection,
In this circuit
fuses and others are disconnected from the
the particular NMOS is made intact using the
by blowing the fuses off. But, using NMOS we can realize only NOR function. In order to get
OR function all outputs are inverted.
AND function all inputs are inverted. Similarly to get
6.2. PAL AND PLDs
generating product terms
We have different kinds of PLDs. All have one AND array for
and one OR array for generating SOP terms.
In architecture
"-> Denotes hardwired
X-> Denotes fuse intact.
6.2.1. PLD PROM
In this AND array is hard wired and OR array is programmable. Let us consider a PROM
in such a
with 3 inputs, 8 product terms and 4 outputs. Here as AND array is hard wired
manner that each of the 8 AND gates will generate each one of all the possible combination of
inputs. This finds its application where all combinations of input variables are required for
producing output functions. e.g. code converters and data storage table.
PLDs AND MEMORIES 201

Inputs
A B C

OR Aray programmable

A A B B C
AND Array hard wired

Fig. 6.2.1 (a) PROM architecture.

Inputs
A B

OR ATay programmed

A
A B B cc
AND Aray hard wired

Fig. 6.2.1 (6) Programmed PROM.

the unwanted
desired inputs or product terms for OR inputs can be got by blowing has no effect
The on input. When the link isopen input
depends
links.When the link is intact output
on output.
 202 VLSI DESIGN
For example, if we want to realize
O, = ABC + AB = ABC + ABC+ AB C
0, = ABC+ AC = ABC + ACB + ACB
0 = 1[comprises of all8 input combinations)
0, = ABC + ABC
Then the PROM can be programmed as shown in Fig. 6.2.1 (6).
6.2.2. PAL - Programmable Array Logic
In this AND array is programmable and OR array is Hard wired. It is used in applications
where we don't require all the possible combination of inputs to generate output.
Inputs
A B

OR Array hard wired

A A B BC
AND Array programmable

O,
Fig. 6.2.2 (a) PAL architecture.
Here we can see that each OR gate has only 4 inputs. So a
product terms cannot be realized using this. But if we requirefunction requiring more than 4
less than 4 product terms for
output, then the unwanted one can be made 0.
For example, suppose we want to realize.
0, = ABC+ ABC
0, = ABC+ ABC+ ABC + ABC
0, = ABC + ABC
0, = ABC + A BC
DAND MEMOKIEN 203

The above quntions can be progrnmmed as shown in figure below :

Inputs

O Anay havd wlred

ABC

ABC

ABC

ABC

ABC

A BC

A A D C C

AND Array programned

Piy. 6.2.2 (b) Progranmed PAL.

want to have 0' product term, all the fuses at the input ofAND gates should be
Hero if we
0
made intact as AA.B B.CC
6.3. FOLDED PLAN
standard PLA is called a folded PLA. The folded PLA is used under
T'he improved form of
the following conditions.
product terms available in SOP equations should be functions of disjoint sets
1. The diforent BC...Jare
following example. The product terms of 0,,0,, 0,IABC,A
of input variable. In the and C, whereas the product terms of 0,, 0, are functions of D,
functions of input variables A, B for two
disjoint input sets can be spatially sogregated. So, it is pOssible
Also inputs
E and F only. Now the their complements to share the same ANDplane columns,
distinct input terms and Similarly EB and CF also. Now the width ofPLA is reduced
column. folding.
A,D sharesame AND planenumber of AND plane columns. This is called AND plane
because of the reduction in be functions of disjoint sets of product terms.
should
2. Thedifferent output terms of product terms A BC, A BC,output A B.
functions
0,, 0,, 0, are sogregated. So, it is possible for two distinct
In the Example outputs can be spatially and is known as OR
"These disjoint product terms plane column. This reduces the width of PLAthe folding of diferent
OR
terms to share the sameoperations reduces the area required by PLA. But
planefolding. Also these
 VLSI DESIGN
204

interact and it is difficult to get optimal PLA folding. HeuristicS are nornnally
groupsof variables
used to find a good folded structure for a PLA. implemented.
following e.g. illustrates how folded PLA structure can be
The be output terms.
0,, 0,, 0,, 0,
Lat A,B,C,D,E,F be input variables and 0,, 0,,
Let
0, = ABC+ ABC+ ABC + ABC
0, = AB+ BC + AC
0, = A B + AB

0, = DE + DE
0, = DEF +DE F
0, = ABC+ DEF+ DE
using standard PLA it requires 6 input columns (if complement
For implementing this columns.) 13 product terms and6 output columns.
See
terms are included it requires 12 input columns.
6.3.1Whereas folded PLA requires only 3 input columns and four output
Fig.
OR Plane
AND Plane
DEF

DEF

DE

DE

AB

" AB

" AC

" BC

AB

ABC

" A BC
" ABC

" AB C

A A B B CC D DE E F F 01 02 03 04 05 06

Fig. 6.3.1 Standard PLA implementation (6, 13, 6).

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PLDs AND MEMORIES
AND Plane OR Plane

D D E E F F DEF
X " X X
DEF
X" X X

DE
X X

X X DE
AB

AB

A C

" BC

AB

A BC

ABC
ABC

ABC

A B B 01 02 03 04 05 06
A

(3, 13, 6).

Fig. 6.3.2 Folded AND -plane PLA implemnentation
AND Plane OR Plane

D DE E F F 04 05
X " X X X DEF

X X X DEF
X "

X X " X DE

X " X X DE

AB

AB

AC

BC

AB

ABC

" ABC

" AB C

ABC

A B B CC 01 02 03 06
A
13, 4).
Fig. 6.3.3Both AND and OR plane folded PLA implementation (3,