Professional Documents
Culture Documents
CHP 4 - Field Effect Transistor
CHP 4 - Field Effect Transistor
1/63
ELECTRONIC DEVICES
CHAPTER 4
Terminals C, B, E D, G, S
Digital ICs
Typical Analog amplifiers
High current and high speed
applications Discrete analog circuits
switching elements
IV.4/63
Contents
1. Junction FET
2. Metal Oxide Semiconductor FET
IV.5/63
1 - Junction FET
N-channel P-channel
IV.8/63
1.1 Structure and basic operation
N-channel JFET
biasing
IV.9/63
1.1 Structure and basic operation
Consider an example:
N-channel JFET with
UGS ≤ 0 and UDS > 0
– First:
• Fix: UGS = 0
• Change: UDS > 0
Phenomenon:
• G-S is reversed-biased,
hence IG = 0.
• A thin depletion region is
produced along the P-N
junction.
• The channel is a ohmic
conductor.
IV.10/63
1.1 Structure and basic operation
– When UDS increased
differences among
voltages along the
channel increase.
Phenomenon:
• The depletion region is
gradually extended.
• Wider depletion region,
lower channel
conductivity channel
becomes “non-ohmic”.
• Always: IG = 0
IV.11/63
1.1 Structure and basic operation
– When UDS is high enough (= UP) the channel is “pinched”
and ID reaches maximum value.
UP is called “pinch-off voltage”.
– When UDS ≥ UP ID = constant
IV.12/63
1.1 Structure and basic operation
– Second:
• Fix: UGS < 0
• Change: UDS > 0
Phenomenon:
• The reversed voltage of the P-N
junction is “added” an amount =
|UGS| channel is “pinched”
earlier (UDS < UP).
• More negative value of UGS
channel is pinched faster the
saturation of ID is smaller.
• When UGS = UGS(off) = −UP the
channel is pinched regardless the
value of UDS.
Transfer characteristic:
– Presents the relation between UGS
and ID (UGS controls ID).
– Can be plotted based on 4 special
points as in the figure.
– Can also be developed from the
drain characteristic curves by
plotting values of ID for the values
of UGS taken from the family of
drain curves (see next page).
IV.18/63
1.2 Characteristic curves of JFET
IV.19/63
1.3 Shockley equation and transconductance
Forward transconductance: gm
ID
gm
UGS
2IDSS
gm0
UGS ( off )
IV.22/63
1.4 JFET biasing
The nature of work: creating a negative value of
UGS to pinch the channel ID is saturated and
ready for being controlled.
There are 3 types of bias:
– Fixed-bias
– Self-bias
– Voltage-divider bias
In each type, we must consider:
– Position of the Q-point.
– The stability of the Q-point when parameters (IDSS, UP,
gm) of JFET vary.
– A good bias circuit: IDQ is highly stable
IV.23/63
1.4 JFET biasing
Note: the stability of the bias
circuit is very important
because the transfer
characteristic of a JFET can
differ considerably from one
device to another of the
same type.
E.g., 2N5459:
– IDSS: 4 ÷ 16 (mA)
– UGS(off): −2 ÷ −4 (V)
UGS
UP UGSQ = EGS
Self-bias:
• Q-point can be
determined by using the ID
transfer characteristic
IDSS
Q is the intersection of the
transfer characteristic curve and
the line UGS = − ID.RS
Q IDQ
• Stability of Q-point:
relatively good …?
UGS
UP UGSQ = EGS
IV.28/63
1.4 JFET biasing
+EDS
Voltage-divider bias:
– UGS is created by the voltage-divider and
the dropout on RS. ID RD
R1
Q-point: D
• VG = EDS.R2/(R1 + R2) (because IG = 0)
• VS = IS.RS = ID.RS IP G
UGS = VG – ID.RS
S
• Combined with the Shockley equation UGS
R2
a quadratic equation of UGS there are RS
2 solutions choose |UGS| < |UP|
IS
UDSQ = EDS – IDQ.(RD + RS)
Voltage-divider bias:
• Stability of Q-point: good …?
ID
IDSS
Q is the intersection
of the transfer
characteristic curve Q IDQ
and the line
UGS = VG − ID.RS
UGS
UP UGSQ VG
IV.30/63
1.4 JFET biasing
+EDS
+EDS +EDS
RD ID RD ID RD
D D R1
D
G G
IP G
RG S
UGS S S
UGS UGS
EGS - RG R2
RS RS
+
IS IS
IV.31/63
1.5 Parameters and datasheets
1. Junction FET
2. Metal Oxide Semiconductor FET
IV.33/63
2 - Metal Oxide Semiconductor FET
E-MOSFET:
Actual E-MOSFETs:
Symbol IRF540 (N-channel) and
IRF9540 (P-channel)
B and S is
connected
IV.37/63
2.1 Structure and basic operation
D-MOSFET:
– Differences from E-MOSFET: there is a conduction
channel between D and S
– D-MOSFET can operate in both enhancement-
mode and depletion-mode
N-channel P-channel
D-MOSFET D-MOSFET
IV.38/63
2.1 Structure and basic operation
D-MOSFET:
Actual D-MOSFET:
Symbol IXTP01N100D
IV.39/63
2.1 Structure and basic operation
For proper operation, MOSFET need to be biased.
For N-channel E-MOSFET: UGS > 0
– A positive gate voltage (above a threshold value) induces
a channel by creating a thin layer of negative charges in
the substrate region adjacent to the SiO2 layer
IV.40/63
2.1 Structure and basic operation
N-channel E-MOSFET :
– When UDS increases, the
channel becomes smaller.
– The channel is pinched-
off when UDS is high
enough ID is saturated
– The higher UGS the
thicker channel the
larger ID UGS can
control the saturation
value of ID
– IDSS is the leakage current
very small
IV.41/63
2.1 Structure and basic operation
Depletion-mode Enhancement-
(commonly used) mode
IV.42/63
2.1 Structure and basic operation
N-channel D-MOSFET :
– The narrow channel connects D and S the operation is similar
to JFET and the E-MOSFET in which the channel is induced
• When UDS increases, the channel becomes smaller.
• The channel is pinched-off when UDS is high enough ID is saturated
• The higher UGS the thicker channel the larger ID
UGS can control the saturation value of ID.
– Operation mode:
• Enhancement: UGS > 0 channel becomes thicker ID(max) > IDSS
• UGS = 0 ID(max) = IDSS
• Depletion: UGS < 0 channel becomes thinner ID(max) < IDSS
– Similar to JFET, when UGS = UGS(off) the channel is totally
depleted and ID = 0 regardless the value of UDS
IV.43/63
2.2 Characteristic curves of MOSFET
E-MOSFET:
Transfer Drain
characteristic characteristic
IV.45/63
2.2 Characteristic curves of MOSFET
E-MOSFET
IV.46/63
2.2 Characteristic curves of MOSFET
D-MOSFET
Enhancement-mode
Depletion Enhan-
cement
Depletion-mode
Transfer Drain
characteristic characteristic
IV.47/63
2.3 Shockley equation and transconductance
E-MOSFET: (on)
2
ID k UGS UT (on)
+EDS
RD
N-channel
D-MOSFET D
N-channel
G E-MOSFET
RG S
UGS
EGS
EGS must
EGS can be
be ≥ UT
<, =, > 0
IV.51/63
2.4 MOSFET biasing
Fixed-bias:
– Q-point can be determined by using the transfer
characteristic.
ID ID
N-channel
D-MOSFET N-channel
Q IDQ Q E-MOSFET
IDQ
UGS UGS
UP UGSQ = EGS UT UGSQ = EGS
IV.52/63
2.4 MOSFET biasing
+EDS
Self-bias:
ID RD
– Not applicable for E-MOSFET
D
• VG = 0 (because IG = 0)
• VS = IS.RS = ID.RS
G
UGS = − ID.RS
• Combined with the Shockley S
equation a quadratic equation of UGS
RG
UGS there are 2 solutions RS
choose |UGS| < |UP| IS
Self-bias:
– Q-point determination using transfer characteristic.
ID
UGS
UP UGSQ
IV.54/63
2.4 MOSFET biasing
Voltage-divider bias:
+EDS +EDS
ID RD ID RD
N-channel R1 R1
D-MOSFET D D N-channel
E-MOSFET
IP G IP G
S S
UGS UGS
R2 R2
RS RS
IS IS
IV.55/63
2.4 MOSFET biasing
Voltage-divider bias:
• VG = EDS.R2/(R1 + R2) (because IG = 0)
• VS = IS.RS = ID.RS
UGS = VG – ID.RS
• In case of D-MOSFET: see JFET
• In case of E-MOSFET:
ID = k.(UGS – UT)2 combined with UGS = VG – ID.RS a quadratic
equation of UGS there are 2 solutions choose |UGS| < |UP|
Voltage-divider bias:
– Q-point determination using transfer characteristic.
ID ID
IDSS
Q IDQ
IDQ Q
UGS UGS
UP UGSQ UG UT UGSQ UG
Drain-feedback bias:
– Q-point determination using transfer characteristic.
ID
UGS
UGSQ EDS
IV.59/63
2.4 MOSFET biasing
Voltage-divider Drain-feedback
Fixed-bias Self-bias
bias bias
+EDS +EDS
RD
ID RD
D
+EDS R1
D +EDS
G
ID RD IP G ID RD
RG S D S
UGS
R2
UGS D
EGS RS
G IS D-MF RG
D-MF
S
+EDS UGS +EDS G
RG
RD RS
E-MF E-MF ID RD
D IS R1 UGS
D S
G
IP G
RG S
UGS S
UGS
EGS R2
RS
D-MF IS E-MF
IV.60/63
2.5 - Parameters and datasheets
Similar to the other semiconductor components,
MOSFET has some maximum rating: ID(max),
UDS(max), UGS(max), PD(max), …
Dedicated parameters:
– gm: transconductance
– ID(on), RDS(on): drain current and channel resistance (in a
specific condition).
– CGS, CGD: parasitic capacitances
E-MOSFET D-MOSFET
UT: threshold voltage UGS(off): channel cutoff voltage
Note: Static electricity applied to the gate of MOSFET can destroy gate oxide layer
MOSFET needs to be handled with care
IV.61/63
2.6 Complementary MOS
Complementary MOS = CMOS = combination
among N-channel and P-channel E-MOSFETs.
Advantages: low power consumption, high-speed
switching, high-density, high most commonly-used
technology for digital ICs.
IV.62/63
Summary
Studied
– Junction FET (JFET)
– Metal Oxide Semiconductor FET (MOSFET)