ESC201T : Introduction to

Electronics

Lecture 39: Sequential circuit design-3

B. Mazhari
Dept. of EE, IIT Kanpur
Sequential Circuits: Summary

0/0

SO

1/0 1/0
0/0 S1

0/0
S2 1/0

0/0 1/1
S3

•we need to know how the system goes from one state
to another in response to the inputs and how the
outputs respond to these changes
Synthesis involves the following tasks:

0/0

 Number of storage elements SO

1/0 1/0
 State Encoding 0/0 S1

0/0
 Choosing a flipflop type to 1/0
S2
implement states
0/0 1/1

 Synthesize next state logic S3

 Synthesize output logic

Counters
A B C
A
0 0 0
B
clk 0 0 1
C 0 1 0
0 1 1
S0 S1 S2 S3 1 0 0
1 0 1
S7 S6 S5 S4 1 1 0
1 1 1
In state S0, the output ABC is 000, in S1 001 and so on

There are 8 states so 3 FFs are at least required. Let us choose T FF.
000 001 010 011

TA QA
111 110 101 100

TB QB
NS logic
PS NS
A B C A B C TA TB TC
0 0 0 0 0 1 0 0 1 TC QC
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1 clk
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1 TA  B.C ; TB  C ; TC  1
1 1 1 0 0 0 1 1 1
Binary UP counter

B
clk
TA QA
C

A B C
TB QB
0 0 0
0 0 1
0 1 0
0 1 1 1 TC QC
1 0 0
1 0 1
clk
1 1 0
1 1 1
TA  B.C ; TB  C ; TC  1
Counter with Enable

0
TA QA

EN A

B 0
clk TB QB
C

0
1 TC QC

Counter is in Hold state. 0

Enable clk

When Enable = 1, the counter begins the count.

Counter with Asynchronous Reset

TA QA
EN A

B
clk
TB QB
R C

1 TC QC

Enable clk

Reset

When Enable = 1, the counter begins the count.

 -D toggles every clock cycle
-B toggles only when D is 1
ABCD -C toggles only when both C and D are 1
0 0 00 -A toggles only when B C D are 1
0 0 01
0 0 10 T FF toggles when T=1 BCD
0 0 11 TA QA
0 1 00
0 1 01
0 1 10
0 1 11 TB QB
1 0 00 CD
1 0 01
1 0 10
1 0 11 D
TC QC
1 1 00
1 1 01
1 1 10
1 1 11 1 TD QD
0 0 00
clk
4-bit Down Counter -D toggles every clock cycle
-C toggles only when D is 0
ABCD
-B toggles only when both C and D are 0
1111 -A toggles only when D C B are 0
1110
1101
1100 TA QA
1011
1010 QA
1001
1000 TB QB
0111
0110 QB
0101
0100 TC QC
0011
0010 QC
0001
0000 1 TD QD
1111
clk QD
Counters

A B C D
A B C
0 0 0 0
1 1 1 0 0 0 1 A B C
1 1 0 0 0 1 0 0 0 0
1 0 1 0 0 1 1 0 0 1
1 0 0 0 1 0 0 0 1 0
0 1 1 0 1 0 1 0 1 1
0 1 0 01 1 0 1 0 0
0 0 1 0 1 1 1
0 0 0 1 0 0 0 Modulo-5 Counter
1 0 0 1
Binary down counter Decade counter
Modulo-10 Counter
4-bit Up-Down Counter

TA QA TA QA

QA

TB QB TB QB

QB

TC QC TC QC

QC

1 1 TD QD
TD QD
U/D
clk U/D clk QD

Merging of the two structures gives an Up/down counter

BCD Counter

Binary Coded Decimal (BCD): each decimal digit is coded as a 4-bit binary number

25 = 0010 0101

A B C D Y
0 0 0 0 0

0 0 0 1 0
0 0 1 0 0 BCD Counter BCD Counter
0 0 1 1 Output Y Output Y
Count Enable

0 Count Enable
0 1 0 0
0 1 0 1 0

01 1 0 0
0 1 1 1
0
1 0 0 0
1
1 0 0 1
BCD counter from 0 to 99

0 0 1 0 0 0 0 0

0 0 0 1 1 0 0 1

0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 1

0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0

0 1 1
BCD Counter BCD Counter
Count Enable
Output Y Output Y
Count Enable
Counter with Unused States

PS NS
A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X

There are two unused states 011 and 111. one approach to handle this
situation is that, while evaluating expressions for J K , we use don’t care
conditions corresponding to these unused states
Counter with Unused States

PS NS
A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X

BC
A 00 01 11 10
0 0 0 X 1
JA = B
1 X X X X
Counter with Unused States
PS NS
A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X

JA  B KA  B
JB  C KB  1
JC  B KC  1

After synthesizing the circuit, one needs to check that if by chance the counter goes
into one of the unused states, after one or more clock cycles, it enters a used state
and then remains among the used states
 1
J Q A
1 0 000 111
1
K

001 110
1
J Q B
1 0
1 K Q 101
010

100 011
0 J Q C
1 0
clk
1 K

We can see that if by chance the counter goes into unused states 111 or 011,
then after a clock cycle it enters one of the used states.
Counter as frequency divider A B C
0 0 0
0 0 1
A
0 1 0
0 1 1
B
clk 1 0 0
C 1 0 1
1 1 0
1 1 1

Clock f

C f/2

f/4
B

A f/8
Example From a frequency of 10KHz, generate the following signal of frequency 1KHz

Clock

0 0 0 0 0 1 1 1 1 1

A B C D
0 0 0 0
0 0 0 1
0 0 1 0
This will have a frequency of 1KHz but it will not
0 0 1 1 have the same waveform
0 1 0 0
0 1 0 1
01 1 0
0 1 1 1
1 0 0 0
1 0 0 1
Example From a frequency of 10KHz, generate a signal of frequency 1KHz

Clock

0 0 0 0 0 1 1 1 1 1

A B C
1 1 1 1 0
0 0 0 0 0 0 0 0 0
0 0 1
1 1 1 1
0 1 0 0 0 0 0 0 0 0
0 1 1
1
1 0 0 0 0 0 0 0 0 0 0 1 0

The idea is to generate a divide by 5 counter first and then divide it again by 2 to get the
required waveform
 Modulo 5
A T Z

B
clk clk
C

1 1 1 1 0
0 0 0 0 0 0

1 1 1 1
0 0 0 0 0 0 0

1
0 0 0 0 0 0 0 0 1 0
 Clock

Alternatively design a divide by 10 counter with the following states

A B C D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
Example From a frequency of 10KHz, generate the following signal of frequency 2KHz

Clock

0 0 1 1 1 0 0

A divide by 5 counter is required that has 5 states.

A B C A B C
0 0 0 0 0 0
0 0 1 Modify 0 0 1
0 1 0 1 1 0
0 1 1 1 1 1
1 0 0 1 0 0

A will give the required waveform.

Ring Counter

T3 T2 T1 T0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
Alternative Implementation

1000
T0 T1 T2 T3 0100
0010
0001
2:4 decoder

2-bit Counter 00
count enable 01
10
11
Ripple Counter
1 T A0

T FF toggles when T = 1; otherwise Hold state

count

Clock is negative edge Triggered

1 T A1

1 T A2

1 T A3
Ripple Counter
0 1 2 3 4 5 ------15

1 T A0 0 1 0 1 0 1 ------1 0

count

0 0 1 1 0 0 ------1 0
1 T A1

0 0 0 0 1 1 ------1 0
1 T A2

1 T A3 0 0 0 0 0 0 ------1 0
Ripple Down Counter

1 T A0 0 1 0

count A0

1 T A1
0 1 1

A1

1 T A2 0 1 1

A2

1 T A3 0 1 1

A3
BCD Ripple Counter
1 J AO
count c
1 K
A 3 A 2 A 1 A0
0 0 0 0
J A1
0 0 0 1 c
0 0 1 0 1 K

0 0 1 1
0 1 0 0 1 J A2
c
0 1 0 1
1 K
01 1 0
0 1 1 1 J A3
1 0 0 0 c
1 K A3
1 0 0 1
BCD Ripple Counter
1 T Q A0

count
A 3 A 2 A 1 A0
0 0 0 0 T Q A1

0 0 0 1
0 0 1 0
0 0 1 1
1 T Q A2
0 1 0 0
0 1 0 1
01 1 0
0 1 1 1 A1
A2 T Q A3
1 0 0 0
A3
1 0 0 1 Q
Cascading of BCD counters

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1

BCD Counter BCD Counter BCD Counter Count pulses

2 1 0
10 digit 10 digit 10 digit