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Simulation methodology and flow

integration for 3D IC stress
management
Xiaopeng Xu, Vinay Dasarapu
IEEE Custom Integrated Circuits Conference 2010

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 Simulation Methodology and Flow Integration
for 3D IC Stress Management
Mark Nakamoto1, Riko Radojcic1, Wei Zhao1,
Vinay K. Dasarapu2, Aditya P. Karmarkar2 and Xiaopeng Xu3
1
Qualcomm, Inc., San Diego, CA, USA
2
Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India
3
Synopsys, Inc., Mountain View, CA, USA

Abstract—a new methodology to bridge package and silicon

domain simulations is demonstrated using a new data file to Tier 2 Die Underfill ƒ Tier 1 : CMOS SoC
facilitate stress information exchange. The flow integration uses ~ 100’s um ~ low 10’s um ƒ TSV
u-Bump ƒ Very thin wafer
equivalent stress conditions to replace sensitive process Tier 2 FEOL Size ~ 10’s um
information and parameterized modules to minimize user ~ 1’s um ƒ Interface u-Bump
Pitch ~ 10’s um
ƒ Backside metal
interventions for 3D IC stress simulations. Back Metal ƒ Interface to u-Bump
Width ~ 1’s um ƒ TSV/u-Bump offset
Pitch ~ 10’s um
ƒ U-Bump
Keywords— Through-silicon via (TSV), mechanical stress, Tier 1 Die ƒ Very thin underfill
~ 10’s um ƒ Tier 2 : Memory/Analog
layout proximity, performance variation, reliability, modeling
Underfill TSV ƒ Regular die
~ hi 10’s um Size ~ 1’s um ƒ Frontside metal
I. INTRODUCTION Pitch ~ 10’s um ƒ Package Bump
Package Bump Tier 1 FEOL ƒ Regular flip chip bump
Three dimensional (3D) integration technologies use Size ~ 100’s um ~ 1’s um ƒ Regular underfill
Pitch ~ 100’s um
through silicon vias (TSVs) to link silicon dies that are ƒ Package
Package Substrate
encapsulated in a package, as shown in Fig. 1. New processes ~ 100’s um ~mm ƒ Regular substrate
ƒ Regular plastic potting
for 3D IC integration introduce mechanical stresses not only
in silicon active regions but also in interconnect and package Fig. 1 Schematic of the 3D TSV chip stacking architecture.
structures[1][2]. Mechanical Stress modulates the transistor
performance and also compromises the structural integrity and Strained silicon methods have played a major role in recent
reliability. These concerns are not addressed in the existing generations of CMOS technology.
modeling methodologies and design flows. Currently The advent of 3D integration has significantly increased the
mechanical stress is managed independently in the silicon and level of interaction between the silicon and the packaging
package domains. The lack of a methodology that bridges domains. Existing features and factors such as soft low-
silicon and package domains imposes a severe constraint for dielectrics, strained silicon and CTE mismatch with packaging
3D IC stress management. For silicon domain stress analysis, material will now interact with new 3D features and processes.
designers face additional modeling constraints, since Dies thinned to 10s of m will be much more susceptible to
conventional TCAD simulation requires detailed process bending or warpage due to the normal BEOL film stack and
information not accessible to fab-less companies. Apart from packaging stresses. These will also interact with new features
these constraints, the complex 3D multi-disciplinary nature of such as TSVs, -bumps and other dies in the 3D stack [4].
the problem requires robust and easy to use simulation One example is a -bump connection between two dies that
methodology. In this paper, innovative techniques are would normally be simulated in the package modeling realm
employed to overcome these constraints and a modeling as shown in Fig. 2 (a); where the force is usually not high
framework is developed for 3D TSV stress analysis with enough to cause reliability concerns. However, when the
parameterized geometry and mesh generation modules. mechanical stress from this “packaging” effect is transferred
to the silicon simulation domain, the impact of stress on the
II. BRIDGING PACKAGING AND SILICON
silicon performance is evident from the mobility change
Traditionally mechanical stress modeling for packaging and shown in Fig. 2 (b).
silicon has been performed as two distinct functions, and often Accordingly, there is an increasing demand for accurately
by different organizations. Package modeling is typically modeling stress induced transistor performance deviation at
focused on reliability issues such as solder ball fatigue, die the silicon die level, while accounting for both global and
cracking and more recently de-lamination or cracking of ultra local stress sources and their interactions. This requires a
low- dielectric layers on the die. On the other hand, silicon hierarchy of sub-modeling from global packaging level to
mechanical simulation is most often focused on performance local silicon level. However, the nature of packaging level
enhancement or degradation at the single transistor level. modeling can be different from that of silicon level modeling.
For example, the packaging level modeling often involves

978-1-4244-5760-1/10/$26.00 ©2010 IEEE

 Mobility Change

Layout
View
Global Local
(a) (b)
Package Silicon
Model Model
Fig. 2 (a) Physical layout, -bump between two die; (b) Mobility change
•w/o detailed BEOL feature •w/ detailed BEOL features
at active silicon surface resulting from mechanical stress.
•Thermal process history •Equivalent stress conditions
plastic deformation and will ignore detailed local BEOL
features and is currently handled by packaging FEA tools. On
contrary, silicon level modeling mainly focuses on elastic Global package BC Local silicon stress
deformation, considers the impact of detailed BEOL features
and requires translating stress information to transistor
performance deviation. This is best handled by silicon TCAD Local silicon stress w/ global BC constraints Combined
FEA tools [3]. Thus, the desired solution for 3D IC stress Model
modeling will be enabling sub-modeling with different FEA
tools. Specifically, global package stress information from Fig. 4 Simulation flow for bridging package and silicon.
package FEA tool will be imported to local TCAD models as
A simple test case demonstrates the feasibility of this
boundary constraints in the form of displacements.
simulation flow. As shown in Fig. 4, a cube (500×500×500m)
To facilitate interfacing between different tools, a stress
that consists of silicon, oxide and copper layers has been built
exchange file is proposed to transfer the boundary conditions
as a standalone local silicon model. The global package model
from package level analyses to silicon feature level analyses.
is represented as the local silicon model wrapped by package
Such a data file is needed in order to decouple the choice of
substrate material (1mm×1mm×2mm). While total
the simulation environments for different domains, thereby
displacement from the global package model consists of both
allowing optimum tool usages without retooling existing
mechanical displacement and thermal expansion displacement,
simulators. The data file consists of a matrix of stress fields,
only the mechanical component should be transferred to the
expressed in terms of displacements, on every face of every
local silicon model to account for the impact of the global
die in the package. The granularity of a given matrix is
package. In addition, meshes in the global and the local
determined by the size of the features on the respective die
models need to be chosen carefully to match each other in
face.
order to minimize the error during transfer. Fig. 5 shows
displacements from the center of the top face down to the
center of the bottom face for global, local and combined cases.
ε t2_top The combined case is local silicon model after importing
ε t2_side ε t2_side ε tx_bottom global displacement as boundary constrains. Note that the
Tier 2
ε tx_1,1 ε tx_1,2 …. …. ε tx_1,x displacements of global and combined cases align well at the
θ tx_1,1 θ tx_1,2 …. …. θ tx_1,x
ε t1_side ε t1_side ε tx_2,1
θ tx_1,1 θ tx_1,2
…. …. ….
….
….
…. θ tx_1,x boundaries (Z=±250m) of the local model, indicating a
Tier 1 θ tx_2,1
θ tx_2,1
….
….
….
….
….
….
….
….
successful displacements transfer. Accordingly, stress in local
…. …. …. …. ….
…. …. …. …. …. silicon will change from the local case to the combined case as
…. …. …. …. ….
Substrate
….
….
….
….
….
….
….
….
….
….
shown in Fig. 6, and stress in the combined case agrees well
ε tx_x,1
….
….
….
….
…. ….
…. ε tx_x,x
…. with that of the global case.
θ tx_x,1 …. …. …. θ tx_x,x
θ tx_x,1 …. …. …. θ tx_x,x

Global
Local
Combined
Fig. 3 (Left) Physical view of 3D stacked die in package: (Right) Stress
Exchange File, matrix of strain displacements for each face of each die.

(a) (b)
Fig. 5 (a) Displacements in x direction; (b) Displacements in z direction.
 Global
Local
Combined
(a) (b)
Fig. 6 (a) Normal stress in x direction; (b) Normal stress in z direction.
III. SILICON STRESS MODELING
To model the silicon stress in 3D ICs, the interactions
between the mechanical stresses generated by TSV, wafer
thinning, -bump and the BEOL structure should be taken into
consideration. Hence, stress simulation at the silicon level
requires a multi-level, multi-scale simulation approach
described previously. Here, the mechanical stress effects of
the higher level models can be ported to the TSV model using
the stress exchange files described previously and the stress
impact can be assessed while accounting for various factors
like packaging, BEOL and other manufacturing processes.
In order to demonstrate the feasibility of the above
approach a generic TSV model is studied here. This model
consists of a combination of two silicon wafers, i.e. Tier 1
wafer and Tier 2 wafer. Tier 1 wafer consists of one circuit
block, the metallization structure, an embedded TSV and a -
bump. Tier 2 wafer consists of another circuit block, the
metallization structure and a -bump to form a connection
with the Tier 1 wafer. Both the wafers are combined using a
bonding material. Fig. 7 (A) shows the Tier 1 wafer, Fig. 7(B)
shows the Tier 2 wafer and Fig. 7 (C) shows the combined
structure that contains Tier 1 and Tier 2 wafer. In order to
simulate the process induced stress effects in the entire
structure, all the geometries need to be defined manually and
detailed mesh needs to be specified for each region.
Fabrication process information for each step is also necessary
for the mechanical stress analysis. The process information
may not be available readily due to its confidential nature.
Overall, this process is extremely complex and requires
intervention by experienced user at multiple stages.
In order to overcome the limitations of the conventional
modeling methodology, a modeling framework using a
pseudo-process simulation is developed. This framework uses
an FEM based 3D simulator with advanced algorithms to
Fig. 7 (A) Tier 1 wafer; (B) Tier 2 wafer; (C) Combined structure.
Fig. 8 Modeling framework for TSV analysis.
generate the structures and meshes and to solve the partial
differential equations. The modeling framework also provides
application specific TSV flow templates that provide
meaningful default model and material parameter selection.
Default mesh settings are also provided for accurate resolution
of stress gradients. Fig. 8 shows a schematic representation of
the modeling framework developed for advanced TSV
structures.
Instead of using detailed process information, which can be
difficult to obtain due to confidentiality, non-proprietary
material information such as stress-free temperature or thin-
film residual stress can be used to generate a fast and accurate
model of TSV structures. The TSV stress free temperatures
can be easily determined from direct measurement. The
residual stresses in various BEOL layers and packaging levels
can be sourced directly from a foundry or determined from
measurements. Using this information, the structures and the
meshes are generated utilizing the built-in structure library
that contains parameterized structure and mesh generation
modules. Mechanical stresses are calculated using the material
properties, stress free temperatures and intrinsic stresses
contained within the material library. The entire process
requires only a few geometry and/or technology specifications
from the user. Using this framework, a system designer can
quickly generate an accurate feedback for the impact of
process induced stress on TSV reliability.
To assess the modeling framework presented here, TSV
stress analysis is carried out on a generalized structure. Here,
the geometry specifications are provided by the user. For Tier
1 and Tier 2 structures, one thermal ramp-down from stress-
free temperature 250 °C to room temperature 25 °C is
performed. The Tier 1 and Tier 2 structures are combined and
the under-filling operation is carried out at the stress-free
temperature. For these analyses, the boundary conditions are
set to represent a repetitive structure in the xy-plane; and
allow for the simulation of only one quarter of the structure.
Fig. 9 shows a portion of the user specified inputs. Here, only
the geometry specifications and the thermal cycles for the

Fig. 9 Portion of the user specified inputs.
Fig. 10 (A) Tier 1 wafer; (B) Tier 2 wafer; (C) Complete TSV structure.
TSV are defined. The TSV modeling framework generates
accurate structures and stress profiles after completing the
numeric simulation. Fig. 10 (A) shows the Tier 1 wafer, Fig.
10 (B) shows the Tier 2 wafer and Fig. 10 (C) shows the
combination of Tier 1 and tier 2 wafers along with the under-
filling material between the two wafers.
The mechanical stress profiles are analyzed after
performing the stress simulation. Fig. 11 (A) shows Von
Mises’ effective stress in Tier 1 wafer, Fig. 11 (B) shows Von
Mises’ effective stress in Tier 2 wafer and Fig. 11 (C) shows
Von Mises’ effective stress in the combined TSV structure.
These results clearly indicate that the thermal cycles
experienced by the structure during fabrication have a
significant impact on the residual mechanical stress. Also, the
residual mechanical stresses are generated primarily due to the
expansion and contraction of the copper TSV during
processing. Moreover, the mechanical stresses generated in
the -bumps depend on the joining and under-filling process
used. Additionally, the device performance in the active
silicon is altered by the interaction between mechanical
stresses generated during TSV fabrication, backside thinning,
-bumping, and packaging processes.
Fig. 11 Von Mises' Effective Stress (MPa) in: (A) Tier 1 wafer; (B) Tier 2
wafer; (C) Combined structure
The results illustrate the feasibility of using a pseudo-
process approach to simulate mechanical stresses in 3D IC
structures. Also, mechanical stresses from top level structures
like backside layers, -bumps, BEOL layers and package
structures can be easily ported into the simulation framework
using the stress exchange files described earlier. This porting
allows the designer to simulate an entire 3D IC structure with
different tools at different geometry levels, thereby optimizing
the tool usage. This porting increases the accuracy and the
robustness of the 3D modeling and provides a complete
understanding of mechanical stress effects in 3D IC structures.
IV SUMMARY AND CONCLUSIONS
An innovative methodology that bridges package and
silicon domain stress simulations and a new stress exchange
file that facilitates stress information exchange across domains
are proposed and demonstrated for 3D IC stress analysis and
management. New techniques that account stress history
evolution and differentiate thermal and mechanical
displacements are developed. A modeling framework that
provides fast and reliable design inputs for 3D IC structure
generation and stress analysis is presented. The modeling
framework uses a pseudo-process simulation approach, where
sensitive process-related information is replaced by equivalent
stress-free temperatures and thin film residual stresses. The
framework also provides parameterized geometry and mesh
generation modules to build 3D IC structures and to perform
accurate stress simulations with minimal user intervention.
REFERENCES
[1] R. Radojcic, et al., 2009 DATE, 3D Integration
Workshop Digest, pp 282
[2] A. Karmarkar, X. Xu, and V. Moroz, 2009 IRPS, pp.
682-687
[3] Fammos – TX User Guide and Fammos – TX Reference
manual, Synopsys, Inc., June 2009.
[4] The International Technology Roadmap for
Semiconductors (ITRS), 2007.