Electrical Engineering Principlesand Applications 6th

Edition by Hambley ISBN 0133413985 9780133413984

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CHAPTER 7

Exercises

E7.1 (a) For the whole part, we have:

Quotient Remainders
23/2 11 1
11/2 5 1
5/2 2 1
2/2 1 0
1/2 0 1
Reading the remainders in reverse order, we obtain:
2310 = 101112
For the fractional part, we have
2  0.75 = 1 + 0.5
2  0.50 = 1 + 0
Thus, we have
0.7510 = 0.1100002
Finally, the answer is 23.7510 = 10111.112

(b) For the whole part, we have:

Quotient Remainders
17/2 8 1
8/2 4 0
4/2 2 0
2/2 1 0
1/2 0 1
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 Reading the remainders in reverse order, we obtain:
1710 = 100012
For the fractional part, we have
2  0.25 = 0 + 0.5
2  0.50 = 1 + 0
Thus, we have
0.2510 = 0.0100002

Finally, the answer is 17.2510 = 10001.012

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 (c) For the whole part we have:
Quotient Remainders
4/2 2 0
2/2 1 0
1/2 0 1
Reading the remainders in reverse order we obtain:
410 = 1002
For the fractional part, we have
2  0.30 = 0 + 0.6
2  0.60 = 1 + 0.2
2  0.20 = 0 + 0.4
2  0.40 = 0 + 0.8
2  0.80 = 1 + 0.6
2  0.60 = 1 + 0.2
Thus we have
0.3010 = 0.0100112
Finally, the answer is 4.310 = 100.0100112

E7.2 (a) 1101.1112 = 123 + 122 +021 +120 +12-1 +12-2 +12-3 = 13.87510

(b) 100.0012 = 122 +021 +020 +02-1 +02-2 +12-3 = 4.12510

E7.3 (a) Using the procedure of Exercise 7.1, we have

9710 = 11000012
Then adding two leading zeros and forming groups of three bits we have
001 100 0012 = 1418
Adding a leading zero and forming groups of four bits we obtain
0110 0001 = 6116

(b) Similarly
22910 = 111001012 = 3458 = E516

E7.4 (a) 728 = 111 010 = 1110102

(b) FA616 = 1111 1010 0110 = 1111101001102

E7.5 19710 = 0001 1001 0111 = 000110010111BCD

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 E7.6 To represent a distance of 20 inches with a resolution of 0.01 inches, we
need 20/0.01 = 2000 code words. The number of code words in a Gray
code is 2L in which L is the length of the code words. Thus we need L =
11, which produces 2048 code words.

E7.7 (a) First we convert to binary

2210 = 16 + 4 + 2 = 101102
Because an eight-bit representation is called for, we append three
leading zeros. Thus +22 becomes
00010110
in two’s complement notation.

(b) First we convert +30 to binary form

3010 = 16 + 8 + 4 + 2 = 111102
Attaching leading zeros to make an eight-bit result we have
3010 = 000111102
Then we take the ones complement and add 1 to find the two’s
complement:
one’s complement: 11100001
add 1 +1
11100010
Thus the eight-bit two’s complement representation for -3010 is
11100010.

E7.8 First we convert 1910 and -410 to eight-bit two’s complement form then we
add the results.
19 00010011
-4 111111100
15 00001111
Notice that we neglect the carry out of the left-most bit.

E7.9 See Tables 7.3 and 7.4 in the book.

E7.10 See Table 7.5 in the book.

E7.11 (a) To apply De Morgan’s laws to the expression

AB + B C
first we replace each logic variable by its inverse

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 A B + BC
then we replace AND operations by OR operations and vice versa
(A + B )(B + C )
finally we invert the entire expression so we have
D = AB + B C = (A + B )(B + C )

(b) Following the steps of part (a) we have

[F (G + H ) + FG ]

[F (G + H ) + F G ]

[(F + G H )(F + G )]

E = [F (G + H ) + FG ] = [(F + G H )(F + G )]

E7.12 For the AND gate we use De Morgan’s laws to write

AB = (A + B )

See Figure 7.21 in the book for the logic diagrams.

E7.13 The truth table for the exclusive-OR operation is

A B AB
0 0 0
0 1 1
1 0 1
1 1 0

Focusing on the rows in which the result is 1, we can write the SOP
expression
A  B = A B + AB
The corresponding logic diagram is shown in Figure 7.25a in the book.

Focusing on the rows in which the result is 0, we can write the POS
expression
A  B = (A + B )(A + B )

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 The corresponding logic diagram is shown in Figure 7.25b in the book.

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 E7.14 The truth table is shown in Table 7.7 in the book. Focusing on the rows in
which the result is 1, we can write the SOP expression
A =  m (3, 6, 7, 8, 9, 12)
= F D GR + F DGR + F DGR + FD G + FD G R + FDG R
R

Focusing on the rows in which the result is 0, we can write the POS
expression
A =  M (0, 1, 2, 4, 5, 10, 11, 13, 14, 15)
= (F + D + G + R )(F + D + G + R )(F + D + G + R ) (F + D + G + R )

E7.15 The Truth table is shown in Table 7.8.

E7.16 (a) A B C D

(b) A B C D

E7.17 See Figure 7.34 in the book.

E7.18 See Figure 7.35 in the book.

E7.19 Because S is high at t = 0, Q is high and remains so until R becomes high

at t = 3. Q remains low until S becomes high at t = 7. Then Q remains
high until R becomes high at t = 11.

E7.20 See Table 7.9.

E7.21 See Figure 7.49 in the book.

Problems

P7.1* 1. When noise is added to a digital signal, the logic levels can still be
exactly determined, provided that the noise is not too large in amplitude.
Usually, noise cannot be completely removed from an analog signal.

2. Component values in digital circuits do not need to be as precise as in

analog circuits.

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 3. Very complex digital logic circuits (containing millions of components)
can be economically produced. Analog circuits often call for large

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 capacitances and/or precise component values that are impossible to
manufacture as large-scale integrated circuits.

P7.2 The noise margins for a logic circuit are defined as

NML = VIL − VOL and NMH = VOH − VIH
in which VIL is the highest input voltage accepted as logic 0, VIH is the
lowest input voltage accepted as logic 1, VOL is the highest logic-0 output
voltage, and VOH is the lowest logic-1 output voltage.
Large values for the noise margins are important so noise added to
or subtracted from logic signals in the interconnections does not change
the operation of the logic circuit.

P7.3 A bit is a binary symbol that can assume values of 0 or 1. A byte is a

word consisting of eight bits. A nibble is a four-bit word.

P7.4 In positive logic, the logic value 1 is represented by a higher voltage

range than the voltage range for logic 0. The reverse is true for negative
logic.

P7.5 The noise margins for the logic circuits in use are
NML = VIL − VOL = 2.2 - 0.5 = 1.7 V
NMH = VOH − VIH = 4.7 – 3.7 = 1.0 V
Noises in the range from -0.3 V to +0.6 V do not exceed the noise
margins so the system is reliable.
Reference to Figure 7.3 in the book, shows that as long as the
noise amplitude is in the range from –NMH to +NML the logic levels will be
interpreted properly at the receiving end. Thus, as long as the noise
amplitudes are in the range from -1.0 V to +1.7 V, this system will be
reliable.

P7.6 In serial transmission, the bits of a word are transmitted one after
another over a single pair of wires. In parallel transmission, multiple bits
are transmitted simultaneously over a parallel set of wires.

P7.7 Seven-bit words are needed to express the decimal integers 0 through
100 in binary form (because 27 = 128).
Ten-bit words are needed to express the decimal integers 0 through
1000 in binary form (because 210 = 1024).

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 Twenty-bit words are needed to express the decimal integers 0 through
106 in binary form (because 220 = 1048576).

P7.8 (a)* 5.625

(b)* 21.375
(c) 14.125
(d) 13.125
(e) 9.3125
(f) 15.75

P7.9 (a)* 1101.11 + 101.111 = 10011.101

(b) 1011.01 + 1010.11 = 10110.00
(c) 10101.101 + 1101.001 = 100010.110
(d) 1011000.1000 + 10001001.1001 = 11100010.0001

P7.10 (a)* 9.7510 = 1001.112 = 1001.01110101BCD

(b) 6.510 = 0110.12 = 0110.0101BCD

(c) 11.7510 = 1011.112 = 00010001.01110101BCD
(d) 63.0312510 = 111111.000012 =01100011.00000011000100100101BCD
(e) 67.37510 = 1000011.0112 = 01100111.001101110101BCD

P7.11 (a)* FA.F16 = 11111010.11112 = 372.748 = 250.937510

(b) 2A.116 = 101010.00012 = 52.048 = 42.062510
(c) 777.716 = 11101110111.01112 = 3567.348 = 1911.437510
(d) F0F.F16 = 111100001111.11112 = 7417.748 = 3855.937510

P7.12 (a)* 10010011.0101BCD + 00110111.0001BCD = 93.510 + 37.110 = 130.610 =

000100110000.0110BCD

(b) 01010100.1000 BCD + 01001001.1001 BCD = 54.810 + 49.910 = 104.710 =

000100000100.0111BCD

(c) 0111 1001 0110.0011 BCD + 0011 0101.1001 BCD = 796.310 + 35.910 =
832.210 = 100000110010.0010BCD

P7.13 (a) Counting in decimal, 378 follows 377.

(b) Counting in octal, 400 follows 377.

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 (c) Counting in hexadecimal, 378 follows 377.

P7.14 (a)* 313.062510 = 100111001.00012 = 471.048 = 139.116

(b) 253.2510 = 11111101.012 = 375.208 = FD.416
(c) 349.7510 = 101011101.112 = 535.68 = 15D.C16
(d) 835.2510 = 1101000011.012 = 1503.28 = 343.416
(e) 212.510 = 11010100.12 = 324.48 = D4.816

P7.15 (a)* 75 = 01001011 (eight-bit signed two’s complement)

(b)* -87 = 10101001
(c) 19 = 00010011
(d) -19 = 11101101
(e) -95 = 10100001
(f) 125 = 01111101

P7.16 (a)* 777.78 = 111111111.1112 = 1FF.E16 = 511.87510

(b) 123.58 = 1010011.1012 = 53.A16 = 83.62510
(c) 24.48 = 10100.1002 = 14.816 = 20.510
(d) 644.28 = 110100100.01002 = 1A4.416 = 420.2510

P7.17 (a) A 4-bit binary number can represent the decimal integers 0 through
24 – 1 = 15.
(b) A 4-digit octal number can represent the decimal integers 0 through
84 – 1 = 4095.
(c) A 4-digit hexadecimal number can represent the decimal integers 0
through 164 – 1 = 65535.

P7.18* Write the 3-bit code shown in Figure 7.9. Then, extend the list by
writing the 3-bit code in reverse order. Finally, prepend a 0 to each word
in top half of the list and prepend a 1 to each word in the bottom half.
The resulting four-bit Gray code is:
0000
0001
0011
0010
0110
0111
0101
0100
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 1100
1101
1111
1110
1010
1011
1001
1000
The Gray code is used for coding positions of movable parts. In a Gray
code, each code word differs in only one bit from its neighboring code
words, so that erroneous position indications are avoided during
transitions.
P7.19 One's Complement Two's Complement

(a) * 11101000  00010111  00011000

(b) 00000000  11111111  00000000
(c) 01010101  10101010  10101011

(d) 01111100  10000111  10000100

(e) 11000000  00111111  01000000

P7.20 (a)* FA5.616 = 4005.37510

(b)* 725.38 = 469.37510
(c) F4.816 = 244.5010
(d) 143.258 = 99.32812510
(e) EF.A16 = 239.62510

P7.21 (a)* 33 00100001

-37 11011011
-4 11111100

(b) 17 00010001
+15 00001111
32 00100000

(c) 17 00010001
-15 11110001
2 00000010

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 (d) 15 00001111
-39 11011001
-24 11101000

(e) 49 00110001
-44 11010100
5 00000101

P7.22 Overflow and underflow are not possible if the two numbers to be added
have opposite signs. If the two numbers to be added have the same sign
and the result has the opposite sign, underflow or overflow has occurred.
P7.23 (a) 0.110 = 0.000110011 0011 2

(b) 0.610 = 0.100110011 0011 2

(c) Most calculators give (0.1  1024 − 102)  10 − 4 = 0 exactly.

(d) Using MATLAB, I have

>> (0.1*1024 - 102)*10 - 4
ans = 5.6843e-014
which is not zero because of the error associated with representing 0.110
in binary with a finite number of bits.

P7.24 A truth table lists all of the combinations of the variables in a logic
expression as well as the value of the expression.

P7.25 If the variables in a logic expression are replaced by their inverses, the
AND operation is replaced by OR, the OR operation is replaced by AND,
and the entire expression is inverted, the resulting logic expression
yields the same values as before the changes. In equation form, we have:
ABC = A + B + C (A + B + C ) = A B C

P7.26 AND gate:

AB C
00 0
01 0
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 10 0
11 1

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 OR gate:

AB C
00 0
01 1
10 1
11 1

Inverter:

AA
0 1
1 0

NAND gate:

AB C
00 1
01 1
10 1
11 0

NOR gate:

AB C
00 1
01 0
10 0
11 0

Exclusive OR gate:
AB C
00 0
01 1
10 1
11 0
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 P7.27 (a)* E = AB + ABC + CD

A B C D E
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
(b) D = ABC + AC

A B C D
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

(c) Z = WX + (X + Y )

X Y W Z
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
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 1 1 0 0
1 1 1 1

(d) D = AB +C
A B C D
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

(e) D = (A + BC )

A B C D
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

P7.28 One method to prove the validity of a Boolean identity is to list the truth
table and show that both sides of the identity give the same result for
each combination of logic variables.

P7.29* A B C (A + B)(A + C) A + BC
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
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 P7.30 A B C A + B +C ( A + B +C ) ABC

0 0 0 1 0 0
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 0 0
1 1 0 1 0 0
1 1 1 0 1 1

Thus, we have ABC = A + B + C

A B C AB C (A B C ) A +B +C
0 0 0 1 0 0
0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 0 1 1
1 0 0 0 1 1
1 0 1 0 1 1
1 1 0 0 1 1
1 1 1 0 1 1

Thus, we have A + B + C = A B C

P7.31 A B A +B A + AB (A + B )(A + AB )
0 0 0 1 0
0 1 1 1 1
1 0 1 0 0
1 1 1 1 1

Notice that the column for B matches that for (A + B )(A + AB ).

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 P7.32 A B A +AB A +B

0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1

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 P7.33 A B C (ABC + AB C + AB C + ABC )

0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

P7.34 (a) F = (A + B )C
A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

(b) F = A + B + (BC )
A B C F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

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 (c) F = AB + (BC ) + D

A B C D F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

P7.35 (a)* ( )
F = A + B + C (A + B + C ) A + B + C ( )

(b) F = ABC + AB C + ABC

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 (c) F = A + BC

P7.36 (a)* F = (A + B + C )(A + B + C )(A + B + C ) = A B C + A BC + AB C

(b)* F = ABC + AB C + A BC = (A + B + C )(A + B + C )(A + B + C )

(c) (
F = AB + (C + A )D = A + B (C A + D ) )

(d) ( )
F = A B + C + D = (A + BC )D

(e) (
F = ABC + A(B + C ) = A + B + C A + B C )( )

P7.37 (a) Applying De Morgan's laws to the output, we have

C = A + B = AB

Thus, the gate shown is equivalent to a NAND gate.

(b) Applying De Morgan's laws to the output, we have

F =D E =D +E

Thus, the gate shown is equivalent to a NOR gate.

P7.38 The truth table is

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

The circuit is

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 P7.39 The truth table is

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 A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The circuit is

P7.40 NAND gates are said to be sufficient for combinatorial logic because any
Boolean expression can be implemented solely with NAND gates.
Similarly, NOR gates are sufficient.

P7.41 In this circuit, if switch C is closed and if either of the other two
switches is closed, the output is high. Thus, we can write:
D = (A + B )C
The truth table is:
A B C D
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

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 P7.42

P7.43 In this circuit, the output is high only if switch A is open (A low) and if
either of the other two switches is open. Thus, we can write
D = A (C + B )

The truth table is:

A B C D
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

P7.44 In synthesizing a logic expression as a sum of products, we focus on the

lines of the truth table for which the result is 1. A logical product of
logic variables and their inverses is written that yields 1 for each of
these lines. Then, the products are summed.

In synthesizing a logic expression as a product of sums, we focus on the

lines of the truth table for which the result is 0. A logical sum of logic
variables and their inverses is written that yields 0 for each of these
lines. Then, the sums are combined in an AND gate.

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 P7.45* F = A B C + ABC + ABC + ABC

= m (0,2,5,7)
( )
F = (A + B + C ) A + B + C (A + B + C ) A + B + C ( )
=  M (1,3,4,6)

P7.46 G = A B C + A BC + ABC

=  m (0,1,3)
G = (A + B + C )(A + B + C )(A + B + C )(A + B + C )(A + B + C )

=  M (2,4,5,6,7 )
P7.47 H = A B C + A B C + A BC + A BC + A BC

=  m (0,1,2,6,7)
H = (A + B + C )(A + B + C )(A + B + C )

=  M (3,4,5)
P7.48 I = A BC + A BC + ABC + ABC

=  m (2,3,6,7)
I = (A + B + C )(A + B + C )(A + B + C )(A + B + C )
=  M (0,1,4,5)

P7.49 J = A B C + A BC + ABC + ABC

=  m (1,3,6,7)
J = (A + B + C )(A + B + C )(A + B + C )(A + B + C )
=  M (0,2,4,5)

P7.50 K = A BC + A BC + AB C + AB C

=  m (2,3,4,5)
K = (A + B + C )(A + B + C )(A + B + C )(A + B + C )
=  M (0,1,6,7)
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 P7.51 Applying De Morgan's Laws to the output of the circuit, we have
AB + CD = AB CD
Thus, the circuit implemented with NAND gates is

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 P7.52 Applying De Morgan's Laws to the output of the circuit, we have
(A + B )(C + D ) = (A + B ) + (C + D )

Thus, the circuit implemented with NOR gates is

P7.53* The truth table is:

A B A B
0 0 0
0 1 1
1 0 1
1 1 0
Thus, we can write the product of sums expression and apply De Morgan’s
Laws to obtain:
A  B = AB + AB = (AB ) (A B )
The circuit is:

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 P7.54 The truth table is:
A B A B
0 0 0
0 1 1
1 0 1
1 1 0
Thus, we can write the product of sums expression and apply De Morgan’s
Laws to obtain:
A  B = (A + B )(A + B ) = (A + B ) + (A + B )

The circuit is:

P7.55 An example of a decoder is a circuit that uses a BCD input to produce the
logic signals needed to drive the elements of a seven-segment display.

Another example is the three-to-eight-line decoder that has a three-bit

input and eight output lines. The 3-bit input word selects one of the
output lines and that output becomes high.

P7.56* (a) S1 S2 ST E
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0

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 (b) E =  m (1,6) = S1 S2ST + S1S2 ST

(c) Circuit diagram:

P7.57 (a) The truth table is:

B E F G I
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0

(b) I = m (4,5,8,12,13)

(c) I =  M (0,1,2,3,6,7,9,10,11,14,15 )

(d) I = E F + BF G

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 P7.58 The truth table (x = don't cares) is:
B8 B4 B2 B1 A B C D
0 0 0 0 1 1 1 1
0 0 0 1 0 1 1 0
0 0 1 0 1 1 0 1
0 0 1 1 1 1 1 1
0 1 0 0 0 1 1 0
0 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1
0 1 1 1 1 1 1 0
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

A =  M (1,4,6)
B =  M (5,6)
C = M (2) = B8 + B4 + B2 + B1
D =  M (1,4,7,9)
The circuits are:

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 P7.59* (a) The Karnaugh map is:

(b) F = BC + A CD

(c) Inverting the map, and writing the minimum SOP expression yields
F = AC + B C + CD . Then applying DeMorgan's laws gives

F = (A + C )(B + C )(C + D )

P7.60 (a) The Karnaugh map is:

(b) D = B C + A BC

(c) Inverting the map, and writing the minimum SOP expression yields two
possibilities:
D = AC + BC + B C and D = AB + BC + B C

Then, applying DeMorgan's laws gives the POS expressions:

D = (A + C )(B + C )(B + C ) and D = (A + B )(B + C )(B + C )

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 P7.61 (a) The Karnaugh map is:

(b) D = C + AB

(c) Inverting the map, and writing the minimum SOP expression yields
D = AC +BC

Then, applying De Morgan's laws gives the POS expression:

D = (A + C )(B + C )

P7.62 (a) The Karnaugh map for D is:

(b) D = A C + AC

(c) D = A C + AC D = (A + C )(A + C )

P7.63 (a) The Karnaugh map is:

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 (b) D = AB + BC

(c) Inverting the map, and writing the minimum SOP expression yields
D = B + A C . Then, applying De Morgan's laws gives

D = B (A + C ) = AB + BC which is the same as the expression found

in part (b) so the implementation is the same.

P7.64 (a) The Karnaugh map is:

(b) F = AB D + BCD

(c) The circuit is:

(d) Inverting the map, and writing the minimum SOP expression
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 yields F = A D + B + C D . Then applying DeMorgan's laws gives

F = (A + D )B (C + D )

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 P7.65* (a) The Karnaugh map is:

(b) E = AB + CD

(c) The circuit is:

(d) Inverting the map, and writing the minimum SOP expression yields
E = A C + A D + B C + B D . Then, applying DeMorgan's laws gives

E = (A + C )(A + D )(B + C )(B + D )

P7.66 (a) The Karnaugh map is:

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 (b) F = ABC + BCD

(c) The circuit is:

(d) Inverting the map, and writing the minimum SOP expression yields
F = A D + B + C . Then, applying De Morgan's laws gives

F = (A + D )BC

P7.67 (a) The Karnaugh map is:

(b) G = BC + AD

(c) The circuit is:

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 (d) Inverting the map, and writing the minimum SOP expression yields
G = A B + A C + B D + C D . Then, applying DeMorgan's laws gives

G = (A + B )(A + C )(B + D )(C + D ) .

P7.68 (a) The Karnaugh map is:

(b) H = AC + AD

(c) The circuit is:

(d) Inverting the map, and writing the minimum SOP expression yields
H = A + CD . Then, applying De Morgan's laws gives
H = A (C + D ) .

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 P7.69 (a) The Karnaugh map is:

(b) I = AB + CD

(c) The circuit is:

(d) Inverting the map, and writing the minimum SOP expression yields
I = A C + A D + BC + B D . Then, applying De Morgan's laws gives

I = (A + C )(A + D )(B + C )(B + D )

P7.70 The Karnaugh map (with the decimal equivalent of each word in the upper
right hand corner of each square) is:

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 By inspection, the minimal SOP expression is:
X = B8B4 + B8B2
Inverting the map, and writing the minimum SOP expression yields
X = B8 + B2B4 . Then, applying DeMorgan's laws gives
X = B8 (B2 + B4 ) .

P7.71 The Karnaugh map (with the decimal equivalent of each word in the upper
right hand corner of each square) is:

By inspection the minimal SOP expression is:

X = B8 B1

P7.72 The truth table is:

S I1 I2 O1 O2
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 1 1
1 0 0 0 0
1 0 1 1 0
1 1 0 0 1
1 1 1 1 1

The Karnaugh maps are:

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 The logic circuit is:

P7.73 The Karnaugh map (with the hexadecimal equivalent of each word in the
upper right hand corner of each square) is:

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 By inspection the minimal SOP expression is:

X = B1B4

Inverting the map, and writing the minimum SOP expression yields
X = B1 + B4 . Then, applying DeMorgan's laws gives
X = B1B4 .

P7.74 The Karnaugh map for a three-member council is:

By inspection, we see that three two-cubes are needed and the minimal
SOP expression is
X = AB + AC + BC

Clearly, the minimal SOP checks to see if at least one group of two
members has voted yes.

For a five-member council, the Karnaugh map consists of two four-

variable maps, one for A = 1 and one for A = 0.

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 Notice that six four-cubes are needed to cover the A = 1 part of the
map. Think of the A = 0 map as being (over or under) the A = 1 map. Four
two cubes are needed to cover the A = 0 part of the map. However each
of these cubes can be combined with corresponding cubes in the A = 1
part of the map to form four 4-cubes. The minimum SOP expression is:
X = ABC + ABD + ABE + ADE + ACD + ACE + BCD + BCE + BDE + CDE

Here, the minimal SOP expression checks to see if at least one group of
three members has voted yes.

P7.75 The Karnaugh map is

By inspection, we see that six one cubes are needed. Thus the minimal
SOP expression is:
X = ABC D + AB CD + AB C D + A BCD + A BC D + A B CD

P7.76 (a) The truth table for the circuit of Figure P7.76 is
A B C D P
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
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 1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

(b) The Karnaugh map for P is:

From the map, we see that no simplification is possible and the minimum
SOP is actually the sum of minterms:
P =  m(1, 2, 4, 7, 8, 11, 13, 14)

(c) The parity check can be performed by the same method as used in
Figure P7.76, namely to XOR all of the bits. The circuit is:

P7.77 By inspection, we see that

X =A

The Karnaugh maps for Y and Z are:

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 Y = A B + AB Z = BC + B C

P7.78 By inspection, we see that

A=X

The Karnaugh maps for B and C are:

B = XY + XY C = X Y Z + X YZ + XY Z + XYZ

P7.79* (a) F = A + BC + BD

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 (b) G = A + BD + BC

(c) H = A + B C + BC D

(d) I =D

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 P7.80 (a) A = FH

(b) B = F G + FH

(c) C = GH + G H

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 (d) D =I

P7.81 (a) W = A + BC + BD

(b) X = B C + B D + BC D

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 (c) Y = CD + C D

(d) Z =D

P7.82 (a) A = WX +WZ

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 (b) B = X Y + XYZ +WYZ

(c) C = Y Z + YZ

(d) D=Z

P7.83 See Figure 7.39 in the text.

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 P7.84

P7.85 See Figure 7.44 in the text.

P7.86 Asynchronous inputs are recognized independently of the clock signal.

Synchronous inputs are recognized only if the clock is high.

P7.87 In edge triggering, the input values present immediately prior to a

transition of the clock signal are recognized. Input values (and changes
in input values) at other times are ignored.

P7.88 See Figure 7.47 in the text.

P7.89* The successive states are:

Q0Q1 Q2
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
(repeats)
Thus, the register returns to the initial state after seven shifts.

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 P7.90 (a) With an OR gate, we have:

Q0 Q1 Q2
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
1 1 1
After the register reaches the 111 state, it remains in that state and
never returns to the starting state.
(b) With an AND gate, we have:
Q0 Q1 Q2
1 0 0
0 1 0
0 0 1
0 0 0
0 0 0
After the register reaches the 000 state, it remains in that state and
never returns to the starting state.

P7.91

The period of the Q0 waveform is double that ofVIN . Similarly, the

period of Q1 is twice that of Q0 . Thus, flip flops connected in this

manner divide the frequency of an input signal by two and by four.

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 P7.92

Q3 becomes high at t = 7 and quickly resets all four flip flops.

P7.93*

Q J K D
memory 0 0 0 0
reset 0 0 1 0
set 0 1 0 1
toggle 0 1 1 1
memory 1 0 0 1
reset 1 0 1 0
set 1 1 0 1
toggle 1 1 1 0

D = QJ K + QJK + QJ K + QJ K
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 ( )
= QJ K + K + QK J + J ( )

= QJ + QK

P7.94

P7.95 (a) There are four diodes and to make one revolution in two seconds each
diode must be on for 0.5 s. Thus, the frequency of the clock is 2 Hz.

(b) The modulo-4 counter is:

(c) The truth table is

S Q2 Q1 D1 D2 D3 D4
0 0 0 1 0 0 0
0 0 1 0 1 0 0
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is protected by Copyright and written permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system,
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 1 0 0 1 0 0 0
1 0 1 0 0 0 1
1 1 0 0 0 1 0
1 1 1 0 1 0 0

The minimal SOP expressions are:

D1 = Q1Q2 D2 = Q1Q2S + Q1Q2S D3 = Q1Q2 D4 = Q1Q2S + Q1Q2S

P7.96 (a) The logic diagram for the counter is:

(b) The truth table for the encoder is:

Q3 Q2 Q1 D1 D2 D3 D4 D5 D6 D7
0 0 0 x x x x x x x
0 0 1 0 0 0 1 0 0 0
0 1 0 1 0 0 0 0 0 1
0 1 1 1 0 0 1 0 0 1
1 0 0 1 1 0 0 0 1 1
1 0 1 1 1 0 1 0 1 1
1 1 0 1 1 1 0 1 1 1
1 1 1 x x x x x x x

The Karnaugh maps are:

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 From the maps we can write:
D1 = D7 = Q2 + Q3 D2 = D6 = Q3 D4 = Q1 and D3 = D5 = Q2Q3

The logic diagram is:

Practice Test

T7.1 (a) 12, (b) 19 (18 is incorrect because it omits the first step, inverting
the variables), (c) 20, (d) 23, (e) 21, (f) 24, (g) 16, (h) 25, (i) 7, (j) 10, (k)
8, (l) 1 (the binary codes for hexadecimal symbols A through F do not
occur in BCD).
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 T7.2 (a) For the whole part, we have:
Quotient Remainders
353/2 176 1
176/2 88 0
88/2 44 0
44/2 22 0
22/2 11 0
11/2 5 1
5/2 2 1
2/2 1 0
1/2 0 1
Reading the remainders in reverse order, we obtain:
35310 = 1011000012
For the fractional part, we have
2  0.875 = 1 + 0.75
2  0.75 = 1 + 0.5
2  0.5 = 1 + 0
Thus, we have
0.87510 = 0.1112
Finally, combining the whole and fractional parts, we have
353.87510 = 101100001.1112

(b) For the octal version, we form groups of three bits, working outward
from the decimal point, and then write the octal symbol for each group.
101 100 001.1112 = 541.78

(c) For the hexadecimal version, we form groups of four bits, working
outward from the decimal point, and then write the hexadecimal symbol
for each group.
0001 0110 0001.11102 = 161.E16

(d) To obtain binary coded decimal, we simply write the binary equivalent
for each decimal digit.
353.87510 = 0011 0101 0011.1000 0111 0101BCD

T7.3 (a) Because the left-most bit is zero, this is a positive number. We simply
convert from binary to decimal:
011000012 = 1  26 + 1  25 + 1 20 = 64 + 32 + 1 = +9710

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 (b) Because the left-most bit is one, this is a negative number. We form
the two's complement, which is 01000110. Then, we convert from binary
to decimal:
010001102 = 1  26 + 1  22 + 1  21 = 64 + 4 + 2 = +7010
Thus, the decimal equivalent for eight-bit signed two's complement

integer 10111010 is −70.

T7.4. (a) The logic expression is D = A B + (B + C ) .

(b) The truth table is:

A B C D
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

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 The Karnaugh map is:

(c) The map can be covered by two 2-cubes and the minimum SOP
expression is D = AB + B C .

(d) First, we invert the map to find:

This map can be covered by one 4-cube and one 2-cube and the minimum
SOP expression is D = B + AC . Applying DeMorgan's laws to this yields

the minimum POS expression D = B (A + C ) .

T7.5 (a) The completed Karnaugh map is:

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 (b) The map can be covered by two 2-cubes and the minimum SOP
expression is G = B1 B2 B8 + B1B2B8 .

(c) First, we invert the map to find:

This map can be covered by one 8-cube and two 4-cubes and the minimum
SOP expression is G = B1 + B2 B8 + B2B8 . Applying De Morgan's laws to this

yields the minimum POS expression G = B1 (B2 + B8 )(B2 + B8 ) .

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 T7.6 Clearly, the next value for Q0 is the NAND combination of the current
values of Q1 and Q2. The next value for Q2 is the present value for Q1.
Similarly, the next value for Q1 is the present value for Q0. Thus, the
successive states (Q0 Q1 Q2) of the shift register are:

100 (initial state)

110
111
011
001
100
111

The state of the register returns to its initial state after 5 shifts.

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