“Digital Logic Design”

LAB REPORT 4
Date of Submission:
4th April 2023

Prepared For:
Sir Noman Ahmed

Section:
BEE-2C

Prepared by:

NAME REGISTRATION NUMBER

Muhammad Abdul Moiz CIIT/FA22-BEE-122/ISB

Muhammad Abdullah CIIT/FA22-BEE-125/ISB

Muhammad Ali Aijaz Kiani CIIT/FA22-BEE-133/ISB

COMSATS UNIVERSITY ISLAMABAD.

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Design and Implementation of Boolean Functions by

Standard Forms using ICs/Verilog

Objective:

In this lab, we implement Boolean functions by using SoP (sums of product) and PoS (products
of sum).

Pre-Lab:
TASK 1:

TASK 2 AND 3:

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POST LAB:

Write a Verilog code for the sum of minterms circuit, 𝑭𝟏, (Structural Level).

module postlab1(F, A, B, C, D);

output F;
input A, B, C, D;
wire w1, w2, w3, w4, w5;
not G1(w1, A);
not G2(w2, C);
nand G3(w3, w1, C, D);
nand G4(w4, A, B);
nand G5(w5, w2, A);
nand G6(F, w3, w4, w5);

endmodule

Write a Verilog code for the reduced SoP circuit, 𝑭𝟐, (Structural Level).

module postlab2(F, A, B, C, D);

output F;
input A, B, C, D;
wire w1, w2, w3, w4, w5, w6, w7, w8;
not G1(w1, A);
not G2(w2, B);
not G3(w3, C);
nor G4(w6, A, C);
nor G5(w5, w1, B, D);
nor G6(w8, w3, A, D);
nor G7(w7, w1, w2, C, D);
nor G8(w4, w1, B, w3, D);
nor G9(F, w4, w5, w6, w7, w8);

endmodule

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Write a Verilog code for the reduced PoS circuit 𝑭𝟑, (Structural Level).

module postlab3(F, A, B, C, D);

output F;
input A, B, C, D;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9;
not G1(w1, A);
not G2(w2, B);
not G3(w3, C);
not G4(w4, D);
and G5(w5, w1, w2, C, D);
and G6(w6, w1, B, C, D);
and G7(w7, A, w2, w3, w4);
and G8(w8, A, B, w3, D);
and G9(w9, A, B, C, w4);
and G10(w10, A, B, C, D);
or G11(F, w8, w5, w6, w7, w9, w10);

endmodule

Simulate and verify the outputs by making an appropriate stimulus for the
above modules.

Post lab 1:

RESULT OF POSTLAB 1 ON XILINX

COMSATS UNIVERSITY ISLAMABAD.

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Post lab 2:

RESULT OF POSTLAB 2 ON XILINX

Post lab 3:

RESULT OF POSTLAB 3 ON XILINX

COMSATS UNIVERSITY ISLAMABAD.

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Critical Analysis:
In this lab, we learned about the minterms and maxterms and their reduced forms that are SoP
and PoS respectively. We also learned to make circuit diagrams through algebraic functions.
We implemented this as this was the lab task. It was really difficult because we haven’t studied
the theory about it in the class. I searched on google, asked for the help of sir, and following the
lab manual, still was stuck in how to draw circuits. After a thorough study of lab manual and
book, I completed the diagrams but the lab time was over.
After this, I completed all the tasks that were to be done by hand and only got left with the
implementation on the trainer. Later in the same week, I gave extra time in lab and tried to
complete it with the help of friends and google. But finally, at the end the task was completed.
Submitted By:

NAME REGISTRATION NUMBER

Muhammad Abdullah CIIT/FA22-BEE-125/ISB

COMSATS UNIVERSITY ISLAMABAD.