2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)
Performance Analysis of Transformer-less Dynamic Voltage Restorer
Haitham Elmasry1, Haitham. Z. Azazi2, E. E. El-Kholy3, Sabry A. Mahmoud4
Electrical Engineering Department, Faculty of Engineering, Menoufia University, Shebin El-Kom, Egypt
Abstract— Achieving high voltage quality for electrical power
system with small size device and low cost has a great interest
recently. This paper proposes a three-phase transformer-less dynamic
voltage restorer (DVR) system that can mitigate the voltage
disturbances in electrical distribution network. The proposed DVR
system depends on the multilevel inverter (MLI) with twelve power
electronic switches producing 49 levels in the output voltage. The
present DVR is characterized by low cost and small size where the
number of switches is lower than other DVR systems, and eliminate
the filter requirements. The proposed DVR presents a compensation
scheme with optimal utilization of energy. The DVR system is
modeled using PSCAD/EMTDC software and the simulation results
are discussed. A high performance with different fault types is
obtained using the proposed DVR system. With the help of the
dSPACE (DS1104) evaluation board, the prototype of the proposed
DVR has been constructed and tested in laboratory.
Keywords—DVR, transformer-less, multilevel inverter (MLI),
voltage sag, voltage swell, power quality, voltage disturbance.
1. INTRODUCTION
The voltage disturbances are considered one of the most
common issues of the power quality in the medium networks.
Voltage sags, swells, unbalanced voltage and transients have
the most serious effects compared with other voltage
disturbance phenomena [1]. Voltage sag (voltage dip according
to IEC term) is drooping effective voltage value between 10%
and 90%. The voltage sag is the most voltage disturbance
occurs in the distribution system [2]. The increase of voltage
magnitude more than 10% is defined as voltage swells, these
problems have durations from half cycle to 1min. [3]-[6]. In
addition to the loads (electronic applications) become more
sensitive to voltage disturbances, therefore it must have high
electrical power quality [7]-[8].
Dynamic voltage restorer (DVR) is capable of solving this
problem efficiently and fast response [9]-[12]. Conventional
DVR adjusts the voltage at load to the required value by
injecting a certain voltage value series through the line by
injection transformer. However, this injection transformer
causes many different problems including large size, high cost,
more losses and weight. The transformer-less DVR eliminates
the problems of the injection transformer by not using the
transformer in the conventional DVR configuration scheme
[13]-[14],[29]. [15]-[16] presents different DVR topologies and
control strategies. The main part in the DVR construction is
inverter. The conventional DVR at the beginning was based on
two-level inverters.
Recently, the DVR depends on multilevel inverter types,
because these types operates at high voltage levels with low
harmonics [17]. In [18], the pre-fault compensation method
has been studied. This control strategy is maintaining the load
voltage at the pre-fault value but has a disadvantage due to
high real power injection during voltage compensation. In
[19]-[20], the DVR operates at less voltage or less by
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applying a post-fault compensation strategy. The main
disadvantage of the all DVR topologies aforementioned
above is large number of components, which cause high cost,
high losses, high size and have complex control systems. This
paper proposes an economic transformer-less DVR, the
multilevel inverter used in this DVR has only twelve switches
producing 49-level of voltage in the output. The proposed
DVR achieves low cost, low losses, low size and its control
system has low running cost at any fault occurs. The proposed
DVR with the power circuit configuration as well as
compensation strategy is presented. The PSCAD/EMTDC
software program is used to produce the simulation results,
that demonstrate the proposed DVR ability to compensate the
voltage sags and swells resulting from different faults.
2. PROPOSED DVR SYSTEM
The proposed DVR system shown in Fig. 1 is used to voltage
correction. When the source side voltage (V1) changes, the DVR
injects an appropriate voltage (Vdvr) in such a way that the desired
load voltage (V2) undisturbed regardless of source side
conditions. The proposed DVR consists of only two main parts;
a- Energy storage unit
To compensate the voltages during the sag period, the DVR
should be containing the energy source to provide active power to
the load. Two methods are used to deliver power to the
distribution system. One using internal DC source and another
using converter to supply DVR from the incoming supply. The
energy storage units such as superconducting magnetic energy
storage (SMES) and flywheels supplies DVR. The super-
capacitors and lead acid batteries also can be used as energy
storage devices.
b- Inverter circuit
The inverter is the core of the DVR. Multilevel inverter (MLI)
in proposed DVR system performs the function of both inverter
and transformer in conventional DVR.
V1
line V2
Vdvr
LOAD
supply Control
Multilevel inverter system
Energy
Storage
Element
Fig. 1 The main components of the proposed DVR.
 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)

This paper depends on reduction the number of switches

with high number of output levels in the output voltage Level 1
Sw1
waveform. Figure 2 shows a single-phase structure of MLI Reference Level 2 Sw2
with 12 switches to give 49 symmetric levels in the output sine wave Level 3 Sw3
voltage. DVR
Vref
Logic Drive
Figure 3 shows the output waveform. MLI topology has been compensation comparators
circuits
circuits
presented in [28]. method
The number of levels in the inverter output waveform (N) is
given by:
Sw12
N=2(V1+V2+V3+V4)/V+1 (1)
Where (V1) is the value of the first DC voltage source. Level 49
Where V1=V, V2=2V, V3=7V, V4=14V and the maximum Fig. 4 The block diagram of the MLI control system
peak value of the output voltage is
Vmax=V1+V2+V3+V4=24V 3. CONTROL OF THE DVR SYSTEM
and according to (1), the number of levels N is: The DVR control system is the brain in the DVR system.
N=2(V+2V+7V+14V)/V+1 =49 levels This part is the most important part, where has ability
start/stop operation DVR system by send/not send the
Vout reference signal to the switching pulse system as shown in
figure 7.
The proposed compensation method achieves balanced
three-phase load voltages with minimum real power
S4 S5 S6 S10 S11 S12 injection under balanced or unbalanced voltage
disturbances [27]. The control system operates once the
voltage disturbance occurs.
V1 V2 V3 V4 Figure 5 shows the compensation method when the
distribution system is operating at supply-voltage (Vpre-
S1 sag) and this voltage is changed to (V1) due to any fault.
S2 S3 S7 S8 S9 DVR injects the suitable voltage value (VDVR) to keep the
Fig. 2 49-level single phase MLI.
magnitude of the load voltage (V2) at the same value before
the fault occurs and always access to balance three phase
voltages, the active power of supply for one phase (P phase)
is:

Pphase =V1 IL cos(Ψ) (2)

Ψ = ∠V1 –∠IL (3)

Ψ=ФL –(∠V2 –∠V1 )=ФL –(θ2F –θ1 )= ФL –θ2F +θ1 (4)

Fig. 3 Output waveform of 49 levels MLI V2

After generation the reference signal by the compensation
method, the switching signals can be generated through three ϴ2F
steps, comparators, logic circuit and drive circuits as shown in ФL VDVR
ϴ1

Figure 4. The comparators divide the reference signal into V1

number of levels. This number equals the number of levels
required in the output waveform. The comparators transfer
from a level to the next when the reference sine wave reaches
to mid-value between the two levels. The outputs of the
comparators are considered as inputs to logic circuits which
generate the pulses according to the switches required to be on
for each level. Then, drive circuits are required to make pulses
suitable for switches. The total harmonic distortion (THD) in
the this MLI is very low as a result, Thus the filter unit in the
conventional DVR is unnecessary in the proposed DVR.
Ψ
IL V pre-sag
Fig. 5 Single phase phasor diagram to compensation method.
Where IL is the load current, V2 is the magnitude of the load
voltage, ФL is the load power factor angle, θ2F is the angle
between the load voltage after compensation and the load
voltage before disturbance and θ1 is the angle between the
source voltage after disturbance and the source voltage
before disturbance.

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 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)

By applying this compensation method for three phases, both

the load real power (PL) and the real power of the distorted
supply voltages (PS ) can be stated as follows:
z y
PL=3V2ILcos ФL (5)
β
PS =V1a IL cos(Ψa )+V1b IL cos(Ψb )+V1c IL cos (Ψc ) (6) x
Where; V1a, V1b, and V1c are magnitudes of the supply voltages; Fig. 6
Ψa, Ψb and Ψc are the angles between the three phase currents
and three phase voltages respectively. From Eqs. (15) to (18) thus,
From eqs. (5) and (6) then:
3V2 cos(ФL )= cos(ФL –θzero )z cos β – sin(ФL –θzero )z sin β
PS =V1a IL cos(ФL –θ2F +θ1a )+V1b IL cos(ФL –θ2F +θ1b ) = cos(ФL –θzero +β)z (19)
+V1c IL cos(ФL –θ2F +θ1c ) (7)
Assume V2 = 1 as a perunit, then
Where θ1a, θ1b and θ1c are the angles between the source voltage θzero =ФL +β– cos-1 [ 3cos(ФL )⁄z ] (20)
after disturbance and the source voltage before disturbance for
each phase. The active power injected by the DVR system in to Eq. (20) leads to the following condition:
the distribution system can be expressed as:
PDVR =PL –PS (8) 3cos(ФL )
α= ≤1 (21)
Z
The DVR real power depends on 𝜃2𝐹 that is the salient The voltage disturbance is compensated by reactive power only
concept of the compensation strategy. This method of and without inject any active power if 𝛼 ≤ 1 is satisfied.
compensation satisfies balanced three-phase load side voltages.
This strategy is classified in two modes. B. Minimum active power injection
This mode is used when α > 1. The mode control in this case
A. No real power injection. makes the DVR operates in the minimum active power mode. The
load-side voltage (V2) is modified to one per unit and phase angle
In this mode the DVR active power is zero. Thus, θ 2F θ2F changed to θmin . To determine θmin , will differentiate PDVR
changed to θzero at PDVR = 0 with respect to θmin .
from (7) then 𝑃𝐿 = 𝑃𝑆 (9) And from (2), (7) and (8)
and by applying [cos(A + B) = cos(A) cos(B) – sin(A) sin(B)]
on Eq.7. thus ∂PDVR
=0–IL [V1a sin(ФL –θmin +θ1a )+V1b sin(ФL –θmin +θ1b )
∂θmin
PS =IL [[V1a cos(ФL –θ2F ) cos(θ1a ) +V1b cos(ФL – θ2F ) cos(θ1b ) +V1c sin(ФL –θmin +θ1c ) (22)
+V1c cos(ФL –θ2F ) cos(θ1c ) ]–[V1a sin(ФL –θ2F ) sin(θ1a )
+V1b sin(ФL –θ2F )sin(θ1b )+V1c sin(ФL –θ2F ) sin(θ1c )]] (10) And from [sin(A + B) = sin(A) ∗ cos(B) + cos(A) ∗ sin(B)] (23)
Then:
Simplifying (10) to:
[V1a sin(ФL –θmin ) cos(θ1a ) +V1b sin(ФL –θmin )cos(θ1b )+V1c
PS =IL [[(cos(ФL –θ2F )(V1a cos(θ1a ) +V1b cos(θ1b ) +V1c cos(θ1c ) ) ] sin(ФL –θmin ) cos(θ1c )]+[V1a cos(ФL –θmin ) sin(θ1a ) +V1b
–[(sin(ФL –θ2F )(V1a sin(θ1a ) +V1b sin(θ1b ) +V1c sin(θ1c ) ) ]] (11) cos(ФL –θmin ) sin(θ1b )+V1c cos(ФL –θmin ) sin(θ1c )]=0 (24)

Eq. (11) can be written in the form: From (13,14) Thus,

PS =IL ( cos(ФL –θ2F )x–sin(ФL –θ2F )y ) (12) sin(ФL –θmin )x- cos(ФL –θmin )y=0 (25)

tan(ФL –θmin )= –y⁄x (26)

Where
x=V1a cos(θ1a ) +V1b cos(θ1b ) +V1c cos(θ1c ) (13)
And from (16) then:
y=V1a sin(θ1a ) +V1b sin(θ1b ) +V1c sin(θ1c ) (14)
tan(ФL –θmin )=–tan(β) (27)
Eqs. (2), (9), and (12) lead to the following equation: Thus,
θmin =ФL + β (28)
3V2 IL cos(ФL )=IL ( cos(ФL –θzero )x–sin(ФL –θzero )y ) (15)
Eq. (20) gives the value of θmin , The minimum active power
And from Fig. (6) injected by DVR can be calculated from the following equation.
β= tan-1 ( y⁄𝑥 ) (16)
𝑥 = 𝑧 ∗ 𝑐𝑜𝑠 𝛽 (17)
𝑦 = 𝑧 ∗ sin 𝛽 (18)

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 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)

PDVR =IL [3V2 cos(ФL )–V1a cos(θ1a –β )–V1b cos(θ1b –β ) A. Three-phase balanced voltage sag mitigation
Figure 8 Shows the waveforms of the three-phase
–V1c cos(θ1c –β )] (29)
voltages at the supply side, the DVR output voltages and the
waveforms of the three-phase voltages at the load side after
4. GENERATION THE REFERENCE SIGNALS compensation when the distribution system is subjected to
The reference signals required to switching system of MLI three-phase balanced fault, that cause a small voltage sag to
can be generated from the difference between the 89.7% for a interval of 0.2 sec from t=0.2 sec until t=0.4
uncompensated three-phase voltages of the source side and sec. Figure 9 shows the pu values of the source and the load
three-phase waveform which generated with frequency 50 side voltages. These results clear the accurate performance
for the DVR system where the DVR inject the appropriate
HZ, 1 per unit and phase angle θ2F such that: amount of missing voltage to recover the load voltage to its
nominal voltage value during the sag event. The
v̅2a-star =1∠θ2F
instantaneous active and reactive powers are shown in
{ v̅2b-star =1∠(θ2F –120) (30)
v̅2c-star =1∠(θ2F +120) figure 10. The DVR operates with no active power
injection (no real power mode) and the reactive power
injected is 0.342 MVAR during the sag event.
Then the reference signals which in modulation
10
technique as follows:

Supply voltages (kv)

5
v̅a_ref = v̅2a_star –v̅1a
{ v̅b_ref = v̅2b_star –v̅1b (31) a
v̅c_ref = v̅2c_star –v̅1c 0 b
c

vL -5
power
α <=1 No real Va,b,c_ref.
iL factor power
-10
V1a injection. 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec)

v1a
(a)
ϴ1a
8
ϴzero
Calculation Generation of 6
of RMS V1b Calculation of Generation of reference
v1b 4
values and x, y and z Calculate α Va_star, Vb_star, voltages va, vb,
phase angle ϴ1b (13), (14), (17), (21) Vc_star vc 2
Vdvr(kv)

for three (18) (30) (31) 0

v1c phases
V1c ϴmin. -2

-4

ϴ1c Minimum -6
active v1a v1b v1c -8
power 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
α >1 injection Time(sec)
(b)
Fig. 7 The block diagram of the proposed DVR control system. 15

10
5. SIMULATION RESULTS AND DISCUSSION
Load voltage(kv)

5
The testing of the proposed DVR system was done by
considering different fault types which causes sags and swells 0
such as three-phase fault (symmetrical fault) and line to ground
-5
fault (unsymmetrical fault). The PSCAD/EMTDC simulation
package is used to implement the distribution system. The -10
parameters of proposed DVR system are given in table I.
-15
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Table I System parameters. Time(sec)
Supply Three phase 11kv (RMS,
line to line voltage), 50hz
(c)
Load P=1.35MW, Pf=82.67 lag Fig. 8. (a)Supply voltages. (b)DVR voltages. (c)Load voltages.
Respectively, in case the small three phase balanced voltage sag.
First cell DC source of the V1=310 volte
MLI

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 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)

2 15
data1
data2
10
Perunit voltages(PU)

1.5

Load voltages(kv)
5
1
0

0.5 -5

-10
0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec) -15
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Fig. 9 Perunit values for load side and source side voltages during small Time (sec)
three phase balanced voltage sag.
(c)
Fig. 11 High balanced three phase voltage sag (a)Supply voltages.
0.5 (b)DVR voltages. (c)Load voltages.
P
0.4 Q 2
Supply
P(kw) and Q(kvar)

0.3
Load

Perunit voltages(PU)
1.5
0.2

0.1
1
0

-0.1
0.5

-0.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec) 0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Fig. 10 Active and Reactive DVR output powers during small three phase Time (sec)
balanced voltage sag. Fig. 12 Per-unit values for load side and source side voltages during deep
three phase balanced voltage sag.
In case of deep voltage sag occurs, the DVR compensates 1.2
P
the deep voltage sag by operating in the minimum real power 1
Q

injection mode. Figure11 shows the waveforms of the three-

P(MW) and Q(MVAR)

phase voltages at the supply side, the injected voltages by DVR 0.8

system and the waveforms of the three-phase voltages at the 0.6

load side after compensation when a three-phase balanced deep 0.4

voltage sag occurs in the distribution system. Figure 12shows
0.2
the per unit value for the load and supply side voltages which
shows that the voltage sag is 0.493 pu. The DVR active power 0

is 517.5 KW (minimum real power injection mode) and -0.2

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
reactive power is 878 KVAR as shown in figure 13. Time(sec)

10
Fig. 13 Active and Reactive DVR output powers during deep three phase
balanced voltage sag.

5 B. Three-phase unbalanced voltage sag mitigation

Supply voltages(kv)

a
Single line to ground (SLG) fault is the most faults
0 b which causes unbalanced voltage sag. The system is
c
subjected to phase 'a' to ground fault, this fault makes
-5 voltage sag 50% in phase 'a' for 0.2 sec. from t=0.2 till t=0.4.
Figure 14 demonstrates that the DVR recovers the load
-10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
voltages to the pre-fault value by injecting the required
Time(sec) voltages in all phases to maintain the three phases balanced.
(a) The line voltages Vca and Vab will be affected whereas Vbc
10 will not.
10

5
DVR voltages(kv)

5
Supply voltages(kv)

0 a
0 b
c

-5
-5

-10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec) Time(sec)
(b) (a)

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 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)

8 C. Voltage swell mitigation

6
The swell occurs when the large loads or application of large
4
capacitor banks removed suddenly. The voltage swell is not
DVR voltages(kv)

2
common as the voltage sag.
0
The condition {α= 3 cos (ФL )⁄Z ≤1 } can be applied for
-2 voltage swells. Thus, the DVR system may not absorb active
-4 power during swell compensate. Figure 17 shows the
-6 waveforms of a three-phase voltages at the supply side, the
-8
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
DVR output voltages and the waveforms of the three-phase
Time(sec)
voltages at the load side during the three-phase balanced
(b) voltage swell to 134.8 % for interval 0.2 sec from t=0.2 sec.
15
until t=0.4 sec. Figure 18 shows the source side and load side
10 per unit voltages, this figure confirms that the load voltage is
close to one per-unit. Figure 19 shows that the swell is
Load voltages(kv)

5
compensated without passing active power through the DVR.
0 The reactive power absorbed by DVR is 582.2 KVAR.
-5
15

-10
10

-15

Supply voltages(kv)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 5
Time(sec)
(c) a
0
Fig. 14 Three phase voltages through unbalanced voltage sag(SLG fault). (a) b
c
Waveforms of the supply voltages. (b) Waveforms of the DVR voltage. (c)
-5
Waveforms of the Load voltage.
2 -10
Supply
Load -15
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
1.5
Perunit voltages(PU)

Time(sec)
(a)
1 10

0.5 5
DVR voltages(kv)

0 0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec)
Fig. 15 Perunit values for load side and source side voltages during -5
unbalanced voltage sag (SLG fault).
1.2
P -10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
P(MW)and Q(MVAR) powers

1 Q Time(sec)

0.8
(b)
15
0.6
10
0.4
Load voltages(kv)

0.2
5

0 0

-0.2 -5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec)
-10
Fig. 16 Active and Reactive DVR output powers during unbalanced
voltage sag (SLG fault).
-15
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec)
Figure 15 demonstrates that the system succeeds in
(c)
regulating the load side voltage to the nominal value with the Fig. 17 Three phase waveforms during voltage swell. (a)supply voltage.
DVR running in control mode which achieves zero injection (b)DVR voltage. (c)Load voltage.
real power and reactive power 900 KVAR as shown in Figure
16.

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 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)

2
Supply Table II Experimental System parameters
Load
Supply Phase voltage 50V/50HZ
1.5
Perunit voltages(PU)

(peak value) Vs
1
Load Inductance (LL) 50 mH
Load Resistance (RL) 20 ohm
0.5 Switching frequency (Fs) 10 KHZ
Last cell DC source of 42 V
0
0 0.05 0.1 0.15 0.2 0.25
Time(sec)
0.3 0.35 0.4 0.45 0.5 the MLI
Fig. 18 Per-unit values for load side and source side voltages during voltage swell.
0.6
P
Figure 22 shows the voltage source with unbalanced
P(MW) and Q(MVAR) powers

0.4 Q

0.2
voltage sag, where the voltage sag occurs in one phase. The
0
interval of the 20% voltage sag continues for 12 cycle. As
-0.2
shown in figure 23, The load voltage is constant at the
-0.4

-0.6
nominal value where the proposed DVR system succeeded
-0.8
in voltage sag compensation. Figure 24 shows the voltage
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time(sec) supply with deep voltage sag 54% for 17 cycles. The load-
Fig. 19 Active and Reactive DVR output powers during voltage swell.
side voltage is constant at 50 volt (peak) with deep sag
6. EXPERIMENTAL RESULTS occurs as shown in figure 25. All experimental results are
saved by dSPACE and sketched by MATLAB soft wear.
The experimental verification is achieved by constructing the
proposed DVR prototype. As shown in figure 20, the control
system of the proposed DVR is tested with the help of dSPACE
Supply voltage (V)
50
(DS1104) board. The sag is implemented by inserting a series
resistance (Rs). The voltage sag level in the prototype is
determined by the resistance (Rs) value. The prototype of the
DVR is executed to compensate only one phase as shown in 0
figures 24, due to the insufficient possibilities in laboratory.
Table 2 shows the values of all parts of the DVR prototype. The
construction of the prototype in laboratory is implemented by -50
three phase supply, resistances, inductances, DC sources,
0 0.2 0.4 0.6
IGBTs, voltage sensors, current sensors, interface circuits and
Time (sec)
computer with dSPACE as shown in figure 21.
Vc v1c Rlc Llc Fig. 22 The source side voltage with sag 20% for 12 cycles.
Vb Rlb Llb
v1b

Va Rs Rla Lla
50
Load voltage (V)

v1a MLI with 12

switch
Switch

Voltage Gate drive 0

sensors

Personal
DSPACE
DS1104 computer -50
0 0.2 0.4 0.6
Fig. 20 Experimental layout DVR system using DSP-DS1104 board. Time (sec)
Fig. 23 The load side voltage after compensation.
Supply voltage (V)

50

-50
0 0.2 0.4 0.6 0.8
Time (sec)
Fig. 21 The experimental system of the proposed DVR Fig. 24 The source side voltage with sag 54% for 17 cycles.

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 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE)

Transactions on Power Delivery 31.3 (2016): 1160-1167.

[7] Bollen, Math HJ, and Math HJ Bollen. Understanding power quality
50
Load voltage (V)
problems: voltage sags and interruptions. Vol. 445. New York: IEEE press,
2000.
[8] Mahalakshmi, V., and S. Ramamoorthy. "A modified three phase four wire
UPQC topology with reduced dc link voltage rating." Advances in Natural
0 and Applied Sciences 10.14 (2016): 156-161.
[9] Moradlou, Majid, and Hamid R. Karshenas. "Design strategy for optimum
rating selection of interline DVR." IEEE Transactions on Power Delivery
26.1 (2011): 242-249.
-50 [10] Sasitharan, S., and Mahesh K. Mishra. "Constant switching frequency band
controller for dynamic voltage restorer." IET power electronics 3.5 (2010):
0 0.2 0.4 0.6 0.8 657-667.
Time (sec) [11] Ajaei, Firouz Badrkhani, et al. "A fast and effective control scheme for the
dynamic voltage restorer." IEEE transactions on power delivery 26.4 (2011):
2398-2406.
Fig. 25 The load side voltage after compensation.
[12] Kanjiya, Parag, Bhim Singh, and Ambrish Chandra. "“SRF theory revisited”
to control self supported dynamic voltage restorer (DVR) for unbalanced and
nonlinear loads." Industry Applications Society Annual Meeting (IAS), 2011
7. CONCLUSION IEEE. IEEE, 2011.
[13] Santos, Welflen Ricardo Nogueira, et al. "The transformerless single-phase
universal active power filter for harmonic and reactive power compensation."
In this paper, a transformer-less DVR system with a new IEEE Transactions on Power Electronics 29.7 (2014): 3563-3572.
construction is presented, where an energy optimized scheme [14] Santos, Welflen Ricardo Nogueira, et al. "The transformerless single-phase
universal active power filter for harmonic and reactive power compensation."
to compensate the different voltage disturbances is considered. IEEE Transactions on Power Electronics 29.7 (2014): 3563-3572.
The DVR system based on the MLI uses only 12 switches in [15] Nielsen, John Godsk, and Frede Blaabjerg. "A detailed comparison of system
topologies for dynamic voltage restorers." IEEE Transactions on Industry
single phase system. The DVR was compensated the load side Applications 41.5 (2005): 1272-1280.
[16] Babaei, Ebrahim, and M. Farhadi Kangarlu. "A new topology for dynamic
voltage to a desired value with operation in either no real power voltage restorers without dc link." Proc. ISIEA (2009): 1009-1014.
injection mode or minimum real power injection mode. The [17] Agrawal, Rekha, and Shailendra Jain. "An Improvisation of CCS-MLI
Topology in Terms of Maximization of Levels." IETE Journal of Research
major advantages of the proposed DVR system are the 63.5 (2017): 651-661.
reduction of the total cost, size, fast response and accurate [18] dynamic voltage restorer using transformer coupled H-bridge converters."
IEEE transactions on power electronics 21.4 (2006): 1053-1061.
compensating, with optimum energy. The PSCAD/EMTDC [19] Sadigh, A. Khoshkbar, et al. "Dynamic voltage restorer based on stacked
software results show that the proposed DVR system multicell converter." Industrial Electronics & Applications, 2009. ISIEA
2009. IEEE Symposium on. Vol. 1. IEEE, 2009.
compensates the voltage disturbances such as voltage [20] Jazayeri, M., and H. Abdollahzadeh. "A novel DVR control system design
for compensating all types of voltage sags based on pre-fault method."
sages and swells. The experimental results confirm the European Journal of Scientific Research 33.1 (2009): 70-85.
[21] Vilathgamuwa, D. Mahinda, AAD Ranjith Perera, and San Shing Choi.
ability of the proposed DVR to compensate the voltage "Voltage sag compensation with energy optimized dynamic voltage restorer."
IEEE Transactions on Power Delivery 18.3 (2003): 928-936.
sages at different values for voltage sag with THD in the [22] Marei, Mostafa I., Ehab F. El-Saadany, and Magdy MA Salama. "A new
nominal range as shows in table 3. approach to control DVR based on symmetrical components estimation."
IEEE Transactions on Power Delivery 22.4 (2007): 2017-2024.
[23] Teke, Ahmet, et al. "Dynamic Voltage Restorers: A Literature Review."
Table III the THD for the load voltage at 20% and 54% sag in the supply Faculty of Electrical Engineering University Technology Malaysia 12.1
voltage (2010): 7-13.
The load voltage Voltage sag 20% Voltage sag 54% [24] Tiwari, H. P., and Sunil Kumar Gupta. "Dynamic voltage restorer against
voltage sag." International journal of innovation, management and
THD in the supply in the supply technology 1.3 (2010): 232.
voltage voltage [25] Chowdary, D. Deepak, and G. V. Kumar. "Mitigation of voltage sags in a
distribution system due to three-phase to ground fault using DVR." (2010).
Simulation 1.6% 1.75% [26] Woodley, Neil H., L. Morgan, and Ashok Sundaram. "Experience with an
Experimental 3.03% 3.46% inverter-based dynamic voltage restorer." IEEE Transactions on Power
Delivery 14.3 (1999): 1181-1186.
[27] Marei, Mostafa I., Ayman B. Eltantawy, and Ahmed Abd El-Sattar. "An
energy optimized control scheme for a transformerless DVR." Electric Power
8. References Systems Research 83.1 (2012): 110-118.
[28] Harbi, I. A., Azazi, H. Z., Lashine, A. E., & Elsabbe, A. E. (2018). A higher
levels multilevel inverter with reduced number of switches. International
[1] Elnady, Amr, and Magdy MA Salama. "Mitigation of voltage disturbances Journal of Electronics, 105(8), 1286-1299.
using adaptive perceptron-based control algorithm." IEEE transactions on [29] Satputaley, R. J., & Borghate, V. B. (2017). Performance analysis of DVR
power delivery 20.1 (2005): 309-318. using “new reduced component” multilevel inverter. International
[2] Sillapawicharn, Yutthachai. "An improvement of a fast-single-phase voltage Transactions on Electrical Energy Systems, 27(4), e2288.
sag detection method under distorted grid voltages." Electrical
Engineering/Electronics, Computer, Telecommunications and Information
Technology (ECTI-CON), 2016 13th International Conference on. IEEE,
2016.
[3] F II, I. "IEEE recommended practices and requirements for harmonic control
in electrical power systems." New York, NY, USA (1993).
[4] Sadigh, A. Khoshkbar, and K. M. Smedley. "Fast and precise voltage sag
detection method for dynamic voltage restorer (DVR) application." Electric
Power Systems Research 130 (2016): 192-207.
[5] Maniraj, Bashampelli, K. Jaghannath, and D. Kumara Swamy. "Control of
Reduced-Rating Dynamic Voltage Restorer with a Battery Energy Storage
System." Imperial Journal of Interdisciplinary Research 2.9 (2016).
[6] Shahabadini, Masoud, and Hossein Iman-Eini. "Improving the performance
of a cascaded H-bridge-based interline dynamic voltage restorer." IEEE

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