CSSE4010 Digital System Design

Lecture 4
ARITHMETIC CIRCUITS

ITEE, UQ 1
 Recall Number Representations
❑ Unsigned vs Signed representation
❑ Signed:
❑ Signed-magnitude
❑ 1’s complement (diminish radix complement)
❑ 2’s complement (radix complement)
❑ In binary, we use 2’s complement:
❑ Unique zero
❑ No end around carry
❑ A – B is performed as A + (-B)
❑A>B→
❑A<B→

ITEE, UQ 2
 Recall Number Representations
❑ Status of addition operation A + B
❑ N:
❑ Z:
❑ C:
❑ V:
❑ Overflow detection in unsigned

❑ Overflow detection in 2’s complement

❑ What can be done to minimise the error due to overflow?

ITEE, UQ 3
 4-bit twos-complement examples

(1) 0101 - 0010 (5 - 2): (3) -0101 - 0010 (-5 - 2):

0101 1011 (= -0101*)
+ 1110 (= -0010*) + 1110 (= -0010*)
= 10011 (discard carry) = 11001 (discard carry ).
0011 1001 (= -0111*)
Result means -7.
(2) 0010 - 0101 (2 - 5):
0010
+ 1011 (= 0101*)
(4) 0101 + 0010 (5 + 2):
This is trivial, as no conversions
= 1101 (= 0011*).
are required.
No carry to discard. The result is 0111 (= 7).
Result means -3.

ITEE, UQ 4
 Overflow
0 Cin 1 Cin
-3 1101 +5 0101
+ -6 + 1010 + +6 + 0110
-9 1 0111 = +7 +11 0 1011 = -5

0 Cin 1 Cin
-8 1000 +7 0111
+ -8 + 1000 + +7 + 0111
-16 1 0000 = +0 +14 0 1110 = -2

Overflow can be detected by "XORing" Cin and Cout of the MSB

Overflow = Cin + Cout
ITEE, UQ 5
 Half Adder
Binary addition table :
S = A xor B
sum carry C = AB
bit bit
A
A B S C S
B
0+0 0 0
C
0+1 1 0
1+0 1 0
To add numbers with more than 1 bit
1+1 0 1
we need to add carry to An Bn
We need an adder with 3 inputs.

ITEE, UQ 6
 Full Adder
A B Ci
TRUTH TABLE Half adder

A B Ci CA CB Ci+1

0 0 0 0 0 0 Half adder
CA
0 0 1 0 0 0
0 1 0 0 0 0
CB
0 1 1 0 1 1
1 0 0 0 0 0
Ci+1 Si
1 0 1 0 1 1
1 1 0 1 0 1 Ci+1 = CA or CB Si = A + B + Ci
1 1 1 1 0 1
Ci+1 = AB + Ci (A + B)
ITEE, UQ 7
 4-bit ripple carry adder
A3 B3 A2 B2 A1 B1 A0 B0

Cin=‘0’

FA FA FA FA 2 gate delays per bit

C4 N bit ripple carry adder
C3 C2 C1
→ 2N gate delays

OF S3 S2 S1 S0
(overflow)

ITEE, UQ 8
 4-bit adder/subtractor
A3 B3 A2 B2 A1 B1 A0 B0
XOR gate is a
"controlled inverter"

B Sel Xor Sel

0 0 0
0 1 1 = B’
1 0 1 FA FA FA FA
1 1 0 = B’
C4

Sel(ect) input also C3 C2 C1

controls the "add one"

step.
OF S3 S2 S1 S0
(overflow)

ITEE, UQ 9
 4-bit Adder/Subtractor with Saturation

ITEE, UQ 10
 Ripple Carry Chain
The worst case is when C0
A + B = 1111 + 0001 since each bit sum
generates carry-out after arrival of A0 S0 @2
carry-in. The final carry-out is delayed 0
B0
by all the stages of carry chain. C1

A1 S1 @3
@0 A S @n +1
OR 1
@0 B OR B1 C2
@n Ci
A2 S2 @5
sum stage B2
2
C3
@0 A @1 A3
XOR S3 @7
@0 B AND @n + 1 3
B3
C4
@n Ci OR CO
@n + 2
@0 A AND
@0 B @1

carry stage carry chain

ITEE, UQ 11
 Ripple Carry Chain
The worst case is when
Set to 0
A + B = 1111 + 0001 since each bit sum
generates carry-out after arrival of A0 = 1 S0
carry-in. The final carry-out is delayed 0
by all the stages of carry chain. B0 = 1 C1

@0 A 1
OR S @n +1 1
@0 B OR 0
@n Ci
1
sum stage 2
0
@0 A XOR
A3 = 1
@0 B AND @n + 1 3
B3 = 0
@n Ci OR CO
@n + 2
@0 A AND
@0 B @1 0 2 4 6 8 time
carry stage carry chain
ITEE, UQ 12
 Ripple Carry Chain
The worst case is when
Set to 0
A + B = 1111 + 0001 since each bit sum
generates carry-out after arrival of 1 0 @2
carry-in. The final carry-out is delayed 0
by all the stages of carry chain. 1 1 @2

1 S1 @3
@0 A S @n +1
OR 1
@0 B OR 0 C2
@n Ci
1
sum stage 2
0
@0 A XOR
1
@0 B AND @n + 1 3
0
@n Ci OR CO
@n + 2
@0 A AND
@0 B @1 0 2 4 6 8 time
carry stage carry chain
ITEE, UQ 13
 Ripple Carry Chain
The worst case is when
0
A + B = 1111 + 0001 since each bit sum
generates carry-out after arrival of 1 0 @2
carry-in. The final carry-out is delayed 0
by all the stages of carry chain. 1 1 @2

1 0 @3
@0 A S @n +1
OR 1
@0 B OR 0 1 @4
@n Ci
1 S2 @5
sum stage 2
0 C3 @6
@0 A XOR
1
@0 B AND @n + 1 3
0
@n Ci OR CO
@n + 2
@0 A AND
@0 B @1 0 2 4 6 8 time
carry stage carry chain
ITEE, UQ 14
 Ripple Carry Chain
The worst case is when
0
A + B = 1111 + 0001 since each bit sum
generates carry-out after arrival of 1 0 @2
carry-in. The final carry-out is delayed 0
by all the stages of carry chain. 1 1 @2

1 0 @3
@0 A S
OR 1
@0 B OR 0 1 @4
Ci@n +1
@n Ci
1 0 @5
sum stage 2
0 1 @6
@0 A XOR
1 S3 @7
@0 B AND @n + 1 3
0
C4 @8
@n Ci OR CO
@0 A Ci@n + 2
AND
@0 B @1 0 2 4 6 8 time
carry stage carry chain
ITEE, UQ 15
 Ripple Carry Chain
The worst case is when
B + A = 1111 + 0001 since each bit sum 0
generates carry-out after arrival of B0 = 1 0 @2
carry-in. The final carry-out is delayed 0
by all the stages of carry chain. A0 = 1 1 @2

1 0 @3
@0 A XOR S @n +1
XOR
1
@0 B 0 1 @4
@n Ci
1 0 @5
sum stage 2
0 1 @6
@0 A XOR B3 = 1 0 @7
@0 B AND @n + 1 3
A3 = 0
1 @8
@n Ci OR CO
@n + 2
@0 A AND
@0 B @1 0 2 4 6 8 time
carry stage carry chain
ITEE, UQ 16
 Carry Look Ahead
A B Ci

TRUTH TABLE
HA
A B Ci CA CB Ci+1 C S
CA

0 0 0 0 0 0
0 0 1 0 0 0 HA
0 1 0 0 0 0 Propagate C S
0 1 1 0 1 1 CB
1 0 0 0 0 0
1 0 1 0 1 1 Ci+1 = CA or CB
Si = A + B + Ci
1 1 0 1 0 1
1 1 1 1 0 1 Ci+1 = AB + Ci (A + B)
Generate
ITEE, UQ 17
 Carry Look Ahead Method
Ai Pi @1delay
XOR
Gi = Ai Bi Bi
Si @2 delay
XOR
Pi = A i + Bi Ci
Gi @1delay
AND
Si = A i + Bi + Ci = Pi + Ci

Ci+1 = AiBi + Ci(Ai + Bi) = Gi + CiPi

C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

ITEE, UQ 18
 4-bit CLA Adder
A3 B3 A2 B2 A1 B1 A0 B0

A B A B A B A B
Partial Full Partial Full Partial Full Partial Full
Adder Adder Adder Adder
S P G C S P G C S P G C S P G C
S3 S2 S1 S0

P3 G3 C3 P2 G2 C2 P1 G1 C1 P0 G0
Carry Look-ahead Logic
C4 C0

The CLA logic becomes overly complex for more than

4 bits. High fan-in gates.
ITEE, UQ 19
 16-bit CLA+Ripple Carry Adder
A15-A12 B15-B12 A11-A8 B11-B8 A7-A4 B7-B4 A3-A0 B3-B0
4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits

A B A B A B A B
4-bit partial 4-bit partial 4-bit partial 4-bit partial
C16 full adders C12 full adders C8 full adders C4 C0
full adders

4-bit CLA 4-bit CLA 4-bit CLA 4-bit CLA

logic logic logic logic

S15-S12 S11-S8 S7-S4 S3-S0

How can you improve this?

ITEE, UQ 20
 16-bit CLA with Group CLA
A3-A0 B3-B0 The 4-bit CLA adder produces 4 generate
4 bits 4 bits and propagate terms – i.e. G0-3 and P0-3
A B Define the group propagate and generate
4-bit partial
terms as
C4 C0 PG=P3P2P1P0
full adders
GG=G3+P3G2+P3P2G1+P3P2P1G0
4-bit CLA
logic Then
C4 = GG0+PG0C0
C8=GG1+PG1GG0+PG1PG0C0
S3-S0 C12=GG2+PG2GG1+PG2PG1GG0+PG2PG1PG0C0
C16=GG3+PG3GG2+PG3PG2GG1+
PG3PG2PG1GG0+PG3PG2PG1PG0C0
ITEE, UQ 21
 A15-12 B15-12 A11-8 B11-8 A7-4 B7-4 A3-0 B3-0

A B A B A B A B
4-bit CLA 4-bit CLA 4-bit CLA 4-bit CLA
Adder Adder Adder Adder
S P G C S P G C S P G C S P G C
S15-12 S11-8 S7-4 S3-0

PG3 GG3 C12 PG2 GG2 C8 PG1 GG1 C4 PG0 GG0

C16 Group Carry Look-ahead Logic C0

ITEE, UQ 22
 Carry Select Adder
bits 0 - 3 bits 4 - 7 bits 4- 7
4 4 4 4 4 4
0 1
C0 A B C4 A B C8 A B C8 @8
C C C 1 C8
@0 @8
0 @11

2:1 Mux
@8

S0 S1 S2 S3 S4 S5 S6 S7 @11

ITEE, UQ 23
 1 bit Comparators

A B A>B A<B A=B A>=B A=<B

0 0 0 0 1 1 1
0 1 0 k 1 k 0 0
k k 1
1 0 1 0 0 1 0
1 1 0 0 1 1 1
A B A&B’ A’&B A + B A+B A’+B

ITEE, UQ 24
 Comparator Design Example
Design a comparator A > B when A and B are 3 digit numbers

A > B = A2A1A0 > B2B1B0 =

ITEE, UQ 25
 Comparator Design Example
Design a comparator A > B when A and B are 3 digit numbers

A > B = A2A1A0 > B2B1B0 =

(A2>B2) +

ITEE, UQ 26
 Comparator Design Example
Design a comparator A > B when A and B are 3 digit numbers

A > B = A2A1A0 > B2B1B0 =

(A2>B2) + (A2=B2)(A1>B1) +

ITEE, UQ 27
 Comparator Design Example
Design a comparator A > B when A and B are 3 digit numbers

A > B = A2A1A0 > B2B1B0 =

(A2>B2) + (A2=B2)(A1>B1) + (A2=B2)(A1=B1)(A0>B0) =

ITEE, UQ 28
 Comparator Design Example
Design a comparator A > B when A and B are 3 digit numbers

A > B = A2A1A0 > B2B1B0 =

(A2>B2) + (A2=B2)(A1>B1) + (A2=B2)(A1=B1)(A0>B0) =
A2&!B2 + ( A2+ B2)&A1&!B1 + (A2+ B2)&(A1+ B1)&A0&!B0
A0 A0>B0
AND
!B0
A1 A1=B1
OR AND A2A1A0 > B2B1B0
B1 OR

A2 A2=B2
OR
B2 AND

A1 A1>B1 A2
AND AND A2>B2
!B1 !B2

ITEE, UQ 29
 Comparator Design Example
Design a comparator A > B when A and B are 3 digit numbers

A > B = A2A1A0 > B2B1B0 =

(A2>B2) + (A2=B2)(A1>B1) + (A2=B2)(A1=B1)(A0>B0) =
A2&!B2 + ( A2 + B2)&A1&!B1 + (A2 + B2)&(A1+ B1)&A0&!B0
A0 A0>B0
AND
!B0
A1 A1=B1
OR AND A2A1A0 > B2B1B0
B1 OR

A2 A2=B2
OR
B2 AND

A1 A1>B1 A2
AND AND A2>B2
B1’ B2’

ITEE, UQ 30
 Comparator Design Example
Design a comparator A > B when A and B are 3 digit numbers

A > B = A2A1A0 > B2B1B0 =

(A2>B2) + (A2=B2)(A1>B1) + (A2=B2)(A1=B1)(A0>B0) =
A2&B2’ + !(A2 + B2)&A1&B1’ + !(A2 + B2)& (A1 + B1)’&A0&B0’
A0 A0>B0
AND
B0’
A1 A1=B1
OR AND A2A1A0 > B2B1B0
B1 OR

A2 A2=B2
OR
B2 AND

A1 A1>B1 A2
AND AND A2>B2
B1’ B2’

ITEE, UQ 31
 Alternative Comparator
Solution
Cout = A > B = A2A1A0 > B2B1B0 =
(A2>B2) + (A2=B2)(A1>B1) + (A2=B2)(A1=B1)(A0>B0)

ITEE, UQ 32
 Alternative Comparator
Solution
C = A > B = A2A1A0 > B2B1B0 =
(A2>B2) + (A2=B2)(A1>B1) + (A2=B2)(A1=B1)(A0>B0)
{ { {
Cout = (A2>B2) + (A2=B2) (A1>B1) +(A1=B1) (A0>B0) }}}

ITEE, UQ 33
 Alternative Comparator
Solution
Cout = A > B = A2A1A0 > B2B1B0 =
(A2>B2) + (A2=B2)(A1>B1) + (A2=B2)(A1=B1)(A0>B0)
{ { {
Cout = (A2>B2) + (A2=B2) (A1>B1) +(A1=B1) (A0>B0) }}}
C2out = (A2>B2) + (A2=B2){C1out}

C1out = (A1>B1) + (A1=B1){C0out}

C0out = (A0>B0) + (A0=B0) ){0}

Ci = (Ai > Bi) + (Ai = Bi) Ci-1

convert to Boolean operators

Ci = A & B’ + (A + B)’ & C= A&B’ + B’& C + A&C

ITEE, UQ 34
 Iterative Comparator
Ai Bi
Use single bit comparator modules
– start from the LSB
AND

– propagate the result to higher bits AND OR

– the output of the last comparator Ci AND

Ci+1
is the result of comparison.

A0 B0 A1 B1 A2 B2 A3 B3

AND AND
AND
C1 AND
C2 C3 C4
AND AND AND OR AND OR
A>B
OR OR

AND AND AND AND

ITEE, UQ 35
 Iterative Comparator
Ai Bi
Use single bit comparator modules
– start from the LSB
AND

– propagate the result to higher bits AND OR

– the output of the last comparator Ci AND

Ci+1
is the result of comparison.

A0 B0 A1 B1 A2 B2 A3 B3

AND AND
AND
C1 AND
C2 C3 C4
AND AND AND OR AND OR
A>B
OR OR

AND AND AND AND

ITEE, UQ 36
 Iterative Comparator
Ai Bi
Use single bit comparator modules
– start from the LSB
AND

– propagate the result to higher bits AND OR

– the output of the last comparator Ci AND

Ci+1
is the result of comparison.

A0 B0 A1 B1 A2 B2 A3 B3

AND AND
AND
C1 AND
C2 C3 C4
AND AND AND OR AND OR
A>B
OR OR

AND AND AND AND

ITEE, UQ 37
 Iterative Comparator
Ai Bi
Use single bit comparator modules
– start from the LSB
AND

– propagate the result to higher bits AND OR

– the output of the last comparator Ci AND

Ci+1
is the result of comparison.

A0 B0 A1 B1 A2 B2 A3 B3

AND AND
AND
C1 AND
C2 C3 C4
AND AND AND OR AND OR
A>B
OR OR

AND AND AND AND

ITEE, UQ 38
 Iterative Circuits
Iterative circuits are well suited to problems that can be solved
by a simple iterative algorithm:
Set i = 0 , C(i) to its ininial value
Use C(i) and In(i) to COMPUTE Out(i) and C(i+1)
REPEAT UNTIL i > no_of_stages
An iterative circuit "unwinds" the above loop by providing a
combinational circuit for each iteration.
Iterative circuits are easy to build but are slow.

In(0) In(1) In(n-1)

C(0) C(1) C(2) C(n-1) C(n)

module module module
0 1 n-1

Out(0) Out(1) Out(n-1)

ITEE, UQ 39
 Subtractor Based
Comparator
A3 B3 A2 B2 A1 B1 A0 B0

1
FA FA FA FA
C4
A<B
C3 C2 C1
A >= B
S3 S2 S1 S0
A <= B
NOR
NOR
A>B
A=B

ITEE, UQ 40
 A Simple 1 Bit ALU
Mode Code Operation Boolean Expression
M S0 S1 Output Carry Out

0 0 0 A - 1, if LSB Cin = 0,B=1 A + Cin A + Cin

0 0 1 A +1, if LSB Cin = 1,B=0 A + Cin A & Cin
A
0 1 0 A plus B plus Cin A + B + Cin Cin&(A + B) + A&B

0 1 1 A minus B, if LSB Cin = 1 A + B + Cin Cin&(A + B) + A&B

1 0 0 Transfer A A
1 0 1 Bit invert and Transfer A A
L
1 1 0 bitwise OR A + B x
1 1 1 bitwise AND A & B x

ITEE, UQ 41
 A Simple 1 Bit ALU
A B

1 0

Cout AND OR
11 10 01 00
OR
MUX
AND
Cin
OR
OR OR

AND

11 10 01 00 S0
MUX S1

0 Mux 1 M

Output
ITEE, UQ 42
 A Simple 4 Bit ALU
A3 B3 A2 B2 A1 B1 A0 B0

A B A B A B A B

Cout Cin Cout Cin Cout Cin Cout Cin C

Out MS Out MS Out MS Out MS 0
Mode
Select

S3 S2 S1 S0
ITEE, UQ 43
 Binary multiplication
multiplicand 1101 (13)
multiplier * 1011 (11)
1101
1101
0000
1101
10001111
128 + 8+4+2+1 = 143

ITEE, UQ 44
 Partial Product Acumulation
A3 A2 A1 A0
B3 B2 B1 B0

A3&B0 A2&B0 A1&B0 A0&B0

+ + +
A3&B1 A2&B1 A1&B1 A0&B1
+ + +
A3&B2 A2&B2 A1&B2 A0&B2
+ + + C1
A3&B3 A2&B3 A1&B3 A0&B3
C6 C5 C4 C3 C2

S7 S6 S5 S4 S3 S2 S1 S0
ITEE, UQ 45
 4 X 4 Combinational
multiplier
A3B3 A3B2 A2B3 A3B1 A2B2 A1B3 A3B0A2B1A1B2A1B3 A3B0 A2B0 A1B1 A0B1 A1B0 A0B0

PARTIAL
AND

AND

AND

AND

AND
AND

AND
AND
AND
AND

AND
AND

AND

AND

AND

AND
PRODUCTS

ACCUMULATION FA HA HA HA

z FA FA
FA FA

FA FA HA FA

S7 S6 S5 S4 S3 S2 S1 S0

ITEE, UQ 46
 4x4 Multiplier
Sum in X Cin

Y
AND A3 A2 A1 A0
A B B0
CO CI A3B0 A2B0 A1B0 A0B0
S C S C S C S C
Cout
B1
A3B1 A2B1 A1B1 A0B1
Sum Out C S C S C S C
B2
A3B2 A2B2 A1B2 A0B2
C S C S C S C
B3
A3B3 A2B3 A1B3 A0B3

S S S S S S S
P7 P6 P5 P4 P3 P2 P1 P0

ITEE, UQ 47