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LECTURE 8

Logic Implementation Platforms

ITEE, UQ 1
Logic Implementation Technologies
• Fixed logic ICs – MSI logic chips
• Programmable logic
– SPLDs
– CPLDs
– FPGAs
• Application specific integrated circuits
– Full custom – almost every transistor custom made to for best
performance
• Best performance, smallest area
• Very expensive and time consuming to design
– Standard cell – parametrised modules predesigned and put in the
library
• Good performance-area tradeoff
• Easier to design, cheaper to produce

ITEE, UQ 2
 Logic Implementation

ITEE, UQ 3
 General structure of PAL

Images are taken from the instructor resources of the text-book Digital Fundamentals by Thomas L. Floyd, Published by Pearson Educations Inc. 2015, 11th edition

ITEE, UQ 4
 General structure of PAL
Any Boolean function can be implemented as
x 1 x2 xn sum of products

Input buffers
and
inverters
x 1 x1 x n xn

P1

AND plane Pk
OR plane

f1 fm
ITEE, UQ 5
 Structure of a CPLD
I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block

ITEE, UQ 6
 Structure of a CPLD

ITEE, UQ 7
Images are taken from the instructor resources of the text-book Digital Fundamentals by Thomas L. Floyd, Published by Pearson Educations Inc. 2015, 11th edition
 Field Programmable Gate Array
(FPGA)
• CPLD and PAL structures have performance
and capacity drawbacks due to the
implementation technology
– E.g. number of logic cells that can be
implemented
– Latency of logic function
• FPGA – Static RAM (SRAM) based
– Uses Look Up Table (LUT) rather than PAL for
logic implementation.
ITEE, UQ 8
 FPGAs – Look up table

ITEE, UQ 9
 FPGA Structure

ITEE, UQ 10
Images are taken from the instructor resources of the text-book Digital Fundamentals by Thomas L. Floyd, Published by Pearson Educations Inc. 2015, 11th edition
 Two input Look-Up Table
(LUT)
x1 x1 x2 f1 x1
0 0 1
0/1 0 1 0 1
0/1 1 0 0 0
f 1 1 1 f1
0/1 0
0/1 (b) f 1 = x1x2+ x1x2 1
x2 x2

(a) Circuit for a two-input LUT (c) Storage cell contents

in the LUT

ITEE, UQ 11
 Three-input LUT
x1
x2

0/1
0/1
0/1
0/1
f
0/1
0/1
0/1
0/1
x3

ITEE, UQ 12
Images are taken from the instructor resources of the text-book Digital Fundamentals by Thomas L. Floyd, Published by Pearson Educations Inc. 2015, 11th edition
 Pass-transistor switches in
FPGA

x 0 V
1 0 f1
f
0 1
x
2 1
V
A
1 0 0
SRAM SRAM SRAM

(to other wires)

ITEE, UQ 13
 LUT + flip-flop

Select

Out
Flip-flop
In
1
In LUT D Q
2
In
3
Clock

ITEE, UQ 14
 Section of programmed
FPGA
x3 f

x1
x1 0 x2 0
0 f 1 f
x2 x2 0 1 x3 0 2
1 0

f1 0
1 f
f2 1
1

ITEE, UQ 15
 Typical Design Flow

ITEE, UQ 16
Images are taken from the instructor resources of the text-book Digital Fundamentals by Thomas L. Floyd, Published by Pearson Educations Inc. 2015, 11th edition
 Look at some FPGA data sheets and Xilinx FPGA example

https://www.xilinx.com/products/technology/dsp.html#overview

ITEE, UQ 17