CSSE4010 – Digital System Design

Prac 1 – Introduction to Tools and Structural/Behavioural/Data

Flow Design

Learning Objectives
• Getting started with Xilinx Vivado tools
• Explore and learn basics of Structural, Dataflow and Behavioural design methodologies.
• Learn basics of VHDL design entry.
• Understand the use of functional simulation, synthesis and testbeds.
• Understand the concept of FPGA programming.

Introduction:
This practical introduces you to the Xilinx Vivado development environment for design of digital
circuits. This practical also introduces Structural and Behavioural VHDL design methodology. The
focus of this practical is also on synthesis and simulation of VHDL designs. This practical is a self
paced tutorial to introduce you to the key concepts of developing digital designs with VHDL. Please
refer to additional tutorials posted on Blackboard for more information.

Preparation – Installing Vivado

Xilinx Vivado is available for use in lab computers. For home use, you can download and install Xilinx
Vivado Design Suite – HLx webPACK 2020.2 (Windows or Linux web installer) on your home PC or
laptop computer (Windows 10 is the officially supported platform). You may also be able to do
remote desktop connections to lab computers. Details will be provided on this.

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Procedure
You are to follow all the steps (creating a project, choosing the target device, creating the design,
simulating and synthesising) with a simple design. The emphasis is on understanding simulation and
synthesis.

1. Create a new project

a) Open Vivado (Lab computer: Desktop\Laboratory Software\Vivado2020.2). DO NOT open Vivado

HLS. Click "Create New Project". Create new project in your directory e.g. "prac1" on your local drive
or USB drive. DO NOT CREATE THE FOLDER ON YOUR network H DRIVE or DESKTOP - as this will
slow down Vivado, considerably. Backup your work to your USB drive before you log off. Work
saved on local lab computers will be lost after you log off.

b) Create an RTL Project, as you will be using VHDL source files. DO NOT tick the “Do not specify
sources at this time” option box.

c) Make sure that the "Target" and "Simulator Language" settings are both set to VHDL. Do not add
any existing sources.

d) Do not add any existing IP.

e) Do not add any Constraints.

f) Configure the new project for the FPGA being used. Set the FPGA device to be XC7A100T CSG324-3
FPGA from the Artix-7 family. XC7A100T is the FPGA device and CSG324-3 is the pin package. Select
VHDL as the project type. Leave any other fields as their default values. Click “Next” and then click
“Finish” to create your new project.

g) Create a VHDL source file. Click the "Add Sources" icon (Under Project Manager in the Flow
Navigator) to bring up the dialog to create a new file. Select "Add or create design sources". Create a
VHDL source file named "and2gate".

h) Now define the inputs and outputs to the VHDL module with the dialog box that appears.
Completing this wizard will have the Vivado tool auto-generate the entity component of the VHDL
file. As we are making a 2 input AND gate we will need 2 input signals (name them "in1", "in2")
and one output (named "outAnd"). DO NOT use the names "in", "out", "inout" as they are reserved
VHDL keywords. Do not check the "bus" option, or set the MSB or LSB field for any of the signals.
These are used when creating multi-bit signals (or bus).

i) Complete the wizard. We do not have any existing sources to the project.

j) In the Project Manager Window, you should see the Sources window with the project we just
created. and2gate-behavioural (and2gate.vhdl) is the VHDL module we just created. Double
click it to open the VHDL file for editing.

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2. Create a basic design

The entity component is already complete (this was auto-generated for us by the wizard). The
architecture section of the code defines the behaviour or this particular module, i.e. what it actually
does. Between the begin and end Behavioural lines add this line of code:

outAnd <= in1 and in2;

You have now created a behavioural/dataflow description of an AND gate with two inputs. Save the
file (File >> save all).

3. Create a VHDL test bed for simulation

A VHDL Test Bed is used to test a design by providing simulated inputs (into a VHDL module) and
checking the resulting outputs (from the VHDL module). In this exercise, create a VHDL test bed to
simulate the VHDL module with the Vivado simulator.

a) In the Flow Navigator; go to "Add Sources" and select "Add or Create simulation sources". Specify
the simulation set to be "sim_1". Create a VHDL module and name it "test_and2gate".

b) A test bed has an empty entity and does not have any inputs or outputs.

c) You can now see the new test bed source file in the sources window. Double click to open for
editing. This file is like a 'breadboard' described in VHDL, it connects to the simulator through a
special “Entity” section that MUST not have any inputs or output ports. The simulator will know that
it is a test “Entity”.

The “Architecture” section describes how you test bed operates. Your and2gate is a VHDL
component to be tested. This is done in the COMPONENT statement. An instance of the unit under
test is instantiated with the PORT MAP statement. You must add the COMPONENT and PORT MAP
Statements.

d) Add the component declaration of your VHDL module to the test bed, directly after the
"architecture Behavioural of test_and2gate is" statement.

component and2gate port (in1 : in STD_LOGIC;

in2 : in STD_LOGIC;
outAnd : out STD_LOGIC);
end component;

e) You now need to declare input and output signals to control the inputs and to detect the outputs
of your VHDL module being tested. Input 'wires' have default values '0' in their signal declaration
statements. Add the following signal declarations directly after the component declaration.

signal in1 : STD_LOGIC;

signal in2 : STD_LOGIC;
signal outAnd : STD_LOGIC;

f) Add the port map declaration of your VHDL module to the test bed, directly after the "begin"
statement. Note “and2gate” should correspond to the name of your VHDL module.

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u1 : and2gate port map (

in1 => in1,
in2 => in2,
outAnd => outAnd);

g) The next step is to simulate input signal patterns. Simulation patterns can be created in
PROCESS(es) , which are VHDL constructs allowing complex functionality to be described in a
sequential programming-like style. Wait statement in a process allows you to put timing aspects in
signal generation. You can use a process something like this for generation of one or both signals you
need to test your gate. Add the following VHDL process to your test bed (after your port map
declaration). Once entered, make sure that your test bed has been saved.

NOTE: Comments start with ‘--‘. Be careful when copying and pasting the following code.

tgen1: PROCESS -- tgen1 is a label that can be changed

BEGIN
in1 <= '0'; -- Must start from explicitly set values
FOR I IN 0 TO 5 LOOP -- loop as many times you see fit
in1 <= '1' ;

WAIT FOR 10ps ; -- the process stops for 10ps,

in1 <= '0' ;

WAIT FOR 15ps ; -- '0' is kept on in1w for 15ps

END LOOP ;
WAIT ; -- will wait forever, stops simulation
END PROCESS ;

Another more compact way to generate a pattern is shown below. This is suitable only for simple
pattern generation. Add the lines below after “END PROCESS”.

in2 <= '0', '1' AFTER 20 ps, '0' AFTER 20 ps, '1' AFTER 25 ps, '0' AFTER
32 ps, '1' AFTER 41 ps, '0' AFTER 50 ps ;

h) Save your file. IMPORTANT NOTE: The 'AFTER', ‘WAIT’, ‘FOR’ and ‘LOOP’ keywords can ONLY be
used for testbeds and simulation. DO NOT use 'AFTER', ‘WAIT’, ‘FOR’ and ‘LOOP’ for implementation.

I) You should now notice test_and2gate in bold, under “Simulation Sources/sim_1” in the
Project Manager Window. If this is not the case, re-check your steps. Do not proceed until it does
appear.

4. Simulating designs with the Vivado simulator

Vivado has a simulator that you can use to test your design. You can view the waveforms and
current values of inputs, outputs and any internal signals.

a) In the top menu bar (icons) put 30ps in the run for window. In the Flow Navigator, click "Run
Simulation" and select "Run Behavioural Simulation". You will now be able to observe the
waveforms. Check what occurs at 10ps.

WARNING: if there were errors in your VHDL code, error messages appear in message console.
Check carefully ALL those messages, and correct the VHDL source code if necessary.

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b) Clear the simulation view (Simulation >> Restart). Set the simulation to run for 100ps using the
drop down menus in the simulation toolbar. Run for 100ps (Simulation >> Run).

Examine the waveforms alongside with your VHDL test bed code.

5. Creating a self checking test bed

Change the architecture of your test bed to the following code, below. A testbed of this form can be
used to exhaustively test combinatorial logic. The process will 'walk' the complete truth table for the
AND gate by counting in binary on the inputs (the vector signal 'inputs'). Also add the following
libraries to the beginning of your test bed code:

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Replace architecture of testbed with the following:

ARCHITECTURE behavioral OF test_and2gate IS

COMPONENT and2gate
PORT(
in1 : IN std_logic;
in2 : IN std_logic;
outAnd : OUT std_logic);
END COMPONENT;

signal inputs : std_logic_vector(1 downto 0) := "00";

signal outAnd : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: and2gate PORT MAP (
in1 => inputs(0),
in2 => inputs(1),
outAnd => outAnd);

input_gen : process
begin
inputs <= "00";
--this loop will output the truth table for an AND gate
for I in 1 to 4 loop
wait for 10ps;
inputs <= inputs + '1';
end loop;
wait;
end process;

END;

Rerun the simulation, and check if the results are as you expected. After the wait for 10ps in the
code above add the following:

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if (inputs = "00") then

assert (outAnd = '0') report "bad gate - stuck at 1" severity error;
elsif (inputs = "10") then
assert (outAnd = '0') report "bad gate - stuck at 1 " severity error;
elsif (inputs = "01") then
assert (outAnd = '0') report "bad gate- stuck at 1" severity error;
elsif (inputs = "11") then
assert (outAnd = '1') report "bad gate - stuck at 0" severity error ;
end if;
This code will check to see if your AND gate is behaving properly, that is it ascertains as to whether
the AND gate output matches the inputs using the VHDL assert statement. If your AND gate is
functioning correctly then the assertions will succeed (i.e. the bracketed expression will evaluate to
be true). If the AND gate fails, then the assertion fails and the simulator will display the report
message. The report message is an informative character string, used to highlight error conditions.

Rerun the simulation. Notice that nothing out of the ordinary happens. Now 'break' your AND gate
design, by making it function as an OR gate instead. i.e. in and2gate.vhd, change the line of code to:

outAnd <= in1 or in2 ;

Save the file, and rerun the simulation. Notice that the simulator complains in the console window
that the assertions are failing. Adding assertions to the test bed can lead to much easier testing with
larger designs, as rather than looking through the complete waveforms. For future reference, find
out what levels of severity are allowed (Xilinx references or textbook) and experiment to see how
your simulator acts on those levels.

Fix your AND gate design such that it functions again, properly.

6. Add new modules to your design.

a) Download the or2gate.vhd to your project directory. This VHDL design is the same as the AND
gate created above but instead is AND OR gate rather than AND.

b) Add the file to your project (Flow Navigator, "Add Sources"). Locate the file using the dialog box.

c) A more complex design can be made of available modules in VHDL. Copy the VHDL file
describing and2orgatemixed to your directory (from BB), add to your project as a source. Read
carefully the comments in the file. Open and modify if needed.

This module has three outputs: andorout, andorout_flow, and andorout_beh. The first
is an output of structural description (as it builds ANDOR gate of using the modules defined before -
something very similar to a low-level netlist description). The second output andorout_flow is
from a behavioural description as it describes ANDOR functionality with Boolean expressions. This
description style is called dataflow (in contrast to process description which is called in VHDL
behavioural).

7. Synthesize your design and view Synthesis Schematics

Synthesis is a process in which your VHDL modules are converted into logic modules, which then can
be implemented on an FPGA. Select the and2or in the Program Manager Sources window. Double
click 'Run Synthesize' in the Flow navigator. The synthesis starts. NOTE: this can take a lengthy time
to complete, depending on how big your design is. The synthesis summary will show in the messages
console window and lists consecutive operations of the synthesiser and completes with a summary

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of device utilisation. And errors in your VHDL design will appear in the console windows. Check the
error and warning tabs to identify problems in your designs.

Synthesis Schematic (NOT to be included in report)

The Synthesis schematic shows how design is implemented using elements of the FPGA (i.e. lookup
tables (LUT), IO Buffers, etc). In the Flow Navigator, "Synthesis", expand the "Synthesized Design"
tab. Click on 'schematic' to see a similar schematic that shows how your design is implemented using
FPGA components.

8. Assessment task:
Create a self-checking test bed to exhaustively test the operation of the AND2OR gate design, all
three outputs should be tested. Modify your AND2OR gate design to include some gate propagation
delay (this only affects the functional simulator in Vivado) and provide one functional simulation
case to show the propagation delays you specify.

9. Practical report submission:

Submit a short report (electronically typeset) in pdf format containing the following items pertaining
to the AND2OR gate design above. Screenshots should be included wherever applicable with proper
figure numbers and explanations in the text on what they show.
• Block diagram/gate-level diagram of the design with clearly marked inputs/outputs [1 mark]
• Simulation results showing the correct operation of the design (should cover as many input
combinations as possible) including one simulation scenario showing the gate delays. Also,
show the self-checking nature of the testbed by introducing an error into your design and
showing the testbed output. [4 marks]
• A summary of synthesis reporting the FPGA resource consumption. [1 mark]
There is no oral assessment for prac 1.

Programming the FPGA board (optional task – not assessed)

The purpose of this optional task is to give you hands-on experience with downloading the bit
stream to the FPGA. Here, you create the code for a parity generator for 8 bits and test it with Nexys
4 FPGA board by uploading your HDL design bitstream. In order to complete it, follow the s

I. In the parity.vhd code given, complete the architecture part using a dataflow abstraction
(i.e., using the Boolean expression).
II. You may simulate this design to verify its functionality.
III. You can complete the constraint files parity.xdc by referring to the Nexys 4 board properties
(https://github.com/Digilent/digilent-xdc/blob/master/Nexys-4-Master.xdc). Input 8-bit data
is connected to DIP switches, and dataout needs to be connected to LEDs on the board. The
even-parity out can also be connected to one of the unused LEDs. You may refer to tutorials
posted on Blackboard on “Getting Started” and “Input Output Signals”.
IV. When you click Generate the Bitstream in Vivado, it will automatically synthesize and
implement your design. If there are no errors, the bit stream will be successfully generated.
V. Connect the FPGA board to the PC using the USB JTAG cable. In Vivado, open the Hardware
Manager and select Open Target, Auto Connect from the menu. Vivado displays the board
name if it is properly connected.
VI. Upon clicking on Program device, a window appears with a generated bitstream file. You can
then click on Program.
VII. Check the functionality on FPGA board. (Refer to Blackboard: Learning Resources: Tutorials:
Inputs and outputs signals)

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