Equal Areas PWM: A PWM Method Implementation for 3-

level Voltage Source and Multilevel Inverters

F.Paterakis1,2, D.Nafpaktitis1, G.Koulouras1, M.Darwish2 and G.Hloupis1*
1Technological Educational Institute of Athens, Dept. of Electronic Engineering, Egaleo, 12210, Athens, Greece, *hloupis@teiath.gr
2Brunel University, School of Engineering & Design, Uxbribge, UB88PH, UK

Basic Theory: The basic idea behind the Equal Areas PWM strategy is to create a switching scheme so that the integrated area of
the target reference waveform over the carrier interval is the same as the integrated area of the converter switched output (Fig.1).
The accurate production of the PWM pulse train is obtained by using the integrated areas of the corresponding interval (Fig.2). The
modulation ratio in this method is given as: Umax / Up,max. The decrease of Up,max value or the increase of Umax, implies a corresponding
increase at the duration of the pulse. The limit of this method comes when you decrease the Up,max in such a level where the
corresponding duration of the pulse tp, will be less or equal to space d. To avoid overlaps, the Up,max will exist between Umax and 𝐹𝐸.
The minimum-marginal Up,max can be calculated using the equality that, the area ΑΒCD must be equal with the hatched area ΑΒΕGF
(Fig.3).

Figure 1 Approximation of sinusoidal voltage signal. Figure 2 Generation of an accurate EAPWM pulse. Figure 3 Calculation of optimum Upmax .

Investigation of the Over-Modulation region: The implementation in calculations of the minimum Up,max creates a marginal
modulation ratio at any given switching frequency which is always tending to 1 in order the voltage output to meet the wanted target
reference. The basic method, by default cannot enter the overmodulation region, because of pulse overlaps. The basic theory of
Equal Areas has been investigated for optimization, utilizing the necessity of the minimum Up,max in each interval individually. A new
algorithm has been developed giving the possibility of setting a modulation ratio higher than one without any overlaps. The
algorithm examines the limitations of overlapping in each interval and if the corresponding pulse gets out of the interval it applies
the marginal value of the modulation ratio and continues to investigate the next pulse interval repeating the procedure. That means
that the method can be extend to modulation ratios higher than 1 penetrating in the overmodulation region in a liner way.

Implementation on Multilevel Inverters: The EAPWM method is applied in each level of the MI. Fig.4 shows a half sine wave of
a 9-level inverter with E=4 equal DC sources (Vdc). The sinusoidal voltage in Fig.4 can be expressed as: 𝑣 = 𝑉max ⋅ sin𝜔𝑡 and
𝑉max
𝑉𝑑𝑐 = . Time intervals D1, D2, D3…DE show the duration of each level and can be calculated by equation:𝐷𝑒 = 𝑡 ′ 𝑒 − 𝑡 ′ 𝐸−1 where
𝐸
𝑒
arcsin(𝐸 𝑇
𝑡𝑒′ = and 𝑡′ 𝐸 = − 𝑡 ′ 𝐸−1 . The distribution of pulses in each interval De depends on the number of pulses Ap1 set for the
𝜔 2
𝐷𝑒
first interval. The distribution will be analogue and is given as: Ape = Ap1 ⋅ . Each interval De is then divided by the number of
𝐷1
𝐷𝑒
pulses Ape that are calculated for the corresponding interval De to create equal smaller intervals 𝑑𝑒 where 𝑑𝑒 = (Fig.5, Fig.6).
𝐴𝑝𝑒

Figure 4.Nine-level segregation of output sinusoidal voltage (v). Figure 5.Calculation of active and firing time in a De interval. Figure 6.PWM pulses between random levels “e” and “e-1”.

Simulation and experimental results for a single-phase VSI (left) and a 7-level Inverter (right).
Table 1: Analytical simulation results for the
implementation of EAPWM in Multilevel
Inverters.
Levels-m Num. of Ap1 fp (KHz) THD (%) V1,rms (Volts)
1 0,5 35,57 214,4
5 3 1,7 26,24 219.15
5 3 24,3 219,8
1 0,8 23,2 217,6
7 3 2,6 17,03 219,74
5 4,4 15,6 219,9
1 1,1 17,35 218,6
9 3 3,5 12,04 219,8
5 6 10,06 219,9
1 1,4 13,86 219,08
11 3 4,5 9,47 219,9
5 7,5 8,55 219,96

For the experimental results of the Multilevel inverter

the technical characteristics are:
Load: resistive load (100 ohm, to limit the current to 3A)
Topology: cascaded H-bridge with 100V dc source for
each bridge
Microprocessor: PIC 16F877A
Switches: MOSFETS STP7NK80Z

International Conference ‘Science in Technology’ SCinTE, 5-7 November 2015, Athens, Greece
ID CODE goes here

SCinTE-222-A02/141