Chapter 6 Logic

Chapter 6: Combinational Logic using MSI &LSI
Comparators
Objective
Design a combination logic circuit that compares two
binary numbers and determine the relationship of them.
6.1 Theory
A comparator is a combinational circuit that
compares the magnitude of two binary numbers, A and
B, and generates outputs to indicate whether the two
numbers are equal or which input is greater than the
other. Therefore, the circuit has three outputs to
indicate whether (A=B), (A>B) or (A<B). At any given
input quantities, only one output should be equal to
logic 1. Fig (6-1) illustrates the block diagram of the
comparator.
Fig (6-1): Comparator block diagram
Ass. Prof Dr. Qasim Mohammed Hussein Page 177

To find the equality relationship of two numbers, the

AND gate and XNOR gates can be used as a basic
comparator. The output of each XOR is applied to the
AND gate input. When the two bits for each XOR gate
are equal, the output of XOR is 1. If the two input bits
are not equal the output of XOR is 0. When the two
numbers are not equal, at least one of XNOR output is
0. Thus, the output of AND gate produces 0. The
number of XNOR that are used in design the
comparator equal to the highest digit number. For
example, if A=1011 and B=110, the circuit requires
four XNOR gates.
To compare for the inequality, greater than or less
than, relationships between two numbers A and B, we
start the comparison from the most significant digits
(MSD) of the two numbers, highest order, by doing the
following steps:
1. If the MSD of A=1 and the MSD of B=0 the result
is A>B.
2. If the MSD of A=0 and the MSD of B=1 the result is
A< B.

3. If the MSD of A = MSD of B. We compare the next

lower significant pair digits, and continue until they
are unequal.
Also we can construct a truth table and build the
circuit from it using the regular method. For example,
the truth table of 2-bit comparator is:
A B (A=B) (A<B) (A>B)

0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0
The Boolean functions of the output variables are:

(A=B) = AB AB
(A<B) = AB
(A>B) = AB
The logic diagram of 2-bit comparator is shown in fig
(6-2).
Many IC comparators provide output that indicates
which of the two binary numbers being compared is
larger such as 74LS85 that compare 8-bit numbers.

A0
A1
A>B
A=B
B0
A<B
B1
Fig (6-2 ): 2-bit comparator
Example 6.2: Design a 3-bit comparator?

Solution
Since 3-bit, each number has three digits. Let
A=A2A1A0 and B=B2B1B0.
The numbers A and B are equal if A2=B2, A1=B1,
A0=B0. The function is
(A=B) = (A2 B2)(A1 B1)(A0 B0)
= X2X1X0 Where Xi=Ai Bi
(A>B)=A2B2 + X2A1B1+X2X1A0B0

(A<B)= A2B2 + X2A1B1+X2X1A0B0
Example 6.3: Design a comparator that checks whether

a 4-bit binary number value is less than 5?
Solution
First, we construct the truth table, and find the function
as follow.
A1 A2 A3 A4 (X<5)
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 x x x 0
The Boolean function that satisfies (X<5) is

(X<5) =A3A2 + A3A2A1A0
The circuit will be as fig (6-3).

Fig (6-3): Comparator of less 5
Experiment NO. (11)

Procedure
1. Implement the circuit of the comparator in fig (6-2).
2. Implement the comparator that satisfy the relation
between two numbers, A and B, each with 4 bits,
where A=A3A2A1A0, B=B3B2B1B0, which are shown
in the fig (6-4)?
3. Find the outputs of the comparator in previous step
where: A=1011 and B=11001, A=1001 and
B=1010.
4. Implement a 2-bit comparator using NAND gates
only?

Fig (6-4): 4-bit comparator

Discussion
1. Design a logic circuit that check a 4-bit number and
has 3 output light (red, green, and yellow). The red
light is ON whenever the inputs number is prime
and less than 10. The green light is ON whenever
the inputs number is prime and greater than 10. The
yellow light is ON if the inputs number is equal to
10. Use MSI circuit for the magnitude comparator?
Decoders
Object:
To examine the decoders operation and the concept of
code conversion will be explained.
6.2 Decoder
A decoder is a combinational circuit that converts
binary information from n input lines to exactly one
output of a maximum of 2n output lines. If n=3 the
output = 23 = 8. The output line whose value is equal
to 1 represents the binary number of presently
available in the input lines. An example is a BCD
(binary coded decimal) to decimal decoder.
Example 6.4:
Design 3-to-8 line decoder circuit?
Solution
This decoder has three inputs and eight outputs, each
of the output representing one of the minterms of the
3-input variables. The truth table of 3-8 decoder is
shown in table (6-1). The outputs of 3-to-8 decoder
are:

D0 = XYZ D1 = XYZ D2= XYZ

D3 = XYZ D4 = XYZ D5 = X YZ
D6 = XY Z D7 = XYZ
The circuit of this decoder is shown in fig (6-5).
A 3-to-8 line decoder can be used for decoding the
binary code number to octal number. The output line
whose value is equal to 1 represents the minterm (or
octal number) equivalent of the binary number
presently available in the input lines.
Table (6- 1): Truth table of 3-to-8 decoder
Input Output
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Fig (6-5): 3-to-8 decoder circuit
6.3 Implementation the Boolean Function Using

Decoder
A combinational circuit with n inputs and m outputs
can be implemented with an n-to-2n line decoder and
employing an external OR gates. The companies have

produced chips that perform common or most

frequently used circuit functions. For example, the
circuit in fig. (4-1) is shown in the chip of fig (4-2).
Fig (4-2): 3-t0-8 decoder chip

The procedure for implementing a combinational
circuit requires that the Boolean function for the circuit
be expressed in sum of minterm canonical form. The
inputs of each OR gate are selected from the decoder
outputs according to the minterms list in each function,
.
Example 6.5: Implement the following function using

a decoder?
F(X, Y, Z ) = (X  Y).Z + XYZ

Solution
At the first step, the function expresses in sum of
minterm form. So,
F(X,Y,Z) = (X  Y).Z + XYZ
F(X,Y,Z) = (XY + XY )Z = XYZ + XYZ + XYZ
F(X,Y,Z) = m3 + m5 + m2
F(X,Y,Z) = (2, 3, 5).
Since there are three input variables, 3-to-8 decoder
will be used to implement this circuit. The
implementation is shown in fig (6-6).
Fig (6-6): Implementation of Fusing a decoder

Example 6.6: Implement the following functions
using a decoder?
3,6,7)

Solution
At first step, the functions express in a sum of minterm
form.
3,6,7)
=∑(6,7)
Since there are three inputs, 3-to-8 decoder and three
OR gates will used, as showing in the following figure.
Example 6.7: Design excess-3 to seven-segment code

converter using a decoder?
Solution
A decoder can be used as a code converter by
designing a circuit to convert from excess-3 code to
seven-segment code.

Assume that there is a 4-to-16-line decoder. Since there

are only 10 valid excess-3 codes, so only 10 outputs
from a 4-to-16-line decoder will be used.
Table (6-2) illustrate the truth table for each of seven
output functions (the Si) in terms of the four input
variables. The circuit external to the decoder will
consist of seven OR gates, one for each segment. Each
segment is represented by listing the minterm numbers
corresponding to each code for which that segment
output has the value 1.
Table (6-2): Truth table of excess-3 to seven segment
converter
Decimal Input Output
digit Excess 3 Seven-Segment
W X Y Z S1 S2 S3 S4 S5 S6 S7
0 0 0 1 1 1 1 1 1 1 1 0
1 0 1 0 0 0 0 0 1 1 0 0
2 0 1 0 1 1 0 1 1 0 1 1
3 0 1 1 0 0 0 1 1 1 1 1
4 0 1 1 1 0 1 0 1 1 0 1
5 1 0 0 0 0 1 1 0 1 1 1
6 1 0 0 1 1 1 0 0 1 1 1
7 1 0 1 0 0 0 1 1 1 0 0
8 1 0 1 1 1 1 1 1 1 1 1
9 1 1 0 0 0 1 1 1 1 0 1

The minterm lists for the outputs corresponding to the

segments are as follows:
S1 = Σ(3, 5, 6, 11)
S2 = Σ(3, 7, 8, 9, 11, 12)
S3 = Σ(3, 5, 6, 8, 10, 11, 12)
S4 = Σ(3, 4, 5, 6, 7, 10, 11, 12) (8)
S5 = Σ(3, 4, 6, 7, 8, 9, 10, 11, 12)
S6 = Σ(3, 5, 6, 8, 9, 11)
S7 = Σ(5, 6, 7, 8, 9, 11, 12)
Only one of the OR gates (the one for S6) is shown in
Fig (6-7); there should be six others. The excess-3 code
corresponding to a decimal digit appears at the input
displays the digit.

Fig (6-7): Excess-3 to seven-segment code converter

6.4 Encoder
An encoder performs a function that is the opposite of
decoding. The encoder circuit has 2n (or less) input
lines and n output lines. The output lines generate the
binary code for the 2n input variables. An example of
encoder is an octal to binary encoder (8 to 3 encoder).
The truth table and the logic circuit of 8-to-3 encoder
are shown in table (6-3) and fig (6-8), respectively
Table (6-3): 8-to-3 encoder

Input Output
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Fig (6-8): 8-to-3 encoder circuit

6.5 Priority Encoder
The priority encoder establishes an input priority to
ensure that only the highest-priority input line is
encoded. For example, if both D1, D3, and d6 are 1
simultaneously, the output will be 110 because D6 has
higher priority over D1 and D3.An example of a priority
encoder is illustrated in the following example.
Example 6.7: Design 4-to-2 priority encoder?

Solution: At start, we construct the truth table of 4-to-2

priority encoder.
Table (6-4): Truth table of 4-to-2 priority encoder
Input Output
X Y Z W E0 E1
0 0 0 0 x x
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 1
1 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1

Fig (6-9): Outputs simplification

Using Karnaugh map, the output simplifications are
E1= X + YW
E0= X + Y
The logic diagram of priority encoder is shown in fig
(6-10)
Experiment No. (12)

Procedure:
1. Connect the circuit shown in Fig (6-5) and write its
truth table?
2. Connect the circuit shown in Fig (6-8) and write its
truth table?

3. Construct the (7442) BCD to decimal decoder as

shown in Fig (6-12) and write its truth table?
4. Connect the circuit as shown in Fig (6-11) and write
its truth table?
5. Implement the circuit that implement 4-to-2 priority
encoder and find the truth table, Fig (6-13)?
Discussion:
1. Construct a binary to BCD code converter? Write the
truth table of step 1?
2. Design a full adder using a decoder with two or
gates?
3. Implement the following function using a decoder
with three OR gates?
F1(A,B) = X+Y
F2(A,B) =  (0,2)
F3(A,B) = Π (0,1)
4. Design 3-to-2 priority encoder?

Fig (6-10)
Fig (6-11)

Fig (6-12): BCD code to decimal
Fig (6-13)

Multiplexer
Object:
To examine the multiplexer and the demultiplexer and
to explain the concept of the parity generator / checker.
6.6 Theory:
The Multiplexing means transmitting a large numbers
of information over a small number of channels or
lines. A digital multiplexer (MUX) is a combinational
circuit that selects one line of binary information from
many input lines and directs it to a single output line.
The selection of a particular input line is controlled by
a set of selection, control, lines. A MUX with n
selection lines can selected from a maximum of 2n
input lines, as shown in fig (6-14).
Standard MSI package are available as a MUX.
Fig (6-14): A (8X1) multiplexer

A multiplexer is also called a data selector, since it

selects one of many inputs and steers the binary
information to the output line.
The logic gates use to construct the MUX by
connecting them together. Fig (6-15) shows the logic
diagram for 2-input MUX. It uses two inverters ,
four 3-input AND gates ( ), and one 4-output OR
gates ( ). The output of all AND gates except one of
them are 0.
Fig (6-15): 4 x 1 MUX

6.6 Implementation Boolean Function Using

MUX
A MUX can be used to implement of Boolean
function.
The procedure for implementing a function of n
variables with a MUX is as follow:
1. At the first, the function must be represented in
sum of minterms form.
2. If a Boolean function has n variables, we take (n-
1) variables as selection lines of MUX. The
remaining single variable of the function is used
for the input of MUX. The number of input lines
of the MUX is equal to 2number of select lines.
3. Make the truth table of the n variables, , number
each row from 0 to n-1, and the output equal to 0
whenever the value of input variable is
complement, otherwise the out is 1.
4. Draw a table with two rows, each row contain
number of columns equal to number of
multiplexer input lines. The first row list all those
minterm where function out equal 0 (the input

variable is complement) and the second row all

the minterms with the input variable
uncomplemented.
5. Circle all the minterm numbers of the function
in the table and inspect each column separately.
a) If the two minterms in a column are not
circled, apply 0 to the corresponding
multiplexer input.
b) If the two minterms in a column are circled,
apply 1 to the corresponding multiplexer
input.
c) If the bottom minterm is circled and the top
is not circled, apply the input variable to
the corresponding multiplexer input.
d) If the top minterm is circled and the bottom
is not circled, apply the complement of
input variable to the corresponding
multiplexer input.
6. Draw the circuit.

Example 6.8: Implement the function

F(A,B,C,D)=(0,4,6,8,10,11,15) using multiplexer?
Solution
To implement the function F using a multiplexer,
we use the above steps. Since the function has four
variables, we select three of them as a selection
lines. So, the number of input lines is 23=8. While
there is one as a select line.
Suppose that A, B, D are chosen to apply to the
selection lines whereas the C is input variable.
Making the following table:
The multiplexer circuit connection that performs F

is shown in fig (6-16) that illustated that the inputs
are labeled by C , C, 0, and 1, while the selected
lines are lebeled by A, B, and D, where D is the
LSB. The input line I0 is connected to the
complement of C.

Fig (6-16): Multiplexer connection

If we apply B, C and D to the selection lines
whereas the A is input variable. Making the
following table:
The logic diagram is shown in fig (6-17).

Fig (6-17)
6.7 Demultiplexer
A demultiplexer (DEMUX) is a combinational circuit
that selects binary information from one of many input
lines and transmits this information on one of 2 n
possible output lines. The selection of a specific output
line is controlled by the bit values of n selection lines
at any given time. The decoder with enable (E) input,
fig (6-18-a), can function as a demultiplexer. If the E
line is taken as a data input line and the input lines of

decoder are taken as the selection lines in

demultiplexer, fig (6-18-b).
(a) Decoder with enable line (b) Demultiplexer

Fig (6-18)
Decoder/demultiplexer circuits can be connected

together to form a large decoder circuit. Figure (6-19)
shows two 2x4 decoders with enable inputs connected to
form a 3x8 decoder.
Table (6-5) : Demultiplexer truth table

Fig (6-15 ):A demultiplexer circuit
Fig (6-19): a 3 x8 decoder constructed with 2x4

decoder
Experiment No. (13)

Procedure:
1. Connect the circuit in fig (6-15)? Find the results
for all possible of selection inputs?
2. Construct a (4 to 1) MUX using A as input to
give the output of
F(A,B,C) = (m0, m3, m5, m6)?
3. Write the truth table of the circuit?
4. Design (2 x 4) decoder with one enables line that
function as a demultiplexer?
Discussion:
1. Design a full subtractor using MUX?
2. Write its truth table?
3. Implement a 4x16 decoder using four 2X4
decoders?
4. Implement 4 x 16 decoder using 3 x 8 decoders?

Read Only Memory (ROM)
Objective
 Understand the structure and size of the ROM.
 Implement Boolean functions using ROM’s
6.8 Theory
Memories are used for storing binary data. This stored
data can be interpreted as being the implementation of
a combinational circuit. A combinational circuit
expressed as a Boolean function in canonical form that
is implemented in the memory by storing data bits in
appropriate memory locations. Any types of memory
such as ROM (read-only memory), RAM (random
access memory), PROM (programmable ROM),
EPROM (erasable PROM), EEPROM (electrically
erasable PROM), and so on, can be used to implement
combinational circuits.
A block diagram of a ROM is shown in fig (6-20). It
consists of n input lines and m output lines.

Fig (6-20): ROM block diagram

Each bit combination of the input variables is called an
address. Each bit combination that comes out of the
output lines is called a word. The number of bits per
word equal to the number of output lines m. An address
is a binary number that denotes one of the minterms of
n variables. For n input variables, there is 2n addresses.
For each address input, there is a unique selected word.
For example, a 32 x 8 ROM consist of 32 words of 8
bits, each has 5 input lines. The number of addresses is
32, in the range 0 to 31 (00000 to 11111). The ROM is
sometimes specifying by the total number of bits that it
contains, which is 2n x m.
The internal construction of ROM consists of two
parts:
1. An n × 2n decoder.

2. A 2n × m array of switching devices that form

interconnections between the 2n lines from the
decoder and the m output lines
The 2n output lines from the decoder are called the
word lines. The array of OR gates equal to the outputs
within a single IC package. This is shown in the Fig (6-
21).
Fig (6-21): Construction of 32x4 ROM

To simplify the representation of the internal
construction of ROM circuit diagram, we use a new
logical symbol for AND and OR gate with multiple
inputs. Instead of having multiple input lines drawn to
the gate, the input lines are replaced with just one line
going to the gate. The multiple input lines are drawn

perpendicular to this one line. To actually connect an

input line to the gate, an explicit connection point (•)
must be drawn at where the two lines cross. For
example, in Fig (6-22) the AND gate has only two
inputs, whereas the OR gate has three inputs.
AND gate OR gate

Fig (6-22): Array logic symbol
6.9 Implementation the Boolean function using a

ROM
At first, the Boolean function must be expressed in sum

of minterm before implementing it using a ROM. Each
ROM output represents the sum of minterm of function
with n input variables by breaking the links of those
minterms not included in the function. The size of
number of input
decoder is (number of input variable x 2
variable
) . The number of outputs equals to the number of

functions. For n inputs and m outputs combinational

circuit, we need a 2n x m ROM.
Example 6.9: Implement the following functions using
a ROM?
F1(A,B) = ∑ (1, 2, 3)
F2(A,B) = AB + AB
Solution:
Since the inputs of two functions are two, the size of
decoder is 2x4. The ROM that implements the
combinational circuit has two inputs variables and two
outputs variables, so its size is 4 x 2. The truth tables is
Inputs Outputs
A1 A0 F1 F0
0 0 0 1
0 1 1 0
1 0 1 1
1 1 1 0
At first, we express the functions in sum of minterm, so

F2(A,B) equals to ∑(0,2). And then we determine the
links that must be broken and which should be left in

place. For F1, the minterm that specify the output 0 will
broken, while the minterm 1 and 3 if F2 will broken.
The implementation is shown in fig (6-23).
Fig (6-23): The ROM implementation
Example 6.10: Implement the following two Boolean

functions using the 16 × 4 ROM circuit?
F1(A3, A2, A1,A0) = ∑ (3, 6, 7, 8, 10, 14)
F2 (A3, A2, A1,A0) = A3A2A1A0 + A3A2
Solution
The functions must be expressed in sum of minterm.
Therefore the function F2 form changes to sum of
minterm.
F2 (A3, A2, A1,A0) = A3A2A1A0 + A3A2A1A0 +
A3A2A1A0 + A3A2A1A0 + A3A2A1A0
F2(F2 (A3, A2, A1,A0) =∑(0,4,5,6,7)

The implementation is shown in the fig (6-24).
Fig (6-24)
Example 6.11: We have a circuit accepts a 3 bit

number and generates an output binary number equal to
the square of the input number. Design this
combinational logic circuit using a ROM.

Solution
At the first, we derive the truth table for this circuit. It
has 3 inputs and 6 outputs.
Input Output
A2 A1 A0 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 1
1 0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1
From truth table, we see B1=0 and B0 =A0. Therefore,

we need only 4 outputs with the ROM. The ROM size
is 8x4, eight words of four bits. The block diagram that
implements the circuit is shown in fig (6-25).

Fig (6-25)

Programmable Logic Array (PLA)

Objective
 Understand the structure of PLA.
 Implement Boolean functions using PLA.
6.10 Theory
Using ROM to implement a combinational circuit is
very wasteful because usually many locations in the
ROM are not used, don’t care condition. Each storage
location in a ROM represents a minterm. In practice,
only a small number of these minterms are the 1-
minterms for the function being implemented. So, the
ROM implementing the function is usually quite
empty
PLA is similar to a ROM. It is a kind of programmable

logic device used to implement combinational logic
circuits that have large number of inputs and outputs.
It is designed to reduce this waste by not having all the
minterms built in ROM, but rather allowing the user to
specify only the minterms needed.

The PLA has a set of programmable AND gate planes

(instead of using a decoder), which link to a set of
programmable OR gate planes, which can then be
conditionally complemented to produce an output.
This layout allows for a large number of logic
functions to be synthesized in the sum of products (and
sometimes product of sums) canonical forms
according to the PLA program table. Fig (6-26) shows
the PLA block diagram, where n is the number of
inputs, k product term , and m sum terms.
Fig (6-26): PLA block diagram
6.11 Implementation Boolean function using

PLA
The procedure of implementation uses the following
steps:
1. Prepare the truth table.

2. Write the Boolean expression in SOP (sum of

products) form.
3. Obtain the minimum SOP form to reduce the
number of product terms to a minimum.
4. Decide the input connection of the AND matrix for
generating the required product term.
5. Then decide the input connections of OR matrix to
generate the sum terms.
6. Decide the connections of function, either through
NOT gate or not, depend on the case of function.
7. Program the PLA.
Example 6.1: Implement the following functions in

PLA?
F1 = ∑ (0,1,4,5,7)
F2 = BC + AB
Solution
The circuit has three inputs (A, B and C) and two
outputs (F1 and F2). So, the truth table of this circuit is
as following:

A B C F1 F2
0 0 0 1 1
0 0 1 1 1
0 1 0 0 0
 F1(A,B,C)=∑(0,1,4,5,7)
0 1 1 0 0
1 0 0 1 1 F2(A,B,C)=∑(0,1,4)
1 0 1 1 0
1 1 0 0 0
1 1 1 1 0
Simplify F1 and F2 and find their complements using

Karnaugh map and taking the case with lowest terms.
Then we construct PLA program table to specify the

links in the circuit
Product Inputs Outputs
term A B C F1 F2
B - 0 - 1 -
AC 1 - 1 1 1
B - 1 - - 1
T C

The block diagram of PLA circuit is
The program table contains three columns: product

term, inputs and outputs. Product term column
contains a list of product terms.
Inputs column determine the path between inputs and
AND gates. For each product term, the inputs are
marked with 1, 0, or – (dash). If the variable in the
term in normal form, the corresponding input variable
is marked with 1, such as the variable A in product
term AC. If it appears in complement form, it marks
with 0, like the variable B in product term B. If the
variable is absent in the product term, it mark with a
dash, like the variable A in product term (B . A), dash
specifies no connection.

Outputs column specifies the path from AND gates to

OR gates. The output variable marks with 1 for the
product term that appears in the function. The 1 means
there is a path from corresponding AND to the output
OR gate. There is no connection across the NOT gate
in result of F1 since we take the normal function of it.
While there is a connection across the result of F2
since we take the complement of F2.
Example 6.2: Implement the Boolean functions that is
defined by the following truth table using PLA?
Solution:
From truth table, the circuit has three inputs, three product
terms and two outputs
First, F1 and F2 are simplified using karnaugh map

F1=AB' +AC F2= AC + BC

Then the PLA table is constructed to specify the links
The PLA circuit diagram is

Chapter 6 Logic

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Chapter 6 Logic

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Chapter 6: Combinational Logic using MSI &LSI

Fig (6-1): Comparator block diagram

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To find the equality relationship of two numbers, the

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3. If the MSD of A = MSD of B. We compare the next

A B (A=B) (A<B) (A>B)

The Boolean functions of the output variables are:

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Fig (6-2 ): 2-bit comparator

Example 6.2: Design a 3-bit comparator?

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(A<B)= A2B2 + X2A1B1+X2X1A0B0

Example 6.3: Design a comparator that checks whether

The Boolean function that satisfies (X<5) is

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Fig (6-3): Comparator of less 5

Experiment NO. (11)

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Fig (6-4): 4-bit comparator

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D0 = XYZ D1 = XYZ D2= XYZ

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Fig (6-5): 3-to-8 decoder circuit

6.3 Implementation the Boolean Function Using

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produced chips that perform common or most

Fig (4-2): 3-t0-8 decoder chip

Example 6.5: Implement the following function using

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Fig (6-6): Implementation of Fusing a decoder

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Example 6.7: Design excess-3 to seven-segment code

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Assume that there is a 4-to-16-line decoder. Since there

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The minterm lists for the outputs corresponding to the

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Fig (6-7): Excess-3 to seven-segment code converter

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Table (6-3): 8-to-3 encoder

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Fig (6-8): 8-to-3 encoder circuit

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Solution: At start, we construct the truth table of 4-to-2

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Fig (6-9): Outputs simplification

Experiment No. (12)

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3. Construct the (7442) BCD to decimal decoder as

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Fig (6-12): BCD code to decimal

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Fig (6-14): A (8X1) multiplexer

A multiplexer is also called a data selector, since it

Fig (6-15): 4 x 1 MUX

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6.6 Implementation Boolean Function Using

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variable is complement) and the second row all

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Example 6.8: Implement the function