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 Journal of Physics D: Applied Physics

J. Phys. D: Appl. Phys. 52 (2019) 444005 (8pp) https://doi.org/10.1088/1361-6463/ab3716

Compact modelling and SPICE simulation

for three-dimensional, inkjet-printed organic
transistors, inverters and ring oscillators
Sungyeop Jung1,2 , Jimin Kwon1,2 , Shizuo Tokito3, Gilles Horowitz4 ,
Yvan Bonnassieux4 and Sungjune Jung1,2
1
Future IT Innovation Laboratory, Pohang University of Science and Technology (POSTECH),
77 Cheongam-Ro, Pohang, 37673, Republic of Korea
2
Department of Creative IT Engineering, Pohang University of Science and Technology (POSTECH),
77 Cheongam-Ro, Pohang, 37673, Republic of Korea
3
Research Center for Organic Electronics (ROEL), Yamagata University, 4-3-16 Jonan, Yonezawa,
992-8510, Japan
4
Laboratoire de Physique des Interfaces et des Couches Minces (LPICM), Unité Mixte de Recherche
(UMR) 7647, Centre National de la Recherche Scientifique (CNRS), École Polytechnique,
91128 Palaiseau, France

E-mail: sungyeop.jung@postech.ac.kr and sjjung@postech.ac.kr

Received 31 May 2019, revised 23 July 2019

Accepted for publication 30 July 2019
Published 20 August 2019

Abstract
We report an in-depth study of three-dimensional (3D) inkjet-printed flexible organic field-
effect transistors (FETs) and integrated circuits (ICs), and demonstrate the necessity, the
feasibility and the key aspects of modelling-driven design and analysis. In particular, we
performed compact modelling of the flexible printed organic FETs to determine transistor
parameters from measured electrical characteristics, and to optimize the design of transistors
for a balanced inverter. We also conducted a SPICE simulation of both static and dynamic
behaviours of flexible printed organic complementary inverters and ring oscillators. This
study revealed design rules to guide fabrication of the 3D structure of the inverter. The
study also showed that the parasitic capacitances are dominant factors that determine the
transient behaviour of the ring oscillator. Our work provides insights that can guide further
improvement of flexible printed organic FETs and ICs towards the realisation of increasingly
complex organic ICs and unconventional electronic applications.

Keywords: flexible electronics, printed electronics, compact modelling, SPICE simulation,

inkjet printing, organic integrated circuit, organic transistor

(Some figures may appear in colour only in the online journal)

1. Introduction Various passive and active electronic devices have fabricated

Organic electronic devices and circuits are a key enabling
technology for unconventional electronic applications such
as wearable computers [1], artificial skin [2], and artificial
afferent nerves [3]. Inkjet printing (IJP) is a digital, noncontact
and versatile technique that can print a wide range of materials
at low temperatures, so this method is particularly suitable for
fabrication of flexible electronics on flexible substrates [4, 5].
using IJP, including resistors [6], inductors and capacitors
[7, 8], diodes [9], transistors and circuits [10–13]. We recently
demonstrated a three-dimensional (3D) integrated circuit
(IC) based on a 3D complementary organic field-effect tran-
sistor (FET) with high transistor density, 100% yield, uniform
operation, and long-term stability [14]. Nonetheless, model-
ling-driven design and analysis of organic FETs and ICs is
lacking, so industrial commercialization has been IJP has

1361-6463/19/444005+8$33.00 1 © 2019 IOP Publishing Ltd Printed in the UK

J. Phys. D: Appl. Phys. 52 (2019) 444005
Figure 1. Flexible printed organic FET and IC development process in cluding device modelling and circuit simulation as well as design,
fabrication, and analysis and evaluation.
been hindered, despite its potential to facilitate realisation of
diverse and complex circuit applications.
Models of organic transistors have been developed and
improved [15–19], and some have been included in open-
source [17, 18] or licensed [19] circuit simulators. The
validity and universality of state-of-the-art models are contin-
uously tested, but mostly on organic FETs and ICs that have
been deposited using evaporation [17–19]; reports on flexible
inkjet-printed organic FETs and ICs are rare [20].
In this paper, we examine the feasibility of using mod-
elling-driven design and analysis to guide development
of flexible printed organic FETs and ICs. We will consider
both direct-current (DC) and alternating-current (AC) modes
to gain insights to achieve further improvement of flexible
printed organic devices and circuits.
2. Modelling-driven design, fabrication and analysis
for flexible and printed organic electronics
2.1. Organic FET and IC development
The process (figure 1) of developing flexible printed organic
FETs and ICs requires four steps: modelling, design (sche-
matic and layout), fabrication by inkjet printing, then analysis
and evaluation.
2.1.1. Device modelling and SPICE simulation. Modelling
provides rules to guide design of devices and circuits, and
provides a theoretical tool to extract parameters for use in
analysis and evaluation. Optimization of devices and circuits
is generally unattainable, so the approach to the optimum
may require iteration of the development process. For this
approach, modelling is an essential step.
The modelling step includes device modelling and circuit
simulation. Device modelling includes the formulation of a
mathematical equation (i.e. a compact model) that describes
2
S Jung et al
the device behaviour [21]. Circuit simulation consists of pre-
dicting circuit behaviour by using a circuit simulator called
simulation program with integrated circuit emphasis (SPICE).
The compact models developed by device modeling are
implemented in the simulator and its constituent devices are
represented by device parameters. For the results of SPICE
simulation to be useful for circuit designers, the compact
model must be accurate, simple and rigorous.
SmartSPICE (Silvaco, Inc) is a high-quality, commercial-
grade, general-purpose circuit-simulation program for non-
linear DC, nonlinear transient, and linear AC analysis [22].
SmartSPICE includes reliable models for semiconductor
devices such as diodes, metal-oxide-semiconductor field-
effect transistors (MOSFETs), metal–semiconductor field-
effect transistors (MESFETs), and thin-film transistors (TFT).
2.1.2. Consideration for flexible printed organic FETs and
ICs. For the development of flexible printed organic FETs
and ICs, the modelling step requires particular attention
because organic FETs and ICs exhibit unconventional bahav-
iours that have not been seen in silicon FETs and ICs [23].
Such behaviours include gate-voltage dependent field-effect
mobility µFET [24] and contact resistance RC [25] that give
rise to non-linear transfer characteristics. In addition, flexible
printed organic FETs have distinctive contact structures, i.e.
staggered and coplanar [26] or single-gate and dual-gate [27],
and structural dimension, i.e. technique-specific printing reso-
lution of 1 µm to 200 µm [28].
The universal organic thin-film transistor (UOTFT) model
is a dedicated compact TFT model for organic TFTs [19,
22]. It provides a smooth interpolation of the drain current
between linear and saturation operation regions that encom-
pass the channel-length-modulation effect and a unified
expression for a gate-induced charge in the channel; this
expression is valid for all operation regimes. In addition, the
UOTFT model includes a power-law representation of µFET
J. Phys. D: Appl. Phys. 52 (2019) 444005
Figure 2. (a) Circuit diagram and (b) device structure of a 3D
integrated flexible and printed organic complementary inverter
composed of a p -type organic field-effect transistor (PFET)
fabricated on top of an n-type organic field-effect transistor
(NFET). Parylene diX-SR is used as the basement, gate dielectric
and passivation layers. Ag is used for source, drain, gate and via
interconnection.
and a non-linear representation of RC to enable reliable DC
analysis. The UOTFT model also includes Leroux’s charge
model that describes voltage-dependent capacitance that con-
forms to the charge-conservation law, and an overlap capaci-
tance model for a linear AC analysis, which are common for
other types of TFTs. In this study, we used the UOTFT model
and SmartSPICE for compact modelling and SPICE simula-
tion of inkjet-printed organic FETs and ICs.
3. Results and discussion
3.1. Flexible printed organic FETs and inverters
3.1.1. Device structure. A flexible printed organic comple-
mentary inverter (figure 2) was realized using a 3D integration
technique by which a p -type organic FET (PFET) was fabri-
cated on top of an n-type organic FET (NFET). The design
rule behind the 3D device structure of the inverter was clearly
achieved by device physics and inkjet printing technology. To
avoid the difficulty of printing Ag ink on an organic semicon-
ductor layer when fabricating a 3D transistor-on-transistor
structure with a shared gate electrode, a coplanar configura-
tion was chosen for the top transistor, whereas a staggered
configuration was chosen for the bottom transistor. Then a
p -type organic semiconductor with a higher charge carrier
mobility than an n-type organic semiconductor was used as
the top transistor to compensate for its larger RC due to copla-
nar contact configuration. The gate electrode was printed with
multiple Ag lines so that it covers the source and drain con-
tacts, and the channel. Therefore, the Lov was determined as
the linewidth of the source or the drain contact for both PFET
and NFET. After fabrication, the IC was detached from the
supporting glass. The parylene layer was mechanically strong,
and a neutral plane was established by the passivation layer
and the basement layer [29], so the IC fabricated on a parylene
thin-film exhibits excellent mechanical flexibility [12]. The
complete fabrication method is described in [14].
3
S Jung et al
Figure 3. (a) Transfer and (b) output characteristics of NFET and
PFET obtained by measurement (symbols) and SPICE simulation
(solid lines).
3.1.2. Transfer and output characteristics. Digital circuits
require careful design of transistors by complementary match-
ing. Ideally, to achieve a reliable complementary design,
the transfer and output characteristics of an NFET must be
matched to those of a PFET. The transfer and output charac-
teristics of NFET and PFET (figure 3) both showed good bal-
ance, and achieved a maximun drain current IDS of  ±0.3 µA
at drain-source voltages VDS of  ±20 V for NFET and PFET.
These characteristics were achieved by tailoring di­electric
layer thickness and the channel aspect ratio (W/L) of the
NFET and PFET; this capability is a benefit of the 3D integra-
tion technique [30].
A qualitative interpretation of the transfer and output char-
acteristics gives basic information on a given device, whereas
quantitative analysis by means of extracted transistor param­
eters enables a comprehensive understanding of the device
and helps to predict the circuit behaviour by applying SPICE
simulation.
Transistor parameters (table 1) of NFET and PFET that
were extracted by the UOTFT model [19]. Threshold voltage
is higher for the NFET (Vth  =  5.52 V) than for the PFET
(Vth  =  −1.04 V). We note also a slight shift of Vth with VDS
in NFET (~4 V), which, together with a larger characteristic
voltage Vo of the trap density of states, suggestst that the NFET
has more shallow and deep traps than the PFET has [31, 32].
The difference may originate from both material and process.
P(NDI2OD-T2) used as an n-type semiconductor material
develops moderate intra-gap trap states during oxygen expo-
sure [33]. However, the NFET has a top gate staggered geom-
etry, so degradation during the subsequent gate dielectric layer
deposition process on the n-type semiconductor layer cannot
be ruled out, whereas the channel of the upper p -type OFET
is free of damage from the subsequent gate-dielectric layer
deposition. The effects of shift in Vth on the voltage transfer
characteristics of an inverter are discussed in the following
sub-section. µFET at VGS  =  ±20 V was about four times
higher in the PFET (3.22  ×  10−2 cm2 (V−1 s−1)) than in the
J. Phys. D: Appl. Phys. 52 (2019) 444005 S Jung et al

Table 1. Transistor parameters for SPICE simulation.

Values
Parametersa NFET PFET Units
W 973 372 µm
L 26.7 10.6 µm
Lov 200 200 µm
ti 230 440 nm
µi 4.1ε0 4.1ε0 F/cm
εs 3ε0 3ε0 F/cm
Vth 5.52 −1.04 V
Vo 1.5 0.3 V
µacc 0.01 0.01 cm2/Vs
Vacc 1.95  ×  101 5.34  ×  103 V
γ 0.88 −0.35 −
µFETb 7.70  ×  10−3 3.22  ×  10−2 cm2/Vs
λ 9.50  ×  10−4 7.00  ×  10−3 1/V
m 2.98 7.00 −
α 0.95 1.65 −
RDS 5.00  ×  105 6.23  ×  108 Ω
VRDS 0.1 −0.1 V
σo 1.18  ×  10−14 1.19  ×  10−13 S
Cgsov (=Cgdov)c 30.7 6.14 pF
Cgsoth (=Cgdoth)c 246 49.2 pF
a
W: channel width, L: channel length, Lov: overlap length, ti: gate dielectric
thickness, εi and εs; dielectric constants of gate dielectric material and
semiconductor, respectively, Vth: threshold voltage, Vo: characteristic voltage
of the trap density of states, µacc: characteristic effective accumulation
channel mobility, Vacc: characteristic voltage of the effective mobility, γ:
power-law exponent for the gate-voltage dependent field-effect mobility,
λ: output conductance parameter, m: knee-shape parameter, α: saturation
modulation parameter, RDS: zero-bias nonlinear drain-source resistance, Figure 4. (a) Voltage transfer curve of the inverter. (b) Gain of
VRDS: characteristic voltage for RDS, σo: minimum bulk conductance. inverter. SNM is the static noise margin. Vm is the switching
b
Field effect mobility calculated at 20 V. threshold. Symbols: measurement data. Solid lines: SPICE
c
Gate-source and gate-drain overlap capacitance (Cgsov and Cgdov) and other simulation results.
parasitic gate-source and gate-drain capacitance (Cgsoth and Cgdoth) without
Miller effect included.

NFET (7.70  ×  10−3 cm2 (V−1 s−1)). µFET varied differently
with respect to the effective gate-source voltage |VGS  −  Vth|
in each device; in the PFET (i.e. γ  <  0) µFET decreases with
increase in |VGS  −  Vth|, whereas in the NFET, µFET increased
with increase in |VGS  −  Vth| (γ  >  0) [34].
RC was higher in the PFET (6.23  ×  108 Ω) than in the NFET
(5.00  ×  105 Ω). The large RC of PFET reduces the effective
drain-source voltage applied to the channel, so saturation in
the output characteristics is delayed (figure 3(b)) This analysis
has shown the applicability of the UOTFT model to flexible
printed OFETs that are composed of an NFET and a PFET,
and has demonstrated the advantages of the UOTFT model to
interpret and compare two distinct types of OFETs.
3.1.3. Voltage transfer characteristics. SPICE simulation
using the extracted transistor parameters accurately predicted
the behaviour of the 3D integrated flexible printed organic
complementary inverter. Furthermore, these parameters have
clear physical meaning. The analogue characteristics of the
inverter were examined by evaluating the voltage transfer
characteristics that describe the variation of output voltage
Vout with changes in input voltage Vin at VDD  =  10 V and
20 V. Simulations used SmartSPICE and the UOTFT model
implemented in the simulator [22]. Measured data matched
simulation results well over a wide range of operation (figure
4), as confirmed by estimating the static noise margin (SNM),
inverter threshold VM and gain G.
The errors of the SNM between measurement and simula-
tion were ~1% at both VDD. VM was 7 V at VDD  =  10 V, and
14 V VDD  =  20 V; these were larger than VDD/2 because the
magnitude of Vth is larger in an NFET than in a PFET. Despite
its deviation from VDD/2, VM was predictable either by SPICE
simulation or as
Ä ä
Vth.n + VDSAT.n
V
+ r VDD + Vth.p + DSAT.p
(1) 2 2
VM = ,
1+r
where r  =  knVDSAT.n/(kpVDSAT.p). The positive-shifted
threshold voltage of NFET with VDS, which was not taken into
account in the compact model, caused a 4% positive shift in
the measured voltage transfer curve compared to the simu-
lated curve. This shift was 0.4 V at VDD  =  10 V, and 0.8 V at
VDD  =  20 V.

4
J. Phys. D: Appl. Phys. 52 (2019) 444005
Figure 5. (a) Circuit schematic diagram for the 11-stage ring
oscillator with a five-stage inverting buffers. (b) Magnification of
a stage between n and n  +  1 node consisting of two organic FETs
and four parascitic capacitances: Cgc.n and Cgc.p denote channel
capacitance. Cgsp and Cgdp denote gate-source and gate-drain
parasitic capacitances that contain overlap (Cgsov or Cgdov) and other
(Cgsoth or Cgdoth) capacitances (Cgsp  =  Cgsov  +  Cgsoth). (c) Oscillation
frequency of the ring oscillator and the delay time of the inverter
extracted from measured and simulated output characteristics.
(d) Measured and simulated transient output voltage of the ring
oscillator.
However, the maximum value of G was overestimated by
190% at VDD  =  10 V and by 66% at VDD  =  20 V. G of a com-
plementary inverter is expressed as [35]:
1+r
G= 
(2)  . the timing delay of the single inverter decreased from 2.7 s
VM − Vth.n − VDSAT.n
2 (λn − λp )
The discrepancy may be a result of error in the transistor
parameters, i.e. r, VM, Vth.n, VDSAT.n and λ, and of the positive
Vth-shift of the NFET. The error between the measured and
simulated ID of the NFET increased with decrease in VGS, so
the error in G was larger at VDD  =  10 V than at VDD  =  20 V.
5
S Jung et al
Figure 6. Contribution from channel (Cch  =WnLnCi.n  +  Wp Lp Ci.p ),
overlap (Cov  =  4WnLov.nCi.n  +  4WpLov.pCi.p) and other (ΣCF
capacitances in a complementary printed organic ring oscillator.
Miller effect is present in the contributions from both overlap and
other capacitance. Data from (a) this study, (b) Lin et al, (c) Klauk
et al, and (d) Valletta et al.
3.2. Flexible printed organic ring oscillators
3.2.1. Transient output characteristics. Next, we used experi-
ment and simulation to study the electrical characteristics of
an 11-stage voltage-controlled ring oscillator (figure 5(a)).
Transient output voltage was measured through a five-stage
inverting buffer attached to the output of the ring oscillator;
this configuration was used to eliminate the loading effect
that the probe causes to the measurement (Cprobe  =  3 pF).
The SPICE simulation for the transient output voltage was
done by considering the absence or existence of various ele-
ments for the parasitic capacitance in the device, i.e, case I:
Cp  =  Cov; case II: Cp  =  Cov   +  Coth, where Cov is the overlap
capacitance and Coth the other capacitances (magnified view
in figure 5(b)).
The ring oscillator had high G, and therefore produced a
nearly trapezoidal wave form with a swing between VDD and
ground, rather than a sinusoidal wave form. The measured
oscillation frequency f osc of the ring oscillator varied from
~0.02 to ~3 Hz when VDD was increased from 10 to 30 V, and
to 14 ms. The simulated output voltage characteristics agreed
well with the measurements (figure 5(d)). The difference
between simulated and measured data increased with decrease
in VDD (figure 5(c)); this trend may be a result of the abnormal
Vth shift of the NFET with VDS and the concomittant simula-
tion error at low VGS (figure 3(a)).
J. Phys. D: Appl. Phys. 52 (2019) 444005 S Jung et al

Table 2. Parameters used to compare the contribution from channel, overlap and other parasitic capacitances.

Nstage f osc tD |VDD| W L Lov Cch Cov ΣCF

Papers Technology Process — Hz s V µm µm µm pF pF pF Ref.
This study Complementary Inkjet printing 11 3 15m 30 973 27 200 7a 147a 1183 —
372 106 200
Lin et al Complementary Evap.d 5 2k 38µ 100 100 4 10 0.06a 4.50a c
[35]
100 4 10
Klauk et al Unipolare Evap. 5 0.5k 200µ 5 100 10 10 12b 39b 18 [36]
50 50 10
Valletta et al Unipolare Evap.d 11 5k 9.1µ 50 200 100 38 0.48a 1.52a c
[37]
400 50 95
a
Estimated by SPICE simulation.
b
Estimated by fitting by model in [18].
c
Attributed to Cov.
d
Additional lithography process for patterning.
e
Miller effect for a unipolar ring oscillator is estimated by model in [18].

3.2.2. Overlap capacitance. For the analysis of transient
output voltage, all the device intrinsic capacitances Cint and
extrinsic capacitances Cext, i.e. output capacitance of the n-th
inverter for the former and input capacitance of the (n  +  1)th
inverter and the wire capacitance for the latter, are combined
into an equivalent load capacitance CL between the output
node of the n-th inverter and the ground: CL  =  Cint  +  Cext.
Under the first-order approximation for a complementary
ring oscillator [36], Cint is the gate-drain capacitance CGD of
the load and driver transistors, and is composed of the gate-
channel capacitance Cgcd of the drain side, and the gate-drain
parasitic capacitance Cgdp, i.e. CGD  =  Cgcd  +  Cgdp. In addi-
tion, Cext is the gate capacitance CG of the load and driver tran-
sistors, and is composed of the gate-channel capacitance Cgc,
gate-drain parasitic capacitance Cgdp and gate-source parasitic
capacitance Cgsp: CG  =  Cgcd  +  Cgcs  +  Cgdp  +  Cgsp. Then the
load capacitance can be expressed as channel capacitance Cch,
overlap capacitance Cov and other capacitances ΣCF:
CL ≈ CGD.n + CGD.p + CG.n + CG.p + ΣCF
≈ Wn Ln Ci.n + Wp Lp Ci.p + 4Wn Lov.n Ci.n + 4Wp Lov.p Ci.p + ΣCF
      
channel overlap
(3)
where the channel capacitances that vary according to the
operation regime were described using Leroux’s charge-based
capacitance model [22], and the Miller effect accounted for a
part of the parasitic capacitance that originated from CGD [35].
The simulated oscillation frequency was ~60 Hz at
VDD  =  30 V considering solely the channel capacitance,
which is significantly higher (~20 times) than the measured
frequency (3.14 Hz at VDD  =  30 V). The simulated oscilla-
tion frequency decreased to 23 Hz when the gate-source and
gate-drain overlap capacitances (Cgsov.n  =  Cgdov.n  =  30.7 pF
for NFET; Cgsov.p  =  Cgdov.p  =  6.14 pF respectively for PFET)
were considerd. These capacitances were calculated from
the measured dielectric constant, gate dielectric thickness,
channel width and overlap length (table 1).
The overlap capacitance is a more dominant element
than channel capacitance of the load capacitance of inkjet-
printed organic ring oscillators (figure 6 and table 2). It is
also dominant in evaporated organic-ring oscillators that are
based on short-channel organic transistors [18]. In detail,
due to the Miller effect and the greater combined area of
gate-source and gate-drain overlap area than the channel
(L/Lov  =  27 µm/200 µm for the driver transistor), the overlap
capacitance leads to a 21 times larger contribution (147 p) than
the channel capacitance does (7 pF). Despite this large dis-
crepency, additional consideration for other parasitic capaci-
tances may improve the estimate of oscillation frequency.
3.2.3. Other parasitic capacitances. Other factors such as
wiring, fringe effect, inverting buffer and probe could con-
tribute to the load capacitance [37]. Considering the other
parasitic capacitances Coth of 246 pF and for NFET and
49.2 pF for the PFET (ignoring the Miller effect), the simu-
lated oscillation frequency became 3.16 Hz, which matches
well with the measured oscillation frequency of 3.14 Hz (at
VDD  =  30 V). Analysis on the contribution of parasitic capaci-
tances have been reported mostly on organic ring oscillators
that have been fabricated by evaporation [37–39]: reports on
flexible inkjet-printed organic ring oscillators are rare. We
observed that the contribution of other parasitic capacitances
others
is greater than that of channel capacitance (figures 6(a), (c) and
table 2). For the evaporated ring oscillators, we also observed
that the contribution of parasitic capacitances is larger when
the ratio of L to Lov is larger.
This analysis shows that the parasitic capacitance seriously
reduces the speed of a ring oscillator. The short-channel effect
becomes pronounced at the channel length L  <  10 µm, which
is similar to the channel length of the printed OFETs (27 µm)
[40]. The oscillation frequency of the fabricated ring oscillator
makes it suitable for the processing of physical, physiological
or electrical biosignals [41]. Further improvement in inkjet-
printed organic circuits may be obtained by engineering the
parasitic capacitances by reducing the gate length, and hence
the overlap length Lov [42].
4. Conclusion
We have demonstrated the importance and feasibility of using
modelling-driven design and analysis to guide development

6
J. Phys. D: Appl. Phys. 52 (2019) 444005
of flexible printed organic FETs and ICs. Compact modelling
enabled successful design of an NFET and a PFET, which had
distinct types of transfer and output characteristics, which led
to a good balance in the voltage transfer curve of the flexible
printed organic complementary inverter. The extracted tran-
sistor parameters gave an excellent fit between measured and
simulated electrical behaviours of the NFET, the PFET, and
the organic complementary inverter so quantitative evalua-
tion of these devices and circuits was possible. A comparative
study of the measured and simulated transient output charac-
teristics of the flexible printed organic ring oscillator showed
that parasitic capacitances are dominant factors that deter-
mine the transient behaviour of the ring oscillator. Our work
provides insights that guides further improvement of flexible
printed organic FETs and ICs, and may enable realisation
of more-complex organic ICs and unconventional electronic
applications.
Acknowledgments
This work was supported in part by the Center for Advanced
Soft-Electronics funded by the Ministry of Science and ICT as
Global Frontier Project (CASE-2015M3A6A5072945) and in
part by the IT consilience Creative Program supervised by the
Institute for Information and Communications Technology
Promotion under Grant IITP-2019-2011-1-100783 and Basic
Science Research Program through the National Research
Foundation of Korea (NRF) funded by the Ministry of Educa-
tion (NRF-2018R1D1A1B07048877).
ORCID iDs
Sungyeop Jung https://orcid.org/0000-0003-2669-1797
Jimin Kwon https://orcid.org/0000-0002-5213-1323
Gilles Horowitz https://orcid.org/0000-0002-3222-1428
Yvan Bonnassieux https://orcid.org/0000-0003-4413-2067
Sungjune Jung https://orcid.org/0000-0001-9258-0572
References
[1] Myny K, van Veenendaal E, Gelinck G H, Genoe J,
Dehaene W and Heremans P 2011 An 8-bit, 40-instructions-
per-second organic microprocessor on plastic foil IEEE J.
Solid-State Circuits 47 284–91
[2] Someya T, Sekitani T, Iba S, Kato Y, Kawaguchi H and
Sakurai T 2004 A large-area, flexible pressure sensor
matrix with organic field-effect transistors for artificial skin
applications Proc. Natl Acad. Sci. USA 101 9966–70
[3] Kim Y et al 2018 A bioinspired flexible organic artificial
afferent nerve Science 360 998–1003
[4] Jung S and Hutchings I M 2012 The impact and spreading
of a small liquid drop on a non-porous substrate over an
extended time scale Soft Matter 8 2686
[5] Sirringhaus H, Kawase T, Friend R H, Shimoda T,
Inbasekaran M, Wu W and Woo E P 2000 High-resolution
inkjet printing of all-polymer transistor circuits Science
290 2123–6
7
S Jung et al
[6] Jung S, Sou A, Gili E and Sirringhaus H 2013 Inkjet-printed
resistors with a wide resistance range for printed read-only
memory applications Org. Electron. 14 699–702
[7] McKerricher G, Gonzalez Perez J and Shamim A 2015 Fully
inkjet printed RF inductors and capacitors using polymer
dielectric and silver conductive ink with through vias IEEE
Trans. Electron Devices 62 1002–9
[8] McKerricher G, Vaseem M and Shamim A 2017 Fully inkjet-
printed microwave passive electronics Microsyst. Nanoeng.
3 16075
[9] Mitra K Y, Sternkiker C, Martínez-Domingo C, Sowade E,
Ramon E, Carrabina J, Gomes H L and Baumann R R 2017
Inkjet printed metal insulator semiconductor (MIS) diodes
for organic and flexible electronic application Flex. Print.
Electron. 2 15003–11
[10] Chung S, Kim S O, Kwon S-K, Lee C and Hong Y 2011
All-inkjet-printed organic thin-film transistor inverter
on flexible plastic substrate IEEE Electron Device Lett.
32 1134–6
[11] Ng T N et al 2012 Scalable printed electronics: an organic
decoder addressing ferroelectric non-volatile memory Sci.
Rep. 2 585
[12] Fukuda K, Takeda Y, Yoshimura Y, Shiwaku R, Tran L T,
Sekine T, Mizukami M, Kumaki D and Tokito S 2014
Fully-printed high-performance organic thin-film transistors
and circuitry on one-micron-thick polymer films Nat.
Commun. 5 4147
[13] Mandal S et al 2015 Fully-printed, all-polymer, bendable
and highly transparent complementary logic circuits Org.
Electron. 20 132–41
[14] Kwon J, Takeda Y, Fukuda K, Cho K, Tokito S and Jung S
2016 Three-dimensional, inkjet-printed organic transistors
and integrated circuits with 100% yield, high uniformity,
and long-term stability ACS Nano 10 10324–30
[15] Horowitz G 1998 Organic field-effect transistors Adv. Mater.
10 365–77
[16] Kim C H, Hlaing H, Yang S, Bonnassieux Y, Horowitz G
and Kymissis I 2014 Organic electronics Org. Electron.
15 1724–30
[17] Marinov O, Deen M J, Zschieschang U and Klauk H 2009
Organic thin-film transistors: part I-compact DC modeling
IEEE Trans. Electron Devices 56 2952–61
[18] Marinov O and Deen M J 2013 Quasistatic compact modelling
of organic thin-film transistors Org. Electron. 14 295–311
[19] Iñiguez B, Picos R, Veksler D, Koudymov A, Shur M S,
Ytterdal T and Jackson W 2008 Universal compact model
for long- and short-channel thin-film transistors Solid. State.
Electron. 52 400–5
[20] Matsui H, Hayasaka K, Takeda Y, Shiwaku R, Kwon J and
Tokito S 2018 Printed 5 V organic operational amplifiers for
various signal processing Sci. Rep. 8 8980
[21] Gildenblat G S 2010 Compact Modeling : Principles,
Techniques and Applications (Berlin: Springer)
[22] Silvaco 2019 SmartSpice Analog Circuit Simulator (Santa
Clara, CA: Silvaco)
[23] Jung S 2016 Physically-based compact modelling of organic
electronic devices PhD Thesis, Ecole Polytechnique,
Universite Paris-Saclay, Palaiseau
[24] Horowitz G, Hajlaoui M E and Hajlaoui R 2000 Temperature
and gate voltage dependence of hole mobility in
polycrystalline oligothiophene thin film transistors J. Appl.
Phys. 87 4456–63
[25] Richards T J and Sirringhaus H 2007 Analysis of the contact
resistance in staggered, top-gate organic field-effect
transistors J. Appl. Phys. 102 94510–7
[26] Kwon J, Jung S, Kim Y-H and Jung S 2019 Bistaggered
contact geometry for symmetric dual-gate organic TFTs
IEEE Trans. Electron Devices 66 3118–23
J. Phys. D: Appl. Phys. 52 (2019) 444005
[27] Kwon J, Matsui H, Kim W, Tokito S and Jung S 2019 Static
and dynamic response comparison of printed, single-and
dual-gate 3D complementary organic TFT inverters IEEE
Electron Device Lett. 8 1277–80
[28] Khan S, Lorenzelli L and Dahiya R S 2015 Technologies
for printing sensors and electronics over large flexible
substrates: a review IEEE Sens. J. 15 3164–85
[29] Sekitani T, Zschieschang U, Klauk H and Someya T 2010
Flexible organic transistors and circuits with extreme
bending stability Nat. Mater. 9 1015–22
[30] Kwon J, Kyung S, Yoon S, Kim J-J and Jung S 2016 Solution-
processed vertically stacked complementary organic circuits
with inkjet-printed routing Adv. Sci. 3 1500439
[31] Meijer E J, Tanase C, Blom P W M, van Veenendaal E,
Huisman B H, de Leeuw D M and Klapwijk T M 2002
Switch-on voltage in disordered organic field-effect
transistors Appl. Phys. Lett. 80 3838–40
[32] Jung S, Kim C H, Bonnassieux Y and Horowitz G 2015
Fundamental insights into the threshold characteristics
of organic field-effect transistors J. Phys. D: Appl. Phys.
48 035106
[33] Di Pietro R, Fazzi D, Kehoe T B and Sirringhaus H 2012
Spectroscopic investigation of oxygen- and water-induced
electron trapping and charge transport instabilities in n-type
polymer semiconductors J. Am. Chem. Soc. 134 14877–89
[34] Estrada M, Cerdeira A, Puigdollers J, Reséndiz L, Pallares J,
Marsal L F, Voz C and Iñiguez B 2005 Accurate modeling
S Jung et al
and parameter extraction method for organic TFTs Solid.
State. Electron. 49 1009–16
[35] Sze S M and Ng K K 2006 Physics of Semiconductor Devices
(Hoboken, NJ: Wiley)
[36] Rabaey J M 1996 Digital Integrated Circuits : a Design
Perspective (Englewood Cliffs, NJ: Prentice-Hall)
[37] Lin Y-Y, Dodabalapur A, Sarpeshkar R, Bao Z, Li W,
Baldwin K, Raju V R and Katz H E 1999 Organic
complementary ring oscillators Appl. Phys. Lett.
74 2714–6
[38] Klauk H, Zschieschang U and Halik M 2007 Low-voltage
organic thin-film transistors with large transconductance
J. Appl. Phys. 102 074514
[39] Valletta A, Demirkol A S, Maira G, Frasca M, Vinciguerra V,
Occhipinti L G, Fortuna L, Mariucci L and Fortunato G
2016 A compact SPICE model for organic TFTs
and applications to logic circuit design IEEE Trans.
Nanotechnol. 15 754–61
[40] Chabinyc M L, Lu J-P, Street R A, Wu Y, Liu P and
Ong B S 2004 Short channel effects in regioregular
poly(thiophene) thin film transistors J. Appl. Phys.
96 2063–70
[41] Naït-Ali A 2009 Advanced Biosignal Processing (Berlin:
Springer)
[42] Noh Y-Y, Zhao N, Caironi M and Sirringhaus H 2007
Downscaling of self-aligned, all-printed polymer thin-film
transistors Nat. Nanotechnol. 2 784–9