1 School: Electrical Eng. & Computing Department: Electronics & Communication Eng.

2 Course Category Major Mandatory

Course Name Digital Logic Design
Course Code: ECEg3201
3 Synopsis: In this course, students will study various digital logic families such as TTL, ECL,
and CMOS, the logic gates under these families, and the electronic circuit
techniques used to implement them. Subsequently, they will learn Boolean algebra,
logic expressions, number systems and combinational logic design, including logic
minimization and hazards. In addition, with the understanding of combinational
logic design, students will learn how to design sequential systems, including
analysis of the behavior of synchronization elements and system timing design.
Finally, in this course, students will have hands-on design experiences by carrying
out experiments with component-level devices and designing digital systems.
4 Name(s) of Mr.Tadesse Hailu
Academic Staff: Mr.Tesfaye Benti
Mr.GemechuDengai
Dr.G.Subba Rao
Dr.Davinder Singh Rathee
Mr.Amanuel Getachew
5 Semester and Semester: I Year: III
Year offered:
6 Credit Hour: 4
7 Prerequisite/ Co- ECEg2201 Electronics Circuits I
requisite: (if
any)
8 Course Learning Outcome (CLO): At the end of the course the student will be able to do:

CLO1 Distinguish the analog and digital systems and apply positional notations, number systems
and computer codes in digital systems.
CLO2 Design and implement a logic circuit using various logic gates
CLO3 Apply Boolean algebra and Karnaugh maps to simplify and design logic circuits.
CLO4 Apply the concepts of combinational and sequential logic in digital systems
 CLO5 Design shift registers for various applications in digital systems
CL06 Apply the concept of combinational and sequential circuits in memory devices
Mapping of the course Learning Outcomes to the program Learning Outcomes, Teaching Methods and
Assessment:
Program Learning Outcomes (PO)
Outcomes (CLO)
Course Learning

Assessment
9 Teaching

Assignmen
Laboratory
PO10
PO11
PO12

tMid Exam
PO1
PO2
PO3
PO4
PO5
PO6
PO7
PO8
PO9
Methods
L T P O

Exam
Final
Quiz
CLO1 √ √ √ √ √ √

CLO2 √ √ √ √ √ √ √ √ √ √ √

CLO3 √ √ √ √ √ √ √ √ √

CLO4 √ √ √ √ √ √ √ √ √ √ √

CLO5 √ √ √ √ √ √ √ √ √ √ √

CLO6 √ √ √ √ √ √ √ √ √

Indicate the relevancy between the CLO and PO by ticking “√”on the appropriate relevant box
10 Transferable Skills (if applicable)
(Skills learned in the course of study which can be useful and utilized in other settings)
1 Computer Systems
2 Computer Architecture

3 VLSI circuits and systems

11 Distribution of Student Learning Time (SLT)
Teaching and Learning Activities Total
CLO Guided learning Guided Independent (SLT)
Course Content Outline (F2F) Learning Learning
(NF2F) (NF2F)
L T P O
Chapter 1: 15hr
INTRODUCTION, CLO
√ √ √ √ √
NUMBER SYSTEMS 1

AND CODES
1.1 Analog Vs Digital
Quantities and
Representations
1.2 Advantages and limitations
of Digital over analog system
1.3 Types logic Families
1.4 Decimal number AND
Binary number
1.5 Decimal to binary
conversation
1.6 Hexadecimal number
AND Octal number
1.7 1’s and 2’s compliment of
binary number
1.8 BCD codes and its uses
Chapter 2: CLO √ √ √ √ √ 20hr
2
Digital Logic Gates
2.1 The NOT gate, logic
symbol, output expression
2.2 The AND gate, logic
symbol, output expression
2.3 The OR gate, logic symbol,
output expression
2.4 The NAND gate, logic
symbol, output expression
2.5 The NOR gate, logic
symbol, output expression
2.6 The EX-OR AND EX-
NOR gate, logic symbol,
output expression
Chapter 3: 20hr
CLO
Boolean algebra and √ √ √ √ √
3
Logic expression
simplification
3.1 Boolean Operation and
Expression
3.2 Basic Theorems, Laws and
Rules of Boolean Algebra
3.3 Boolean Functions and
Truth Tables
3,4 Standard and Canonical
forms of Boolean Algebra
3.5 Simplification of Boolean
Functions:
Algebraic Simplification
Karnaugh Maps Or K-Maps
3.6 Techniques for Minimal
SOP and POS Forms
3.7 The Use of Don’t Care
Conditions
Chapter 4: √ √ √ √ √ 20hr
CLO
Analysis and Synthesis of
4
Combinational Logic
Circuits
4.1 Design of Combinational
Logic Circuits
4.2 Basic combinational logic
circuits
4.3 Implementing
Combinational logic
4.4 Universal property of
NAND and NOR gates
4.5 Functions of combinational
logic
4.5.1 Basic Adder
4.5.2 Comparator
4.5.3 Encoder and Decoder
4.5.4 Multiplexer and
Demultiplexer
4.5.5 Parity
generator/checker
Chapter 5: √ √ √ √ √ 20hr
CL04
Sequential logic circuit
5.1. Sequential logic circuit
 Flip flops
 Latches
 Edge triggered flip flops
 Master slave flip flops
Applications
5.2. Counters
 Asynchronous counters
 Synchronous counters
 Design of synchronous
counters
Chapter 6: √ √ √ √ √ 15hr
CL05
Shift registers
 Basic shift registers
 Serial in serial out
registers
  Serial in parallel out
Registers
 Parallel in serial out
Registers
 Parallel in parallel out
registers
Jonson’s counter
Chapter 7 CL06 √ √ √ √ √ 20 hr.
Memory and
Programmable Logic
 Random-Access Memory
 Memory Decoding
 Read-Only Memory
 Programmable Logic
Array
 Programmable Array
Logic
Total 130hr
Assessment
Continuous Assessment Percentage
F2F NF2F SLT
Total-60(%)

1 Quiz 10% √ 1hr.

2 Lab-report 20 % √ √ 14hr
3 Assignment 10% √ √ 10hr
4 Mid exam 20% √ 2hr
5

Total 27 hr.
Final Exam Percentage 40 F2F NF2F SLT
(%)
Final Exam √ 3hr
Grand Total SLT 160 hr.
L = Lecture, T = Tutorial, P = Practical, O = Others, F2F = Face to Face, NF2F = Non Face to Face
Note: indicates the CLO based on the CLO’s numbering in item 9.
Special 1 MATLAB Software
requirements and 2 Computer lab
resources to deliver
the course (e.g. 3 Simulation Room
software, computer 4
lab, simulation
room …etc.) 5
Textbook and 1 Morris M. Mano: Digital Design (4th Edition)
reference: 2 R. J. Tocci and N. S. Widmer: Digital Systems – Principles and
Applications, 9th Ed, Prentice Hall, 2004
(note: ensure the
3 Stephen Brown, ZvonkoVranesic: Fundamentals of Digital Logic with
latest edition Verilog Design, McGraw-Hill Science/Engineering/Math; 1st edition
2002
/publication)
4 T.L. Floyd: Digital Fundamentals, 9th edition, Prentice Hall