D31 Umang parmar subject: VLSI physical Design

Q.1 Design specifications which includes introduction to vending machine, architectural and
functional descriptions.

Ans:

1. Introduction:

The vending machine is an automated device designed to dispense products or services to

customers in exchange for money or tokens. It offers a convenient way for users to access
items such as snacks, beverages, tickets, or other small goods without the need for human
intervention. The following design specifications outline the architecture and functionality of the
vending machine.

2. Architectural Description:

The vending machine consists of the following key components:

- User Interface: A display screen and input interface (e.g., keypad, touch screen) allow users to
interact with the machine.

- Product Storage: Internal compartments or shelves hold different products, each identified by
a unique code or label.

- Payment System: This system enables users to make payments using coins, bills, or digital
payment methods like cards or mobile wallets.

- Dispensing Mechanism: Mechanisms for selecting and delivering the chosen product to the
user, often involving motors, conveyors, and sensors.

- Control Unit: The central processing unit that manages user input, product selection, payment
processing, and dispensing operations.

- Power Supply: Provides the necessary electrical power to operate the machine's components.

3. Functional Description:

The vending machine operates based on the following sequence of events:

- User Interaction: The user approaches the machine and interacts with the user interface to
select a desired product.

- Product Selection: The user selects a product by entering its corresponding code or label using
the input interface.

- Payment Processing: The payment system calculates the total cost of the selected product
and accepts the user's payment, either in the form of coins, bills, or digital payment methods.

- Product Dispensing: Once payment is verified, the dispensing mechanism is activated. It

locates the selected product, retrieves it from the appropriate storage compartment, and
delivers it to the user.

- Transaction Completion: The machine displays a confirmation message to the user indicating
successful product dispensing.

- Change (if applicable): If the user's payment exceeds the product price, the machine calculates
and returns any change due.

- Error Handling: The machine should handle scenarios such as insufficient payment, out-of-
stock products, or malfunctioning components. Appropriate error messages are displayed, and
the user is guided through corrective actions.

Q.2 RTL Design overview.

Ans:

RTL (Register Transfer Level) design is a crucial step in digital circuit design. It involves
describing a digital circuit's behavior using a hardware description language (HDL), such as
Verilog or VHDL. At this level, designers define how data flows between registers, how logic
operations are performed, and how components interact.

RTL design abstracts away low-level details and focuses on the functional behavior of the
circuit. It's a vital step before actual circuit synthesis and implementation. Designers use RTL
descriptions to simulate and verify the circuit's functionality, identify potential issues, and
optimize the design before moving to the physical design phase.

RTL design involves creating modules that represent different components of the circuit and
specifying how these modules interact. This includes describing data paths, control signals, and
timing constraints. Once the RTL description is complete, it's synthesized into gate-level
representations for actual chip implementation.
Overall, RTL design serves as a bridge between high-level functional specifications and the
physical layout of a digital circuit, playing a crucial role in the hardware design process.

Q.3 Physical Design Overview including all intermediate steps of floor plan, cell placement and
physical verification(DRC/LVS).

Ans:

Physical Design Overview with Intermediate Steps:

1. Floor Planning:

Floor planning is the initial step in physical design where the chip's layout is divided into
functional blocks. It involves defining the chip's core area, placing macros (large pre-designed
functional blocks), and allocating space for routing channels. The goal is to achieve efficient
use of silicon real estate while minimizing signal delay and congestion.

2. Cell Placement:

In this step, individual standard cells (basic logic gates) are placed within the functional blocks.
The objective is to minimize wirelength, optimize for timing, and satisfy any placement
constraints. Advanced algorithms are used to achieve balanced placement and reduce signal
delay.

3. Power Planning:

Power planning involves distributing power and ground grids throughout the design to ensure
stable power delivery and proper functioning of the components. Decoupling capacitors are
strategically placed to mitigate voltage fluctuations.

4. Clock Tree Synthesis (CTS):

CTS is the process of creating a clock distribution network that ensures clock signals reach all
parts of the design with minimal skew and delay. Clock trees are built to maintain
synchronization across different parts of the chip.

5. Routing:
Routing involves creating metal tracks to connect the placed cells while adhering to design rules
and minimizing congestion. Global routing defines the major signal paths, followed by detailed
routing that connects individual nets.

6. Design Rule Checking (DRC):

After routing, a DRC is performed to check if the layout adheres to manufacturing rules defined
by the foundry. These rules include minimum width, spacing, and other geometrical constraints.
Violations are identified and need to be fixed.

7. Layout vs. Schematic (LVS) Verification:

LVS is a process that compares the physical layout against the original schematic design to
ensure they match accurately. It checks if the fabricated layout accurately represents the
intended circuit functionality.

8. Extraction:

During extraction, parasitic elements (resistors, capacitors) are extracted from the layout. These
parasitics affect circuit performance and need to be considered during post-layout simulation
and analysis.

9. Post-Layout Simulation:

Simulations are performed using extracted parasitics to verify that the circuit still meets its
performance requirements, such as timing and power consumption.

10. Tapeout:

Once the layout is finalized and verified, the design is ready for fabrication. The entire design
data is packaged and sent to the semiconductor foundry for manufacturing.

11. Design for Manufacturing (DFM):

DFM involves optimizing the layout to enhance manufacturability, yield, and reliability. It
addresses potential manufacturing challenges and variations that could affect the final product.
12. Physical Verification (PV):

PV is a comprehensive check that includes DRC, LVS, and other checks like Antenna Rule Check
(ARC) and Design for Reliability (DFR). It ensures the layout adheres to design rules, accurately
represents the intended circuit, and meets reliability criteria.

Q.4 Timing analysis and power analysis.

Ans:

Timing Analysis:

Timing analysis is a critical step in digital design that ensures that a circuit's operation occurs
within specified time constraints. It focuses on assessing the propagation delays of signals
through the logic gates and paths in a design. There are two main aspects of timing analysis:

1. Static Timing Analysis (STA): STA analyzes the worst-case timing delays in a design. It
considers factors such as gate delays, interconnect delays, and clock skew. STA helps identify
potential violations of setup and hold time requirements, ensuring that signals arrive at their
destinations with appropriate timing margins.

2. Dynamic Timing Analysis:This involves considering the impact of varying conditions on

timing, such as process variations and supply voltage changes. Dynamic timing analysis helps
evaluate the design's robustness against real-world conditions.

Timing analysis includes the following steps:

- Path Identification: Identifying critical paths where signal delays are most likely to be
problematic.

- Delay Calculation: Calculating delays through gates, interconnects, and clock paths.

- Setup and Hold Time Verification: Ensuring signals meet setup and hold time requirements at
each flip-flop.

- Clock Domain Crossing Analysis: Verifying proper synchronization of signals that cross clock
domains.
Power Analysis:

Power analysis aims to estimate and optimize the power consumption of a digital circuit. Power
efficiency is crucial to modern electronics, particularly in portable devices. There are different
types of power consumption to consider:

1. Dynamic Power: This is the power consumed due to the charging and discharging of
capacitive loads when signals transition within the circuit. It's the dominant factor in power
consumption during active operations.

2. Static Power (Leakage Power): Static power is the power consumed even when the circuit is
not actively switching. It's primarily due to leakage currents in transistors.

3. Short-Circuit Power: This is the power consumed during the brief period when both NMOS
and PMOS transistors in a CMOS circuit are simultaneously on during a transition.

Power analysis includes the following steps:

- Power Estimation: Calculating power consumption based on circuit activity, switching

frequency, and other factors.

- Power Optimization: Reducing power consumption by optimizing circuit architecture, using low
-power design techniques, and managing clock gating.

-Power Budgeting: Allocating power limits to different components of a system while ensuring
overall system stability.

Q.5 Post layout simulation and final GDS-II generation.

Ans:

Post Layout Simulation:

Post-layout simulation is performed after the physical layout of a circuit has been completed. It
involves simulating the circuit using the actual extracted parasitic elements from the layout.
This step is essential because the parasitics, which include resistances, capacitances, and
inductances of the metal interconnects, impact the circuit's performance. Post-layout
simulation ensures that the circuit's behavior matches the intended functionality, considering
the physical layout's real-world effects.
The main objectives of post-layout simulation include:

- Timing Verification: Ensuring that the design meets timing constraints under real-world
conditions, accounting for the impact of parasitic delays.

- Signal Integrity: Verifying that signal quality is maintained, considering factors like signal
attenuation, reflections, and crosstalk.

- Power and Ground Integrity: Checking for voltage drops and noise on power and ground
networks due to resistive and inductive effects.

- Noise Immunity: Assessing the circuit's immunity to noise generated by neighboring signals
and other sources.

Final GDS-II Generation:

Once the post-layout simulation confirms that the design meets all specifications and
requirements, the final step is to generate the GDS-II (Graphic Design System) file. GDS-II is the
standard file format used to describe the geometric layout of integrated circuits. This file
contains the layout information of the various layers, such as metal, polysilicon, diffusion, and
more.

The GDS-II file generation process involves:

- Converting layout information from the design database into GDS-II format.

- Generating polygons, paths, and other geometric shapes that define the layout of each layer.

- Embedding information about hierarchy, connectivity, and physical properties into the GDS-II
file.

- Ensuring that the GDS-II file adheres to the manufacturing rules and design guidelines provided
by the semiconductor foundry.

The final GDS-II file is then submitted to the foundry for chip fabrication. It serves as the
blueprint that guides the photolithography and manufacturing processes to create the physical
silicon chip based on the design. It's important to ensure that the GDS-II file is accurate and free
of errors, as any mistakes in this stage could lead to defective chips.