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  • Quijada Laboratory6

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    Bautista, Aljhon G.
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    1) This document contains examples and exercises related to timing diagrams, logic gates, and RC circuits used for timing. 2) It asks the reader to determine frequencies from given periods, draw timing diagrams showing signal transitions, and calculate maximum clock frequencies and timing ranges for RC circuits used as timers. 3) Diagrams are provided showing the schematics for RC timer circuits with periods of 1 second and 5 seconds using calculated resistor values.

    Original Description:

    Laboratory 6 for Logic Circuits and Design

    Original Title

    QUIJADA-LABORATORY6

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    1) This document contains examples and exercises related to timing diagrams, logic gates, and RC circuits used for timing. 2) It asks the reader to determine frequencies from given periods, draw timing diagrams showing signal transitions, and calculate maximum clock frequencies and timing ranges for RC circuits used as timers. 3) Diagrams are provided showing the schematics for RC timer circuits with periods of 1 second and 5 seconds using calculated resistor values.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    4 views4 pages

    Quijada Laboratory6

    Uploaded by

    Bautista, Aljhon G.
    1) This document contains examples and exercises related to timing diagrams, logic gates, and RC circuits used for timing. 2) It asks the reader to determine frequencies from given periods, draw timing diagrams showing signal transitions, and calculate maximum clock frequencies and timing ranges for RC circuits used as timers. 3) Diagrams are provided showing the schematics for RC timer circuits with periods of 1 second and 5 seconds using calculated resistor values.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    Alonni Haine Quiad,

    CPE- BA
    Laboratny o
    Revien) Elercises
    1. What is he poriod in seond of the clock with the qiven feauenies?
    a) oo0 Ghert b) 1OMhert c) ooo0 M
    T= ' 1min
    T=
    Lmiy
    CoOsec

    T: \00 nseo f (oo herte


    psec |TDmsec
    a. for the qiven period, Jetermine the frequenc of the clat in Hertz
    b) osO0 nseo c)-msec
    f:'h

    f 0 GHz. f- 1ktz

    3-Acsurne delay for each loaic qate is segonds for the cirant
    euhiloit 33 that input values of Ais low ond Bond C are all at lugic hgh
    traw a timing diagram for a troanition at tine eo hat takes input for O
    fom log1c hiqh to low logic. List iput A,B.C ard output asuel a alues for pins
    nd |0.
    A

    Dutput
    30 35
    A. H he delou d eoch logic aote is b-0 yonose londs, what is the mavimu
    trequenoy that the circuit Aom A-4 Con be reliably clocked in order to insurt proper
    Cperaion?

    Longst delah (l0nsec)(s) = to nsec

    6' A \oo uF Capacitor is used to build tmers. thre timers are to be built with time s of
    1, G and lo Seconds
    a) What resistors hould be chosen to ootain the times provided?
    t< t|o (RC) wuhen t, lsec then ta Ssec when ty ID
    R: e10) c
    R 4090,91
    Resistors for alb: R,=47kQ x2 R,= 36ky2 447kq
    b)
    Ri4.4kn R2 46 4k2
    t 1-lD(4r4)(0)
    t, |·0345 ta 4.944 s tsq.435s
    c) Dow schematic Diagram of the s seond timer
    VESSS

    Triger obutput
    R

    THR
    V
    d) Given tht. Copacitors Wave a berana ot t- lo percent amd esistors have
    a twlerana of 4-s percent,uwhat ranqe of vaues could you espect for yowr timer?

    Romge Vaes for Capauitor


    1 second Timer:
    (1-0)(o.90)(0y6)(o95)4i4 4)4 Achal Value <110(10)(1o0x15)(1-cs)(441o)
    .88 2 Actual Value L 14
    2 Seconds Timer
    (116)(o-q0)(100 xo.4) (454 1o) Achual Valye <Ho( 1Ho 1oxo)(1.o)(4s-4 xio)
    4-27 4 Actual Value < S-17
    3 setnds Timer
    (:10)(0.qo)(00 x1o) (o96)(90-Xo)<Achual Value <110(+1o)(100x(6) (.os) (g0-s xte)
    B-S3< Actual Value Z il's4
    wed to buld docks. Tyuo cocks ore to be bilt
    G.A bouf Capacitor is used with
    periods o 1 and seonds
    a) Usina Volues of esisBors proided in your lab pick to esistors that yeld periods
    as dose to those desired as fossible
    T= doge ime t discharge ting |henT 1s when T = Ss
    T:043(e+R)C t 0-643(R:)c+2R, o443 (0u)
    Rt2R2 14430o|
    S-13(10m)
    R42R43 72150-o7
    -o-
    R42R2: (c) R=R1:4:7k R,= 200 n R 3ok

    T(4) =0-s(44247)ou) T(ss) : b-64a(0042 (s)) (o)


    T(1) =0.935 T(SS) $-o0 s

    b) what is the time on ond time off fr eoch of the clocks during one period?
    at T= Ss

    Charge time :b-b43(476447) (1oo) chorge time o693 (20ot 36*)(Dou)

    dischorge inez b- G93 (47\pou)


    : 33s :2.44s

    c) Draw a scheratiC of the s seond dlock

    TR -Obutput

    THR

    GND

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