EXPERIMENT NO.

9
AIM: - To design and simulation SR flip-flop using VHDL.

Tools Required:- Xilinx 14.7

Theory:
It is a Flip Flop with two inputs, one is S and other is R. S here stands for Set and R here
stands for Reset. Set basically indicates set the flip flop which means output 1 and reset
indicates resetting the flip flop which means output 0. Here clock pulse is supplied to operate
this flop flop, hence it is clocked flip flop.

Block Diagram of SR Flip Flop:

The basic block diagram contains S and R inputs, and between them is clock
pulse, Q and Q’ is the complemented outputs.

SR Flip Flop block diagram

Circuit diagram:

SR Flip Fop using four NAND Gates

Truth table of SR flip flop:

VHDL code of SR- FF

Schematic Design of SR- FF:

Simulation of SR-FF

Result:

All the VHDL codes of SR flip-flop has been simulated and synthesized.

Precautions:

Make sure that there is no syntax and semantic error.