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Features Package
• G3R™ Technology with +15 V Gate Drive D
• Softer RDS(ON) v/s Temperature Dependency
• LoRing™ - Electromagnetically Optimized Design G
• Smaller RG(INT) and Lower QG RoHS
• Low Device Capacitances (COSS, CRSS) KS S
• Superior Cost-Performance Index D = Drain
• Robust Body Diode with Low VF and Low QRR G = Gate
• Industry-Leading UIL & Short-Circuit Robustness TO-247-4 S = Source REACH
KS = Kelvin Source
Advantages Applications
• Compatible with Commercial Gate Drivers • EV Fast Charging
• Low Conduction Losses at all Temperatures • Solar Inverters
• Reduced Ringing • Industrial Motor Drives
• Faster and More Efficient Switching • Transportation
• Lesser Switching Spikes and Lower Losses • Industrial Power Supply
• Better Power Density and System Efficiency • Smart Grid and HVDC
• Ease of Paralleling without Thermal Runaway • Induction Heating and Welding
• Superior Robustness and System Reliability • Pulsed Power
Thermal/Package Characteristics
Values
Parameter Symbol Conditions Unit Note
Min. Typ. Max.
Thermal Resistance, Junction - Case RthJC 0.20 0.26 °C/W Fig. 13
Weight WT 6.2 g
Mounting Torque TM Screws to Heatsink 1.1 Nm
*The chip technology was characterized up to 200 V/ns. The measured dV/dt was limited by measurement test setup and package.
Note 2: Co(er), a lumped capacitance that gives same stored energy as C OSS while V DS is rising from 0 to 1000V.
Co(tr), a lumped capacitance that gives same charging times as COSS while V DS is rising from 0 to 1000V.
Figure 1: Output Characteristics (Tj = 25°C) Figure 2: Output Characteristics (Tj = 175°C)
ID = f(VDS, T);
j tP = 250 µs ID = f(VGS, T);
j tP = 100 µs
Figure 5: On-State Resistance v/s Temperature Figure 6: On-State Resistance v/s Drain Current
Figure 7: Normalized On-State Resistance v/s Temperature Figure 8: On-State Resistance v/s Gate Voltage
RDS(ON) = f(T);
j tP = 250 µs; ID = 75 A; VGS = 15 V RDS(ON) = f(T,V
j GS); tP = 250 µs; I D = 75 A
VGS(th) = f(T);
j VDS = VGS; ID = 60.0 mA ID = 75 A; VDS = 1000 V; Tc = 25°C
Figure 11: Capacitance v/s Drain-Source Voltage Figure 12: Output Capacitor Stored Energy
Figure 13: Transient Thermal Impedance Figure 14: Safe Operating Area (Tc = 25°C)
Figure 15: Current De-rating Curve Figure 16: Power De-rating Curve
Figure 17: Body Diode Characteristics (Tj = 25°C) Figure 18: Body Diode Characteristics (Tj = 175°C)
Figure 19: Third Quadrant Characteristics (Tj = 25°C) Figure 20: Third Quadrant Characteristics (Tj = 175°C)
Figure 21: Inductive Switching Energy v/s Drain Current Figure 22: Inductive Switching Energy v/s Drain Current
(VDD = 1000V) (VDD = 1200V)
Tj = 25°C; VGS = -5/+15V; RG(ext) = 0.5 Ω; L = 32.0µH Tj = 25°C; VGS = -5/+15V; RG(ext) = 0.5 Ω; L = 32.0µH
Figure 23: Inductive Switching Energy v/s RG(ext) Figure 24: Switching Time v/s RG(ext)
(VDD = 1200V) (VDD = 1200V)
Tj = 25°C; VGS = -5/+15V; IDS = 75 A; L = 32.0µH Tj = 25°C; VGS = -5/+15V; IDS = 75 A; L = 32.0µH
Figure 25: Inductive Switching Energy v/s Temperature Figure 26: dV/dt v/s RG(ext)
(VDD = 1200V) (VDD = 1200V)
Tj = 25°C; VGS = -5/+15V; RG(ext) = 0.5 Ω; IDS = 75 A; L = 32.0µH Tj = 25°C; VGS = -5/+15V; IDS = 75 A; L = 32.0µH
VDS
VGS
ID VDD
IG(cont)
QGS QGD
Gate Charge (QG)
90%
Same device as the D.U.T.
LLoad
-5 V VGS 10%
VDS
10% 10%
VDS
VGS
VDD
D.U.T.
RG
90% 90%
ID td(on) td(off)
tr tf
ton toff
VDS
VGS
VDD
D.U.T.
RG
ID
IDS
D.U.T.
LLoad IF
-5 V
trr
IF
0 Level
VGS 90%
VDD
Same device
as the D.U.T. dIrr/dt in 10%
RG Irr
to 90% range
10%
Package Dimensions
TO-247-4 Package Outline
0.62(15.75) 0.19(4.83)
0.516(13.10)
0.635(16.13) 0.205(5.21)
0.557(14.15)
0.5(12.7)
0.216(5.49) 0.487(12.38)
0.236(6.0) 0.075(1.91)
0.25(6.35) 0.529(13.43)
0.085(2.16)
0.037(0.95)
0.049(1.25)
0.237(6.04)
0.248(6.30)
0.145(3.68)
0.2(5.10)
0.64(16.25)
0.695(17.65)
Ø 0.138(3.51)
0.118(3.0) Ø 0.144(3.65)
0.917(23.30)
0.929(23.60)
Ø 0.283(7.18) REF
0.093(2.35)
0.104(2.65)
0.09(2.29)
0.1(2.54)
0.156(3.97)
0.172(4.37)
0.681(17.31)
0.701(17.82)
Ø 0.067(1.7)
0.1(2.54)
G
0.1(2.54) D
0.2(5.08)
S KS
NOTE
1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER.
2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS.
3. THE SOURCE AND KELVIN-SOURCE PINS ARE NOT INTERCHANGABLE. THEIR EXCHANGE MIGHT LEAD TO MALFUNCTION.
Compliance
RoHS Compliance
The levels of RoHS restricted materials in this product are below the maximum concentration values (also referred to as the threshold
limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2011/65/EC (RoHS 2), as
adopted by EU member states on January 2, 2013 and amended on March 31, 2015 by EU Directive 2015/863. RoHS Declarations for this
product can be obtained from your GeneSiC representative.
REACH Compliance
REACH substances of high concern (SVHCs) information is available for this product. Since the European Chemical Agency (ECHA) has
published notice of their intent to frequently revise the SVHC listing for the foreseeable future, please contact a GeneSiC representative to
insure you get the most up-to-date REACH SVHC Declaration. REACH banned substance information (REACH Article 67) is also available
upon request.
Disclaimer
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
Related Links
• SPICE Models: https://www.genesicsemi.com/sic-mosfet/G3R20MT17K/G3R20MT17K_SPICE.zip
• PLECS Models: https://www.genesicsemi.com/sic-mosfet/G3R20MT17K/G3R20MT17K_PLECS.zip
• CAD Models: https://www.genesicsemi.com/sic-mosfet/G3R20MT17K/G3R20MT17K_3D.zip
• Gate Driver Reference: https://www.genesicsemi.com/technical-support
• Evaluation Boards: https://www.genesicsemi.com/technical-support
• Reliability: https://www.genesicsemi.com/reliability
• Compliance: https://www.genesicsemi.com/compliance
• Quality Manual: https://www.genesicsemi.com/quality
Revision History
• Rev 21/May: Updated switching time and switching energy data
• Supersedes: Rev 20/Jun, Rev 20/Sep, Rev 21/Feb
www.genesicsemi.com/sic-mosfet/